MPC8313ERDB_NAND.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
  4. */
  5. /*
  6. * mpc8313epb board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1
  14. #define CONFIG_SPL_INIT_MINIMAL
  15. #define CONFIG_SPL_FLUSH_IMAGE
  16. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  17. #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  18. #ifdef CONFIG_SPL_BUILD
  19. #define CONFIG_NS16550_MIN_FUNCTIONS
  20. #endif
  21. #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  22. #define CONFIG_SPL_MAX_SIZE (4 * 1024)
  23. #define CONFIG_SPL_PAD_TO 0x4000
  24. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  25. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  26. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  27. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  28. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  29. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  30. #ifdef CONFIG_SPL_BUILD
  31. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  32. #endif
  33. #ifndef CONFIG_SYS_MONITOR_BASE
  34. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  35. #endif
  36. #define CONFIG_PCI_INDIRECT_BRIDGE
  37. #define CONFIG_FSL_ELBC 1
  38. /*
  39. * On-board devices
  40. *
  41. * TSEC1 is VSC switch
  42. * TSEC2 is SoC TSEC
  43. */
  44. #define CONFIG_VSC7385_ENET
  45. #define CONFIG_TSEC2
  46. #if !defined(CONFIG_SPL_BUILD)
  47. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  48. #endif
  49. #define CONFIG_SYS_MEMTEST_START 0x00001000
  50. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  51. /* Early revs of this board will lock up hard when attempting
  52. * to access the PMC registers, unless a JTAG debugger is
  53. * connected, or some resistor modifications are made.
  54. */
  55. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  56. /*
  57. * Device configurations
  58. */
  59. /* Vitesse 7385 */
  60. #ifdef CONFIG_VSC7385_ENET
  61. #define CONFIG_TSEC1
  62. /* The flash address and size of the VSC7385 firmware image */
  63. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  64. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  65. #endif
  66. /*
  67. * DDR Setup
  68. */
  69. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  70. /*
  71. * Manually set up DDR parameters, as this board does not
  72. * seem to have the SPD connected to I2C.
  73. */
  74. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  75. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  76. | CSCONFIG_ODT_RD_NEVER \
  77. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  78. | CSCONFIG_ROW_BIT_13 \
  79. | CSCONFIG_COL_BIT_10)
  80. /* 0x80010102 */
  81. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  82. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  83. | (0 << TIMING_CFG0_WRT_SHIFT) \
  84. | (0 << TIMING_CFG0_RRT_SHIFT) \
  85. | (0 << TIMING_CFG0_WWT_SHIFT) \
  86. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  87. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  88. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  89. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  90. /* 0x00220802 */
  91. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  92. | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  93. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  94. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  95. | (10 << TIMING_CFG1_REFREC_SHIFT) \
  96. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  97. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  98. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  99. /* 0x3835a322 */
  100. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  101. | (5 << TIMING_CFG2_CPO_SHIFT) \
  102. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  103. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  104. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  105. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  106. | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  107. /* 0x129048c6 */ /* P9-45,may need tuning */
  108. #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
  109. | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  110. /* 0x05100500 */
  111. #if defined(CONFIG_DDR_2T_TIMING)
  112. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  113. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  114. | SDRAM_CFG_DBW_32 \
  115. | SDRAM_CFG_2T_EN)
  116. /* 0x43088000 */
  117. #else
  118. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  119. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  120. | SDRAM_CFG_DBW_32)
  121. /* 0x43080000 */
  122. #endif
  123. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  124. /* set burst length to 8 for 32-bit data path */
  125. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  126. | (0x0632 << SDRAM_MODE_SD_SHIFT))
  127. /* 0x44480632 */
  128. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  129. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  130. /*0x02000000*/
  131. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  132. | DDRCDR_PZ_NOMZ \
  133. | DDRCDR_NZ_NOMZ \
  134. | DDRCDR_M_ODR)
  135. /*
  136. * FLASH on the Local Bus
  137. */
  138. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  139. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  140. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  141. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  142. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  143. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  144. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  145. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
  146. !defined(CONFIG_SPL_BUILD)
  147. #define CONFIG_SYS_RAMBOOT
  148. #endif
  149. #define CONFIG_SYS_INIT_RAM_LOCK 1
  150. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  151. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  152. #define CONFIG_SYS_GBL_DATA_OFFSET \
  153. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  154. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  155. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  156. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  157. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  158. /* drivers/mtd/nand/raw/nand.c */
  159. #if defined(CONFIG_SPL_BUILD)
  160. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  161. #else
  162. #define CONFIG_SYS_NAND_BASE 0xE2800000
  163. #endif
  164. #define CONFIG_MTD_PARTITION
  165. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  166. #define CONFIG_NAND_FSL_ELBC 1
  167. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  168. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
  169. /* Still needed for spl_minimal.c */
  170. #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
  171. #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
  172. /* local bus write LED / read status buffer (BCSR) mapping */
  173. #define CONFIG_SYS_BCSR_ADDR 0xFA000000
  174. #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
  175. /* map at 0xFA000000 on LCS3 */
  176. /* Vitesse 7385 */
  177. #ifdef CONFIG_VSC7385_ENET
  178. /* VSC7385 Base address on LCS2 */
  179. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  180. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  181. #endif
  182. #define CONFIG_MPC83XX_GPIO 1
  183. /*
  184. * Serial Port
  185. */
  186. #define CONFIG_SYS_NS16550_SERIAL
  187. #define CONFIG_SYS_NS16550_REG_SIZE 1
  188. #define CONFIG_SYS_BAUDRATE_TABLE \
  189. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  190. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  191. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  192. /* I2C */
  193. #define CONFIG_SYS_I2C
  194. #define CONFIG_SYS_I2C_FSL
  195. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  196. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  197. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  198. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  199. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  200. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  201. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  202. /*
  203. * General PCI
  204. * Addresses are mapped 1-1.
  205. */
  206. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  207. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  208. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  209. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  210. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  211. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  212. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  213. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  214. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  215. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  216. /*
  217. * TSEC
  218. */
  219. #define CONFIG_GMII /* MII PHY management */
  220. #ifdef CONFIG_TSEC1
  221. #define CONFIG_HAS_ETH0
  222. #define CONFIG_TSEC1_NAME "TSEC0"
  223. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  224. #define TSEC1_PHY_ADDR 0x1c
  225. #define TSEC1_FLAGS TSEC_GIGABIT
  226. #define TSEC1_PHYIDX 0
  227. #endif
  228. #ifdef CONFIG_TSEC2
  229. #define CONFIG_HAS_ETH1
  230. #define CONFIG_TSEC2_NAME "TSEC1"
  231. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  232. #define TSEC2_PHY_ADDR 4
  233. #define TSEC2_FLAGS TSEC_GIGABIT
  234. #define TSEC2_PHYIDX 0
  235. #endif
  236. /* Options are: TSEC[0-1] */
  237. #define CONFIG_ETHPRIME "TSEC1"
  238. /*
  239. * Configure on-board RTC
  240. */
  241. #define CONFIG_RTC_DS1337
  242. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  243. /*
  244. * Environment
  245. */
  246. #define CONFIG_ENV_OFFSET (512 * 1024)
  247. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  248. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  249. #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
  250. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  251. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  252. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  253. /*
  254. * BOOTP options
  255. */
  256. #define CONFIG_BOOTP_BOOTFILESIZE
  257. /*
  258. * Command line configuration.
  259. */
  260. /*
  261. * Miscellaneous configurable options
  262. */
  263. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  264. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  265. /* Boot Argument Buffer Size */
  266. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  267. /*
  268. * For booting Linux, the board info and command line data
  269. * have to be in the first 256 MB of memory, since this is
  270. * the maximum mapped by the Linux kernel during initialization.
  271. */
  272. /* Initial Memory map for Linux*/
  273. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  274. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  275. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  276. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
  277. /* System IO Config */
  278. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  279. /* Enable Internal USB Phy and GPIO on LCD Connector */
  280. #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
  281. /*
  282. * Environment Configuration
  283. */
  284. #define CONFIG_ENV_OVERWRITE
  285. #define CONFIG_NETDEV "eth1"
  286. #define CONFIG_HOSTNAME "mpc8313erdb"
  287. #define CONFIG_ROOTPATH "/nfs/root/path"
  288. #define CONFIG_BOOTFILE "uImage"
  289. /* U-Boot image on TFTP server */
  290. #define CONFIG_UBOOTPATH "u-boot.bin"
  291. #define CONFIG_FDTFILE "mpc8313erdb.dtb"
  292. /* default location for tftp and bootm */
  293. #define CONFIG_LOADADDR 800000
  294. #define CONFIG_EXTRA_ENV_SETTINGS \
  295. "netdev=" CONFIG_NETDEV "\0" \
  296. "ethprime=TSEC1\0" \
  297. "uboot=" CONFIG_UBOOTPATH "\0" \
  298. "tftpflash=tftpboot $loadaddr $uboot; " \
  299. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  300. " +$filesize; " \
  301. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  302. " +$filesize; " \
  303. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  304. " $filesize; " \
  305. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  306. " +$filesize; " \
  307. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  308. " $filesize\0" \
  309. "fdtaddr=780000\0" \
  310. "fdtfile=" CONFIG_FDTFILE "\0" \
  311. "console=ttyS0\0" \
  312. "setbootargs=setenv bootargs " \
  313. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  314. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  315. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  316. "$netdev:off " \
  317. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  318. #define CONFIG_NFSBOOTCOMMAND \
  319. "setenv rootdev /dev/nfs;" \
  320. "run setbootargs;" \
  321. "run setipargs;" \
  322. "tftp $loadaddr $bootfile;" \
  323. "tftp $fdtaddr $fdtfile;" \
  324. "bootm $loadaddr - $fdtaddr"
  325. #define CONFIG_RAMBOOTCOMMAND \
  326. "setenv rootdev /dev/ram;" \
  327. "run setbootargs;" \
  328. "tftp $ramdiskaddr $ramdiskfile;" \
  329. "tftp $loadaddr $bootfile;" \
  330. "tftp $fdtaddr $fdtfile;" \
  331. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  332. #endif /* __CONFIG_H */