hardware.h 3.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #ifndef _ASM_ARCH_HARDWARE_H
  7. #define _ASM_ARCH_HARDWARE_H
  8. #ifndef __ASSEMBLY__
  9. #include <linux/bitops.h>
  10. #endif
  11. #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
  12. #define ZYNQMP_TCM_SIZE 0x40000
  13. #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
  14. #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
  15. #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
  16. #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
  17. #define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800
  18. #define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
  19. + 0x00000114)
  20. #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
  21. #define ADMA_CH0_BASEADDR 0xFFA80000
  22. #define PS_MODE0 BIT(0)
  23. #define PS_MODE1 BIT(1)
  24. #define PS_MODE2 BIT(2)
  25. #define PS_MODE3 BIT(3)
  26. #define RESET_REASON_DEBUG_SYS BIT(6)
  27. #define RESET_REASON_SOFT BIT(5)
  28. #define RESET_REASON_SRST BIT(4)
  29. #define RESET_REASON_PSONLY BIT(3)
  30. #define RESET_REASON_PMU BIT(2)
  31. #define RESET_REASON_INTERNAL BIT(1)
  32. #define RESET_REASON_EXTERNAL BIT(0)
  33. struct crlapb_regs {
  34. u32 reserved0[36];
  35. u32 cpu_r5_ctrl; /* 0x90 */
  36. u32 reserved1[37];
  37. u32 timestamp_ref_ctrl; /* 0x128 */
  38. u32 reserved2[53];
  39. u32 boot_mode; /* 0x200 */
  40. u32 reserved3_0[7];
  41. u32 reset_reason; /* 0x220 */
  42. u32 reserved3_1[6];
  43. u32 rst_lpd_top; /* 0x23C */
  44. u32 reserved4[4];
  45. u32 boot_pin_ctrl; /* 0x250 */
  46. u32 reserved5[21];
  47. };
  48. #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
  49. #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
  50. #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
  51. #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
  52. struct iou_scntr_secure {
  53. u32 counter_control_register;
  54. u32 reserved0[7];
  55. u32 base_frequency_id_register;
  56. };
  57. #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
  58. #define ZYNQMP_PS_VERSION 0xFFCA0044
  59. #define ZYNQMP_PS_VER_MASK GENMASK(1, 0)
  60. /* Bootmode setting values */
  61. #define BOOT_MODES_MASK 0x0000000F
  62. #define QSPI_MODE_24BIT 0x00000001
  63. #define QSPI_MODE_32BIT 0x00000002
  64. #define SD_MODE 0x00000003 /* sd 0 */
  65. #define SD_MODE1 0x00000005 /* sd 1 */
  66. #define NAND_MODE 0x00000004
  67. #define EMMC_MODE 0x00000006
  68. #define USB_MODE 0x00000007
  69. #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
  70. #define JTAG_MODE 0x00000000
  71. #define BOOT_MODE_USE_ALT 0x100
  72. #define BOOT_MODE_ALT_SHIFT 12
  73. /* SW secondary boot modes 0xa - 0xd */
  74. #define SW_USBHOST_MODE 0x0000000A
  75. #define SW_SATA_MODE 0x0000000B
  76. #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
  77. struct iou_slcr_regs {
  78. u32 mio_pin[78];
  79. u32 reserved[442];
  80. };
  81. #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
  82. #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
  83. struct rpu_regs {
  84. u32 rpu_glbl_ctrl;
  85. u32 reserved0[63];
  86. u32 rpu0_cfg; /* 0x100 */
  87. u32 reserved1[63];
  88. u32 rpu1_cfg; /* 0x200 */
  89. };
  90. #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
  91. #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
  92. struct crfapb_regs {
  93. u32 reserved0[65];
  94. u32 rst_fpd_apu; /* 0x104 */
  95. u32 reserved1;
  96. };
  97. #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
  98. #define ZYNQMP_APU_BASEADDR 0xFD5C0000
  99. struct apu_regs {
  100. u32 reserved0[16];
  101. u32 rvbar_addr0_l; /* 0x40 */
  102. u32 rvbar_addr0_h; /* 0x44 */
  103. u32 reserved1[20];
  104. };
  105. #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
  106. /* Board version value */
  107. #define ZYNQMP_CSU_BASEADDR 0xFFCA0000
  108. #define ZYNQMP_CSU_VERSION_SILICON 0x0
  109. #define ZYNQMP_CSU_VERSION_QEMU 0x3
  110. #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
  111. #define ZYNQMP_SILICON_VER_MASK 0xF
  112. #define ZYNQMP_SILICON_VER_SHIFT 0
  113. struct csu_regs {
  114. u32 reserved0[4];
  115. u32 multi_boot;
  116. u32 reserved1[11];
  117. u32 idcode;
  118. u32 version;
  119. };
  120. #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
  121. #define ZYNQMP_PMU_BASEADDR 0xFFD80000
  122. struct pmu_regs {
  123. u32 reserved[18];
  124. u32 gen_storage6; /* 0x48 */
  125. };
  126. #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
  127. #endif /* _ASM_ARCH_HARDWARE_H */