spr_udc.h 6.2 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __SPR_UDC_H
  24. #define __SPR_UDC_H
  25. /*
  26. * Defines for USBD
  27. *
  28. * The udc_ahb controller has three AHB slaves:
  29. *
  30. * 1. THe UDC registers
  31. * 2. The plug detect
  32. * 3. The RX/TX FIFO
  33. */
  34. #define MAX_ENDPOINTS 16
  35. struct udc_endp_regs {
  36. u32 endp_cntl;
  37. u32 endp_status;
  38. u32 endp_bsorfn;
  39. u32 endp_maxpacksize;
  40. u32 reserved_1;
  41. u32 endp_desc_point;
  42. u32 reserved_2;
  43. u32 write_done;
  44. };
  45. /* Endpoint Control Register definitions */
  46. #define ENDP_CNTL_STALL 0x00000001
  47. #define ENDP_CNTL_FLUSH 0x00000002
  48. #define ENDP_CNTL_SNOOP 0x00000004
  49. #define ENDP_CNTL_POLL 0x00000008
  50. #define ENDP_CNTL_CONTROL 0x00000000
  51. #define ENDP_CNTL_ISO 0x00000010
  52. #define ENDP_CNTL_BULK 0x00000020
  53. #define ENDP_CNTL_INT 0x00000030
  54. #define ENDP_CNTL_NAK 0x00000040
  55. #define ENDP_CNTL_SNAK 0x00000080
  56. #define ENDP_CNTL_CNAK 0x00000100
  57. #define ENDP_CNTL_RRDY 0x00000200
  58. /* Endpoint Satus Register definitions */
  59. #define ENDP_STATUS_PIDMSK 0x0000000f
  60. #define ENDP_STATUS_OUTMSK 0x00000030
  61. #define ENDP_STATUS_OUT_NONE 0x00000000
  62. #define ENDP_STATUS_OUT_DATA 0x00000010
  63. #define ENDP_STATUS_OUT_SETUP 0x00000020
  64. #define ENDP_STATUS_IN 0x00000040
  65. #define ENDP_STATUS_BUFFNAV 0x00000080
  66. #define ENDP_STATUS_FATERR 0x00000100
  67. #define ENDP_STATUS_HOSTBUSERR 0x00000200
  68. #define ENDP_STATUS_TDC 0x00000400
  69. #define ENDP_STATUS_RXPKTMSK 0x003ff800
  70. struct udc_regs {
  71. struct udc_endp_regs in_regs[MAX_ENDPOINTS];
  72. struct udc_endp_regs out_regs[MAX_ENDPOINTS];
  73. u32 dev_conf;
  74. u32 dev_cntl;
  75. u32 dev_stat;
  76. u32 dev_int;
  77. u32 dev_int_mask;
  78. u32 endp_int;
  79. u32 endp_int_mask;
  80. u32 reserved_3[0x39];
  81. u32 reserved_4; /* offset 0x500 */
  82. u32 udc_endp_reg[MAX_ENDPOINTS];
  83. };
  84. /* Device Configuration Register definitions */
  85. #define DEV_CONF_HS_SPEED 0x00000000
  86. #define DEV_CONF_LS_SPEED 0x00000002
  87. #define DEV_CONF_FS_SPEED 0x00000003
  88. #define DEV_CONF_REMWAKEUP 0x00000004
  89. #define DEV_CONF_SELFPOW 0x00000008
  90. #define DEV_CONF_SYNCFRAME 0x00000010
  91. #define DEV_CONF_PHYINT_8 0x00000020
  92. #define DEV_CONF_PHYINT_16 0x00000000
  93. #define DEV_CONF_UTMI_BIDIR 0x00000040
  94. #define DEV_CONF_STATUS_STALL 0x00000080
  95. /* Device Control Register definitions */
  96. #define DEV_CNTL_RESUME 0x00000001
  97. #define DEV_CNTL_TFFLUSH 0x00000002
  98. #define DEV_CNTL_RXDMAEN 0x00000004
  99. #define DEV_CNTL_TXDMAEN 0x00000008
  100. #define DEV_CNTL_DESCRUPD 0x00000010
  101. #define DEV_CNTL_BIGEND 0x00000020
  102. #define DEV_CNTL_BUFFILL 0x00000040
  103. #define DEV_CNTL_TSHLDEN 0x00000080
  104. #define DEV_CNTL_BURSTEN 0x00000100
  105. #define DEV_CNTL_DMAMODE 0x00000200
  106. #define DEV_CNTL_SOFTDISCONNECT 0x00000400
  107. #define DEV_CNTL_SCALEDOWN 0x00000800
  108. #define DEV_CNTL_BURSTLENU 0x00010000
  109. #define DEV_CNTL_BURSTLENMSK 0x00ff0000
  110. #define DEV_CNTL_TSHLDLENU 0x01000000
  111. #define DEV_CNTL_TSHLDLENMSK 0xff000000
  112. /* Device Status Register definitions */
  113. #define DEV_STAT_CFG 0x0000000f
  114. #define DEV_STAT_INTF 0x000000f0
  115. #define DEV_STAT_ALT 0x00000f00
  116. #define DEV_STAT_SUSP 0x00001000
  117. #define DEV_STAT_ENUM 0x00006000
  118. #define DEV_STAT_ENUM_SPEED_HS 0x00000000
  119. #define DEV_STAT_ENUM_SPEED_FS 0x00002000
  120. #define DEV_STAT_ENUM_SPEED_LS 0x00004000
  121. #define DEV_STAT_RXFIFO_EMPTY 0x00008000
  122. #define DEV_STAT_PHY_ERR 0x00010000
  123. #define DEV_STAT_TS 0xf0000000
  124. /* Device Interrupt Register definitions */
  125. #define DEV_INT_MSK 0x0000007f
  126. #define DEV_INT_SETCFG 0x00000001
  127. #define DEV_INT_SETINTF 0x00000002
  128. #define DEV_INT_INACTIVE 0x00000004
  129. #define DEV_INT_USBRESET 0x00000008
  130. #define DEV_INT_SUSPUSB 0x00000010
  131. #define DEV_INT_SOF 0x00000020
  132. #define DEV_INT_ENUM 0x00000040
  133. /* Endpoint Interrupt Register definitions */
  134. #define ENDP0_INT_CTRLIN 0x00000001
  135. #define ENDP1_INT_BULKIN 0x00000002
  136. #define ENDP_INT_NONISOIN_MSK 0x0000AAAA
  137. #define ENDP2_INT_BULKIN 0x00000004
  138. #define ENDP0_INT_CTRLOUT 0x00010000
  139. #define ENDP1_INT_BULKOUT 0x00020000
  140. #define ENDP2_INT_BULKOUT 0x00040000
  141. #define ENDP_INT_NONISOOUT_MSK 0x55540000
  142. /* Endpoint Register definitions */
  143. #define ENDP_EPDIR_OUT 0x00000000
  144. #define ENDP_EPDIR_IN 0x00000010
  145. #define ENDP_EPTYPE_CNTL 0x0
  146. #define ENDP_EPTYPE_ISO 0x1
  147. #define ENDP_EPTYPE_BULK 0x2
  148. #define ENDP_EPTYPE_INT 0x3
  149. /*
  150. * Defines for Plug Detect
  151. */
  152. struct plug_regs {
  153. u32 plug_state;
  154. u32 plug_pending;
  155. };
  156. /* Plug State Register definitions */
  157. #define PLUG_STATUS_EN 0x1
  158. #define PLUG_STATUS_ATTACHED 0x2
  159. #define PLUG_STATUS_PHY_RESET 0x4
  160. #define PLUG_STATUS_PHY_MODE 0x8
  161. /*
  162. * Defines for UDC FIFO (Slave Mode)
  163. */
  164. struct udcfifo_regs {
  165. u32 *fifo_p;
  166. };
  167. /*
  168. * USBTTY definitions
  169. */
  170. #define EP0_MAX_PACKET_SIZE 64
  171. #define UDC_INT_ENDPOINT 1
  172. #define UDC_INT_PACKET_SIZE 64
  173. #define UDC_OUT_ENDPOINT 2
  174. #define UDC_BULK_PACKET_SIZE 64
  175. #define UDC_IN_ENDPOINT 3
  176. #define UDC_OUT_PACKET_SIZE 64
  177. #define UDC_IN_PACKET_SIZE 64
  178. /*
  179. * UDC endpoint definitions
  180. */
  181. #define UDC_EP0 0
  182. #define UDC_EP1 1
  183. #define UDC_EP2 2
  184. #define UDC_EP3 3
  185. /*
  186. * Function declarations
  187. */
  188. void udc_irq(void);
  189. void udc_set_nak(int epid);
  190. void udc_unset_nak(int epid);
  191. int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
  192. int udc_init(void);
  193. void udc_enable(struct usb_device_instance *device);
  194. void udc_disable(void);
  195. void udc_connect(void);
  196. void udc_disconnect(void);
  197. void udc_startup_events(struct usb_device_instance *device);
  198. void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
  199. struct usb_endpoint_instance *endpoint);
  200. #endif /* __SPR_UDC_H */