spr_smi.h 4.0 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef SPR_SMI_H
  24. #define SPR_SMI_H
  25. /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */
  26. /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */
  27. #define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE
  28. #define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE
  29. #define SMIBANK0_BASE (FLASH_START_ADDRESS)
  30. #define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE)
  31. #define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE)
  32. #define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE)
  33. #define BANK0 0
  34. #define BANK1 1
  35. #define BANK2 2
  36. #define BANK3 3
  37. struct smi_regs {
  38. u32 smi_cr1;
  39. u32 smi_cr2;
  40. u32 smi_sr;
  41. u32 smi_tr;
  42. u32 smi_rr;
  43. };
  44. /* CONTROL REG 1 */
  45. #define BANK_EN 0x0000000F /* enables all banks */
  46. #define DSEL_TIME 0x00000060 /* Deselect time */
  47. #define PRESCAL5 0x00000500 /* AHB_CK prescaling value */
  48. #define PRESCALA 0x00000A00 /* AHB_CK prescaling value */
  49. #define PRESCAL3 0x00000300 /* AHB_CK prescaling value */
  50. #define PRESCAL4 0x00000400 /* AHB_CK prescaling value */
  51. #define SW_MODE 0x10000000 /* enables SW Mode */
  52. #define WB_MODE 0x20000000 /* Write Burst Mode */
  53. #define FAST_MODE 0x00008000 /* Fast Mode */
  54. #define HOLD1 0x00010000
  55. /* CONTROL REG 2 */
  56. #define RD_STATUS_REG 0x00000400 /* reads status reg */
  57. #define WE 0x00000800 /* Write Enable */
  58. #define BANK0_SEL 0x00000000 /* Select Banck0 */
  59. #define BANK1_SEL 0x00001000 /* Select Banck1 */
  60. #define BANK2_SEL 0x00002000 /* Select Banck2 */
  61. #define BANK3_SEL 0x00003000 /* Select Banck3 */
  62. #define BANKSEL_SHIFT 12
  63. #define SEND 0x00000080 /* Send data */
  64. #define TX_LEN_1 0x00000001 /* data length = 1 byte */
  65. #define TX_LEN_2 0x00000002 /* data length = 2 byte */
  66. #define TX_LEN_3 0x00000003 /* data length = 3 byte */
  67. #define TX_LEN_4 0x00000004 /* data length = 4 byte */
  68. #define RX_LEN_1 0x00000010 /* data length = 1 byte */
  69. #define RX_LEN_2 0x00000020 /* data length = 2 byte */
  70. #define RX_LEN_3 0x00000030 /* data length = 3 byte */
  71. #define RX_LEN_4 0x00000040 /* data length = 4 byte */
  72. #define TFIE 0x00000100 /* Tx Flag Interrupt Enable */
  73. #define WCIE 0x00000200 /* WCF Interrupt Enable */
  74. /* STATUS_REG */
  75. #define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */
  76. #define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */
  77. #define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */
  78. #define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */
  79. #define RSR 0x00000005 /* Read Status regiser */
  80. #define TFF 0x00000100 /* Transfer Finished FLag */
  81. #define WCF 0x00000200 /* Transfer Finished FLag */
  82. #define ERF1 0x00000400 /* Error Flag 1 */
  83. #define ERF2 0x00000800 /* Error Flag 2 */
  84. #define WM0 0x00001000 /* WM Bank 0 */
  85. #define WM1 0x00002000 /* WM Bank 1 */
  86. #define WM2 0x00004000 /* WM Bank 2 */
  87. #define WM3 0x00008000 /* WM Bank 3 */
  88. #define WM_SHIFT 12
  89. /* TR REG */
  90. #define READ_ID 0x0000009F /* Read Identification */
  91. #define BULK_ERASE 0x000000C7 /* BULK erase */
  92. #define SECTOR_ERASE 0x000000D8 /* SECTOR erase */
  93. #define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */
  94. struct flash_dev {
  95. u32 density;
  96. ulong size;
  97. ushort sector_count;
  98. };
  99. #define SFLASH_PAGE_SIZE 0x100 /* flash page size */
  100. #define XFER_FINISH_TOUT 2 /* xfer finish timeout */
  101. #define WMODE_TOUT 2 /* write enable timeout */
  102. #endif