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- /*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
- #ifndef __SPR_NAND_H__
- #define __SPR_NAND_H__
- struct fsmc_regs {
- u32 reserved_1[0x10];
- u32 genmemctrl_pc;
- u32 reserved_2;
- u32 genmemctrl_comm;
- u32 genmemctrl_attrib;
- u32 reserved_3;
- u32 genmemctrl_ecc;
- };
- /* genmemctrl_pc register definitions */
- #define FSMC_RESET (1 << 0)
- #define FSMC_WAITON (1 << 1)
- #define FSMC_ENABLE (1 << 2)
- #define FSMC_DEVTYPE_NAND (1 << 3)
- #define FSMC_DEVWID_8 (0 << 4)
- #define FSMC_DEVWID_16 (1 << 4)
- #define FSMC_ECCEN (1 << 6)
- #define FSMC_ECCPLEN_512 (0 << 7)
- #define FSMC_ECCPLEN_256 (1 << 7)
- #define FSMC_TCLR_1 (1 << 9)
- #define FSMC_TAR_1 (1 << 13)
- /* genmemctrl_comm register definitions */
- #define FSMC_TSET_0 (0 << 0)
- #define FSMC_TWAIT_6 (6 << 8)
- #define FSMC_THOLD_4 (4 << 16)
- #define FSMC_THIZ_1 (1 << 24)
- extern int spear_nand_init(struct nand_chip *nand);
- #endif
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