spr_udc.c 26 KB

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  1. /*
  2. * Based on drivers/usb/gadget/omap1510_udc.c
  3. * TI OMAP1510 USB bus interface driver
  4. *
  5. * (C) Copyright 2009
  6. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <asm/io.h>
  28. #include <usbdevice.h>
  29. #include "ep0.h"
  30. #include <usb/spr_udc.h>
  31. #include <asm/arch/hardware.h>
  32. #include <asm/arch/spr_misc.h>
  33. #define UDC_INIT_MDELAY 80 /* Device settle delay */
  34. /* Some kind of debugging output... */
  35. #ifndef DEBUG_SPRUSBTTY
  36. #define UDCDBG(str)
  37. #define UDCDBGA(fmt, args...)
  38. #else
  39. #define UDCDBG(str) serial_printf(str "\n")
  40. #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
  41. #endif
  42. static struct urb *ep0_urb;
  43. static struct usb_device_instance *udc_device;
  44. static struct plug_regs *const plug_regs_p =
  45. (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
  46. static struct udc_regs *const udc_regs_p =
  47. (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
  48. static struct udc_endp_regs *const outep_regs_p =
  49. &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
  50. static struct udc_endp_regs *const inep_regs_p =
  51. &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
  52. /*
  53. * udc_state_transition - Write the next packet to TxFIFO.
  54. * @initial: Initial state.
  55. * @final: Final state.
  56. *
  57. * Helper function to implement device state changes. The device states and
  58. * the events that transition between them are:
  59. *
  60. * STATE_ATTACHED
  61. * || /\
  62. * \/ ||
  63. * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
  64. * || /\
  65. * \/ ||
  66. * STATE_POWERED
  67. * || /\
  68. * \/ ||
  69. * DEVICE_RESET DEVICE_POWER_INTERRUPTION
  70. * || /\
  71. * \/ ||
  72. * STATE_DEFAULT
  73. * || /\
  74. * \/ ||
  75. * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
  76. * || /\
  77. * \/ ||
  78. * STATE_ADDRESSED
  79. * || /\
  80. * \/ ||
  81. * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
  82. * || /\
  83. * \/ ||
  84. * STATE_CONFIGURED
  85. *
  86. * udc_state_transition transitions up (in the direction from STATE_ATTACHED
  87. * to STATE_CONFIGURED) from the specified initial state to the specified final
  88. * state, passing through each intermediate state on the way. If the initial
  89. * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
  90. * no state transitions will take place.
  91. *
  92. * udc_state_transition also transitions down (in the direction from
  93. * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
  94. * specified final state, passing through each intermediate state on the way.
  95. * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
  96. * state, then no state transitions will take place.
  97. *
  98. * This function must only be called with interrupts disabled.
  99. */
  100. static void udc_state_transition(usb_device_state_t initial,
  101. usb_device_state_t final)
  102. {
  103. if (initial < final) {
  104. switch (initial) {
  105. case STATE_ATTACHED:
  106. usbd_device_event_irq(udc_device,
  107. DEVICE_HUB_CONFIGURED, 0);
  108. if (final == STATE_POWERED)
  109. break;
  110. case STATE_POWERED:
  111. usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
  112. if (final == STATE_DEFAULT)
  113. break;
  114. case STATE_DEFAULT:
  115. usbd_device_event_irq(udc_device,
  116. DEVICE_ADDRESS_ASSIGNED, 0);
  117. if (final == STATE_ADDRESSED)
  118. break;
  119. case STATE_ADDRESSED:
  120. usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
  121. case STATE_CONFIGURED:
  122. break;
  123. default:
  124. break;
  125. }
  126. } else if (initial > final) {
  127. switch (initial) {
  128. case STATE_CONFIGURED:
  129. usbd_device_event_irq(udc_device,
  130. DEVICE_DE_CONFIGURED, 0);
  131. if (final == STATE_ADDRESSED)
  132. break;
  133. case STATE_ADDRESSED:
  134. usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
  135. if (final == STATE_DEFAULT)
  136. break;
  137. case STATE_DEFAULT:
  138. usbd_device_event_irq(udc_device,
  139. DEVICE_POWER_INTERRUPTION, 0);
  140. if (final == STATE_POWERED)
  141. break;
  142. case STATE_POWERED:
  143. usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
  144. case STATE_ATTACHED:
  145. break;
  146. default:
  147. break;
  148. }
  149. }
  150. }
  151. /* Stall endpoint */
  152. static void udc_stall_ep(u32 ep_num)
  153. {
  154. writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
  155. &inep_regs_p[ep_num].endp_cntl);
  156. writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
  157. &outep_regs_p[ep_num].endp_cntl);
  158. }
  159. static void *get_fifo(int ep_num, int in)
  160. {
  161. u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
  162. switch (ep_num) {
  163. case UDC_EP3:
  164. fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
  165. /* break intentionally left out */
  166. case UDC_EP1:
  167. fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
  168. /* break intentionally left out */
  169. case UDC_EP0:
  170. default:
  171. if (in) {
  172. fifo_ptr +=
  173. readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
  174. /* break intentionally left out */
  175. } else {
  176. break;
  177. }
  178. case UDC_EP2:
  179. fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
  180. /* break intentionally left out */
  181. }
  182. return (void *)fifo_ptr;
  183. }
  184. static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
  185. {
  186. u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
  187. u32 i, nw, nb;
  188. u32 *wrdp;
  189. u8 *bytp;
  190. if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
  191. return -1;
  192. nw = len / sizeof(u32);
  193. nb = len % sizeof(u32);
  194. wrdp = (u32 *)bufp;
  195. for (i = 0; i < nw; i++) {
  196. writel(readl(fifo_ptr), wrdp);
  197. wrdp++;
  198. }
  199. bytp = (u8 *)wrdp;
  200. for (i = 0; i < nb; i++) {
  201. writeb(readb(fifo_ptr), bytp);
  202. fifo_ptr++;
  203. bytp++;
  204. }
  205. readl(&outep_regs_p[epNum].write_done);
  206. return 0;
  207. }
  208. static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
  209. {
  210. u32 i, nw, nb;
  211. u32 *wrdp;
  212. u8 *bytp;
  213. u8 *fifo_ptr = get_fifo(epNum, 1);
  214. nw = len / sizeof(int);
  215. nb = len % sizeof(int);
  216. wrdp = (u32 *)bufp;
  217. for (i = 0; i < nw; i++) {
  218. writel(*wrdp, fifo_ptr);
  219. wrdp++;
  220. }
  221. bytp = (u8 *)wrdp;
  222. for (i = 0; i < nb; i++) {
  223. writeb(*bytp, fifo_ptr);
  224. fifo_ptr++;
  225. bytp++;
  226. }
  227. }
  228. /*
  229. * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO.
  230. * @endpoint: Endpoint pointer.
  231. *
  232. * If the endpoint has an active tx_urb, then the next packet of data from the
  233. * URB is written to the tx FIFO. The total amount of data in the urb is given
  234. * by urb->actual_length. The maximum amount of data that can be sent in any
  235. * one packet is given by endpoint->tx_packetSize. The number of data bytes
  236. * from this URB that have already been transmitted is given by endpoint->sent.
  237. * endpoint->last is updated by this routine with the number of data bytes
  238. * transmitted in this packet.
  239. *
  240. */
  241. static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance
  242. *endpoint)
  243. {
  244. struct urb *urb = endpoint->tx_urb;
  245. int align;
  246. if (urb) {
  247. u32 last;
  248. UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
  249. urb->buffer, urb->buffer_length, urb->actual_length);
  250. last = MIN(urb->actual_length - endpoint->sent,
  251. endpoint->tx_packetSize);
  252. if (last) {
  253. u8 *cp = urb->buffer + endpoint->sent;
  254. /*
  255. * This ensures that USBD packet fifo is accessed
  256. * - through word aligned pointer or
  257. * - through non word aligned pointer but only
  258. * with a max length to make the next packet
  259. * word aligned
  260. */
  261. align = ((ulong)cp % sizeof(int));
  262. if (align)
  263. last = MIN(last, sizeof(int) - align);
  264. UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
  265. endpoint->sent, endpoint->tx_packetSize, last);
  266. usbputpcktofifo(endpoint->endpoint_address &
  267. USB_ENDPOINT_NUMBER_MASK, cp, last);
  268. }
  269. endpoint->last = last;
  270. }
  271. }
  272. /*
  273. * Handle SETUP USB interrupt.
  274. * This function implements TRM Figure 14-14.
  275. */
  276. static void spear_udc_setup(struct usb_endpoint_instance *endpoint)
  277. {
  278. u8 *datap = (u8 *)&ep0_urb->device_request;
  279. int ep_addr = endpoint->endpoint_address;
  280. UDCDBG("-> Entering device setup");
  281. usbgetpckfromfifo(ep_addr, datap, 8);
  282. /* Try to process setup packet */
  283. if (ep0_recv_setup(ep0_urb)) {
  284. /* Not a setup packet, stall next EP0 transaction */
  285. udc_stall_ep(0);
  286. UDCDBG("can't parse setup packet, still waiting for setup");
  287. return;
  288. }
  289. /* Check direction */
  290. if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
  291. == USB_REQ_HOST2DEVICE) {
  292. UDCDBG("control write on EP0");
  293. if (le16_to_cpu(ep0_urb->device_request.wLength)) {
  294. /* Stall this request */
  295. UDCDBG("Stalling unsupported EP0 control write data "
  296. "stage.");
  297. udc_stall_ep(0);
  298. }
  299. } else {
  300. UDCDBG("control read on EP0");
  301. /*
  302. * The ep0_recv_setup function has already placed our response
  303. * packet data in ep0_urb->buffer and the packet length in
  304. * ep0_urb->actual_length.
  305. */
  306. endpoint->tx_urb = ep0_urb;
  307. endpoint->sent = 0;
  308. /*
  309. * Write packet data to the FIFO. spear_write_noniso_tx_fifo
  310. * will update endpoint->last with the number of bytes written
  311. * to the FIFO.
  312. */
  313. spear_write_noniso_tx_fifo(endpoint);
  314. writel(0x0, &inep_regs_p[ep_addr].write_done);
  315. }
  316. udc_unset_nak(endpoint->endpoint_address);
  317. UDCDBG("<- Leaving device setup");
  318. }
  319. /*
  320. * Handle endpoint 0 RX interrupt
  321. */
  322. static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
  323. {
  324. u8 dummy[64];
  325. UDCDBG("RX on EP0");
  326. /* Check direction */
  327. if ((ep0_urb->device_request.bmRequestType
  328. & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
  329. /*
  330. * This rx interrupt must be for a control write data
  331. * stage packet.
  332. *
  333. * We don't support control write data stages.
  334. * We should never end up here.
  335. */
  336. UDCDBG("Stalling unexpected EP0 control write "
  337. "data stage packet");
  338. udc_stall_ep(0);
  339. } else {
  340. /*
  341. * This rx interrupt must be for a control read status
  342. * stage packet.
  343. */
  344. UDCDBG("ACK on EP0 control read status stage packet");
  345. u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
  346. usbgetpckfromfifo(0, dummy, len);
  347. }
  348. }
  349. /*
  350. * Handle endpoint 0 TX interrupt
  351. */
  352. static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
  353. {
  354. struct usb_device_request *request = &ep0_urb->device_request;
  355. int ep_addr;
  356. UDCDBG("TX on EP0");
  357. /* Check direction */
  358. if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
  359. USB_REQ_HOST2DEVICE) {
  360. /*
  361. * This tx interrupt must be for a control write status
  362. * stage packet.
  363. */
  364. UDCDBG("ACK on EP0 control write status stage packet");
  365. } else {
  366. /*
  367. * This tx interrupt must be for a control read data
  368. * stage packet.
  369. */
  370. int wLength = le16_to_cpu(request->wLength);
  371. /*
  372. * Update our count of bytes sent so far in this
  373. * transfer.
  374. */
  375. endpoint->sent += endpoint->last;
  376. /*
  377. * We are finished with this transfer if we have sent
  378. * all of the bytes in our tx urb (urb->actual_length)
  379. * unless we need a zero-length terminating packet. We
  380. * need a zero-length terminating packet if we returned
  381. * fewer bytes than were requested (wLength) by the host,
  382. * and the number of bytes we returned is an exact
  383. * multiple of the packet size endpoint->tx_packetSize.
  384. */
  385. if ((endpoint->sent == ep0_urb->actual_length) &&
  386. ((ep0_urb->actual_length == wLength) ||
  387. (endpoint->last != endpoint->tx_packetSize))) {
  388. /* Done with control read data stage. */
  389. UDCDBG("control read data stage complete");
  390. } else {
  391. /*
  392. * We still have another packet of data to send
  393. * in this control read data stage or else we
  394. * need a zero-length terminating packet.
  395. */
  396. UDCDBG("ACK control read data stage packet");
  397. spear_write_noniso_tx_fifo(endpoint);
  398. ep_addr = endpoint->endpoint_address;
  399. writel(0x0, &inep_regs_p[ep_addr].write_done);
  400. }
  401. }
  402. }
  403. static struct usb_endpoint_instance *spear_find_ep(int ep)
  404. {
  405. int i;
  406. for (i = 0; i < udc_device->bus->max_endpoints; i++) {
  407. if ((udc_device->bus->endpoint_array[i].endpoint_address &
  408. USB_ENDPOINT_NUMBER_MASK) == ep)
  409. return &udc_device->bus->endpoint_array[i];
  410. }
  411. return NULL;
  412. }
  413. /*
  414. * Handle RX transaction on non-ISO endpoint.
  415. * The ep argument is a physical endpoint number for a non-ISO IN endpoint
  416. * in the range 1 to 15.
  417. */
  418. static void spear_udc_epn_rx(int ep)
  419. {
  420. int nbytes = 0;
  421. struct urb *urb;
  422. struct usb_endpoint_instance *endpoint = spear_find_ep(ep);
  423. if (endpoint) {
  424. urb = endpoint->rcv_urb;
  425. if (urb) {
  426. u8 *cp = urb->buffer + urb->actual_length;
  427. nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
  428. 0xfff;
  429. usbgetpckfromfifo(ep, cp, nbytes);
  430. usbd_rcv_complete(endpoint, nbytes, 0);
  431. }
  432. }
  433. }
  434. /*
  435. * Handle TX transaction on non-ISO endpoint.
  436. * The ep argument is a physical endpoint number for a non-ISO IN endpoint
  437. * in the range 16 to 30.
  438. */
  439. static void spear_udc_epn_tx(int ep)
  440. {
  441. struct usb_endpoint_instance *endpoint = spear_find_ep(ep);
  442. /*
  443. * We need to transmit a terminating zero-length packet now if
  444. * we have sent all of the data in this URB and the transfer
  445. * size was an exact multiple of the packet size.
  446. */
  447. if (endpoint && endpoint->tx_urb && endpoint->tx_urb->actual_length) {
  448. if (endpoint->last == endpoint->tx_packetSize) {
  449. /* handle zero length packet here */
  450. writel(0x0, &inep_regs_p[ep].write_done);
  451. }
  452. /* retire the data that was just sent */
  453. usbd_tx_complete(endpoint);
  454. /*
  455. * Check to see if we have more data ready to transmit
  456. * now.
  457. */
  458. if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
  459. /* write data to FIFO */
  460. spear_write_noniso_tx_fifo(endpoint);
  461. writel(0x0, &inep_regs_p[ep].write_done);
  462. } else if (endpoint->tx_urb
  463. && (endpoint->tx_urb->actual_length == 0)) {
  464. /* udc_set_nak(ep); */
  465. }
  466. }
  467. }
  468. /*
  469. * Start of public functions.
  470. */
  471. /* Called to start packet transmission. */
  472. int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
  473. {
  474. udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
  475. return 0;
  476. }
  477. /* Start to initialize h/w stuff */
  478. int udc_init(void)
  479. {
  480. int i;
  481. u32 plug_st;
  482. udc_device = NULL;
  483. UDCDBG("starting");
  484. readl(&plug_regs_p->plug_pending);
  485. udc_disconnect();
  486. for (i = 0; i < UDC_INIT_MDELAY; i++)
  487. udelay(1000);
  488. plug_st = readl(&plug_regs_p->plug_state);
  489. writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
  490. writel(~0x0, &udc_regs_p->endp_int);
  491. writel(~0x0, &udc_regs_p->dev_int_mask);
  492. writel(~0x0, &udc_regs_p->endp_int_mask);
  493. writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
  494. /* Dev_Conf_SYNCFRAME | */
  495. DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
  496. writel(0x0, &udc_regs_p->dev_cntl);
  497. /* Clear all interrupts pending */
  498. writel(DEV_INT_MSK, &udc_regs_p->dev_int);
  499. return 0;
  500. }
  501. /*
  502. * udc_setup_ep - setup endpoint
  503. * Associate a physical endpoint with endpoint_instance
  504. */
  505. void udc_setup_ep(struct usb_device_instance *device,
  506. u32 ep, struct usb_endpoint_instance *endpoint)
  507. {
  508. UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
  509. int ep_addr;
  510. int ep_num, ep_type;
  511. int packet_size;
  512. int buffer_size;
  513. int attributes;
  514. char *tt;
  515. u32 endp_intmask;
  516. tt = getenv("usbtty");
  517. if (!tt)
  518. tt = "generic";
  519. ep_addr = endpoint->endpoint_address;
  520. ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
  521. if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  522. /* IN endpoint */
  523. packet_size = endpoint->tx_packetSize;
  524. buffer_size = packet_size * 2;
  525. attributes = endpoint->tx_attributes;
  526. } else {
  527. /* OUT endpoint */
  528. packet_size = endpoint->rcv_packetSize;
  529. buffer_size = packet_size * 2;
  530. attributes = endpoint->rcv_attributes;
  531. }
  532. switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
  533. case USB_ENDPOINT_XFER_CONTROL:
  534. ep_type = ENDP_EPTYPE_CNTL;
  535. break;
  536. case USB_ENDPOINT_XFER_BULK:
  537. default:
  538. ep_type = ENDP_EPTYPE_BULK;
  539. break;
  540. case USB_ENDPOINT_XFER_INT:
  541. ep_type = ENDP_EPTYPE_INT;
  542. break;
  543. case USB_ENDPOINT_XFER_ISOC:
  544. ep_type = ENDP_EPTYPE_ISO;
  545. break;
  546. }
  547. struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
  548. struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
  549. if (!ep_addr) {
  550. /* Setup endpoint 0 */
  551. buffer_size = packet_size;
  552. writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
  553. &in_p->endp_cntl);
  554. writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
  555. &out_p->endp_cntl);
  556. writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
  557. writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
  558. writel(packet_size, &in_p->endp_maxpacksize);
  559. writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
  560. writel(packet_size | ((buffer_size / sizeof(int)) << 16),
  561. &out_p->endp_maxpacksize);
  562. writel((packet_size << 19) | ENDP_EPTYPE_CNTL,
  563. &udc_regs_p->udc_endp_reg[ep_num]);
  564. } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  565. /* Setup the IN endpoint */
  566. writel(0x0, &in_p->endp_status);
  567. writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
  568. writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
  569. writel(packet_size, &in_p->endp_maxpacksize);
  570. if (!strcmp(tt, "cdc_acm")) {
  571. if (ep_type == ENDP_EPTYPE_INT) {
  572. /* Conf no. 1 Interface no. 0 */
  573. writel((packet_size << 19) |
  574. ENDP_EPDIR_IN | (1 << 7) |
  575. (0 << 11) | (ep_type << 5) | ep_num,
  576. &udc_regs_p->udc_endp_reg[ep_num]);
  577. } else {
  578. /* Conf no. 1 Interface no. 1 */
  579. writel((packet_size << 19) |
  580. ENDP_EPDIR_IN | (1 << 7) |
  581. (1 << 11) | (ep_type << 5) | ep_num,
  582. &udc_regs_p->udc_endp_reg[ep_num]);
  583. }
  584. } else {
  585. /* Conf no. 1 Interface no. 0 */
  586. writel((packet_size << 19) |
  587. ENDP_EPDIR_IN | (1 << 7) |
  588. (0 << 11) | (ep_type << 5) | ep_num,
  589. &udc_regs_p->udc_endp_reg[ep_num]);
  590. }
  591. } else {
  592. /* Setup the OUT endpoint */
  593. writel(0x0, &out_p->endp_status);
  594. writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
  595. writel(packet_size | ((buffer_size / sizeof(int)) << 16),
  596. &out_p->endp_maxpacksize);
  597. if (!strcmp(tt, "cdc_acm")) {
  598. writel((packet_size << 19) |
  599. ENDP_EPDIR_OUT | (1 << 7) |
  600. (1 << 11) | (ep_type << 5) | ep_num,
  601. &udc_regs_p->udc_endp_reg[ep_num]);
  602. } else {
  603. writel((packet_size << 19) |
  604. ENDP_EPDIR_OUT | (1 << 7) |
  605. (0 << 11) | (ep_type << 5) | ep_num,
  606. &udc_regs_p->udc_endp_reg[ep_num]);
  607. }
  608. }
  609. endp_intmask = readl(&udc_regs_p->endp_int_mask);
  610. endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
  611. writel(endp_intmask, &udc_regs_p->endp_int_mask);
  612. }
  613. /* Turn on the USB connection by enabling the pullup resistor */
  614. void udc_connect(void)
  615. {
  616. u32 plug_st;
  617. plug_st = readl(&plug_regs_p->plug_state);
  618. plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
  619. writel(plug_st, &plug_regs_p->plug_state);
  620. }
  621. /* Turn off the USB connection by disabling the pullup resistor */
  622. void udc_disconnect(void)
  623. {
  624. u32 plug_st;
  625. plug_st = readl(&plug_regs_p->plug_state);
  626. plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
  627. writel(plug_st, &plug_regs_p->plug_state);
  628. }
  629. /* Switch on the UDC */
  630. void udc_enable(struct usb_device_instance *device)
  631. {
  632. UDCDBGA("enable device %p, status %d", device, device->status);
  633. /* Save the device structure pointer */
  634. udc_device = device;
  635. /* Setup ep0 urb */
  636. if (!ep0_urb) {
  637. ep0_urb =
  638. usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
  639. } else {
  640. serial_printf("udc_enable: ep0_urb already allocated %p\n",
  641. ep0_urb);
  642. }
  643. writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
  644. }
  645. /**
  646. * udc_startup - allow udc code to do any additional startup
  647. */
  648. void udc_startup_events(struct usb_device_instance *device)
  649. {
  650. /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
  651. usbd_device_event_irq(device, DEVICE_INIT, 0);
  652. /*
  653. * The DEVICE_CREATE event puts the USB device in the state
  654. * STATE_ATTACHED.
  655. */
  656. usbd_device_event_irq(device, DEVICE_CREATE, 0);
  657. /*
  658. * Some USB controller driver implementations signal
  659. * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
  660. * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
  661. * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
  662. * The SPEAr USB client controller has the capability to detect when the
  663. * USB cable is connected to a powered USB bus, so we will defer the
  664. * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
  665. */
  666. udc_enable(device);
  667. }
  668. /*
  669. * Plug detection interrupt handling
  670. */
  671. void spear_udc_plug_irq(void)
  672. {
  673. if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
  674. /*
  675. * USB cable attached
  676. * Turn off PHY reset bit (PLUG detect).
  677. * Switch PHY opmode to normal operation (PLUG detect).
  678. */
  679. udc_connect();
  680. writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
  681. UDCDBG("device attached and powered");
  682. udc_state_transition(udc_device->device_state, STATE_POWERED);
  683. } else {
  684. /*
  685. * USB cable detached
  686. * Reset the PHY and switch the mode.
  687. */
  688. udc_disconnect();
  689. writel(~0x0, &udc_regs_p->dev_int_mask);
  690. UDCDBG("device detached or unpowered");
  691. udc_state_transition(udc_device->device_state, STATE_ATTACHED);
  692. }
  693. }
  694. /*
  695. * Device interrupt handling
  696. */
  697. void spear_udc_dev_irq(void)
  698. {
  699. if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
  700. writel(~0x0, &udc_regs_p->endp_int_mask);
  701. udc_connect();
  702. writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
  703. &inep_regs_p[0].endp_cntl);
  704. writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
  705. UDCDBG("device reset in progess");
  706. udc_state_transition(udc_device->device_state, STATE_DEFAULT);
  707. }
  708. /* Device Enumeration completed */
  709. if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
  710. writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
  711. /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
  712. writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
  713. &udc_regs_p->endp_int_mask);
  714. UDCDBG("default -> addressed");
  715. udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
  716. }
  717. /* The USB will be in SUSPEND in 3 ms */
  718. if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
  719. writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
  720. UDCDBG("entering inactive state");
  721. /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
  722. }
  723. /* SetConfiguration command received */
  724. if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
  725. writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
  726. UDCDBG("entering configured state");
  727. udc_state_transition(udc_device->device_state,
  728. STATE_CONFIGURED);
  729. }
  730. /* SetInterface command received */
  731. if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF)
  732. writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
  733. /* USB Suspend detected on cable */
  734. if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
  735. writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
  736. UDCDBG("entering suspended state");
  737. usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
  738. }
  739. /* USB Start-Of-Frame detected on cable */
  740. if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF)
  741. writel(DEV_INT_SOF, &udc_regs_p->dev_int);
  742. }
  743. /*
  744. * Endpoint interrupt handling
  745. */
  746. void spear_udc_endpoint_irq(void)
  747. {
  748. while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
  749. writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
  750. if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
  751. == ENDP_STATUS_OUT_SETUP) {
  752. spear_udc_setup(udc_device->bus->endpoint_array + 0);
  753. writel(ENDP_STATUS_OUT_SETUP,
  754. &outep_regs_p[0].endp_status);
  755. } else if ((readl(&outep_regs_p[0].endp_status) &
  756. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
  757. spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
  758. writel(ENDP_STATUS_OUT_DATA,
  759. &outep_regs_p[0].endp_status);
  760. } else if ((readl(&outep_regs_p[0].endp_status) &
  761. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
  762. /* NONE received */
  763. }
  764. writel(0x0, &outep_regs_p[0].endp_status);
  765. }
  766. if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
  767. spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
  768. writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
  769. writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
  770. }
  771. while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
  772. u32 epnum = 0;
  773. u32 ep_int = readl(&udc_regs_p->endp_int) &
  774. ENDP_INT_NONISOOUT_MSK;
  775. ep_int >>= 16;
  776. while (0x0 == (ep_int & 0x1)) {
  777. ep_int >>= 1;
  778. epnum++;
  779. }
  780. writel((1 << 16) << epnum, &udc_regs_p->endp_int);
  781. if ((readl(&outep_regs_p[epnum].endp_status) &
  782. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
  783. spear_udc_epn_rx(epnum);
  784. writel(ENDP_STATUS_OUT_DATA,
  785. &outep_regs_p[epnum].endp_status);
  786. } else if ((readl(&outep_regs_p[epnum].endp_status) &
  787. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
  788. writel(0x0, &outep_regs_p[epnum].endp_status);
  789. }
  790. }
  791. if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
  792. u32 epnum = 0;
  793. u32 ep_int = readl(&udc_regs_p->endp_int) &
  794. ENDP_INT_NONISOIN_MSK;
  795. while (0x0 == (ep_int & 0x1)) {
  796. ep_int >>= 1;
  797. epnum++;
  798. }
  799. if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
  800. writel(ENDP_STATUS_IN,
  801. &outep_regs_p[epnum].endp_status);
  802. spear_udc_epn_tx(epnum);
  803. writel(ENDP_STATUS_IN,
  804. &outep_regs_p[epnum].endp_status);
  805. }
  806. writel((1 << epnum), &udc_regs_p->endp_int);
  807. }
  808. }
  809. /*
  810. * UDC interrupts
  811. */
  812. void udc_irq(void)
  813. {
  814. /*
  815. * Loop while we have interrupts.
  816. * If we don't do this, the input chain
  817. * polling delay is likely to miss
  818. * host requests.
  819. */
  820. while (readl(&plug_regs_p->plug_pending))
  821. spear_udc_plug_irq();
  822. while (readl(&udc_regs_p->dev_int))
  823. spear_udc_dev_irq();
  824. if (readl(&udc_regs_p->endp_int))
  825. spear_udc_endpoint_irq();
  826. }
  827. /* Flow control */
  828. void udc_set_nak(int epid)
  829. {
  830. writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
  831. &inep_regs_p[epid].endp_cntl);
  832. writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
  833. &outep_regs_p[epid].endp_cntl);
  834. }
  835. void udc_unset_nak(int epid)
  836. {
  837. u32 val;
  838. val = readl(&inep_regs_p[epid].endp_cntl);
  839. val &= ~ENDP_CNTL_SNAK;
  840. val |= ENDP_CNTL_CNAK;
  841. writel(val, &inep_regs_p[epid].endp_cntl);
  842. val = readl(&outep_regs_p[epid].endp_cntl);
  843. val &= ~ENDP_CNTL_SNAK;
  844. val |= ENDP_CNTL_CNAK;
  845. writel(val, &outep_regs_p[epid].endp_cntl);
  846. }