spr_smi.c 12 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <flash.h>
  25. #include <linux/err.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/spr_smi.h>
  29. #if !defined(CONFIG_SYS_NO_FLASH)
  30. static struct smi_regs *const smicntl =
  31. (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
  32. static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
  33. CONFIG_SYS_FLASH_ADDR_BASE;
  34. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  35. #define ST_M25Pxx_ID 0x00002020
  36. static struct flash_dev flash_ids[] = {
  37. {0x10, 0x10000, 2}, /* 64K Byte */
  38. {0x11, 0x20000, 4}, /* 128K Byte */
  39. {0x12, 0x40000, 4}, /* 256K Byte */
  40. {0x13, 0x80000, 8}, /* 512K Byte */
  41. {0x14, 0x100000, 16}, /* 1M Byte */
  42. {0x15, 0x200000, 32}, /* 2M Byte */
  43. {0x16, 0x400000, 64}, /* 4M Byte */
  44. {0x17, 0x800000, 128}, /* 8M Byte */
  45. {0x18, 0x1000000, 64}, /* 16M Byte */
  46. {0x00,}
  47. };
  48. /*
  49. * smi_wait_xfer_finish - Wait until TFF is set in status register
  50. * @timeout: timeout in milliseconds
  51. *
  52. * Wait until TFF is set in status register
  53. */
  54. static void smi_wait_xfer_finish(int timeout)
  55. {
  56. while (timeout--) {
  57. if (readl(&smicntl->smi_sr) & TFF)
  58. break;
  59. udelay(1000);
  60. }
  61. }
  62. /*
  63. * smi_read_id - Read flash id
  64. * @info: flash_info structure pointer
  65. * @banknum: bank number
  66. *
  67. * Read the flash id present at bank #banknum
  68. */
  69. static unsigned int smi_read_id(flash_info_t *info, int banknum)
  70. {
  71. unsigned int value;
  72. writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
  73. writel(READ_ID, &smicntl->smi_tr);
  74. writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
  75. &smicntl->smi_cr2);
  76. smi_wait_xfer_finish(XFER_FINISH_TOUT);
  77. value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
  78. writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);
  79. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  80. return value;
  81. }
  82. /*
  83. * flash_get_size - Detect the SMI flash by reading the ID.
  84. * @base: Base address of the flash area bank #banknum
  85. * @banknum: Bank number
  86. *
  87. * Detect the SMI flash by reading the ID. Initializes the flash_info structure
  88. * with size, sector count etc.
  89. */
  90. static ulong flash_get_size(ulong base, int banknum)
  91. {
  92. flash_info_t *info = &flash_info[banknum];
  93. struct flash_dev *dev;
  94. unsigned int value;
  95. unsigned int density;
  96. int i;
  97. value = smi_read_id(info, banknum);
  98. density = (value >> 16) & 0xff;
  99. for (i = 0, dev = &flash_ids[0]; dev->density != 0x0;
  100. i++, dev = &flash_ids[i]) {
  101. if (dev->density == density) {
  102. info->size = dev->size;
  103. info->sector_count = dev->sector_count;
  104. break;
  105. }
  106. }
  107. if (dev->density == 0x0)
  108. return 0;
  109. info->flash_id = value & 0xffff;
  110. info->start[0] = base;
  111. return info->size;
  112. }
  113. /*
  114. * smi_read_sr - Read status register of SMI
  115. * @bank: bank number
  116. *
  117. * This routine will get the status register of the flash chip present at the
  118. * given bank
  119. */
  120. static unsigned int smi_read_sr(int bank)
  121. {
  122. u32 ctrlreg1;
  123. /* store the CTRL REG1 state */
  124. ctrlreg1 = readl(&smicntl->smi_cr1);
  125. /* Program SMI in HW Mode */
  126. writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
  127. &smicntl->smi_cr1);
  128. /* Performing a RSR instruction in HW mode */
  129. writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
  130. smi_wait_xfer_finish(XFER_FINISH_TOUT);
  131. /* Restore the CTRL REG1 state */
  132. writel(ctrlreg1, &smicntl->smi_cr1);
  133. return readl(&smicntl->smi_sr);
  134. }
  135. /*
  136. * smi_wait_till_ready - Wait till last operation is over.
  137. * @bank: bank number shifted.
  138. * @timeout: timeout in milliseconds.
  139. *
  140. * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
  141. * The routine checks for #timeout loops, each at interval of 1 milli-second.
  142. * If successful the routine returns 0.
  143. */
  144. static int smi_wait_till_ready(int bank, int timeout)
  145. {
  146. int count;
  147. unsigned int sr;
  148. /* One chip guarantees max 5 msec wait here after page writes,
  149. but potentially three seconds (!) after page erase. */
  150. for (count = 0; count < timeout; count++) {
  151. sr = smi_read_sr(bank);
  152. if (sr < 0)
  153. break;
  154. else if (!(sr & WIP_BIT))
  155. return 0;
  156. /* Try again after 1m-sec */
  157. udelay(1000);
  158. }
  159. printf("SMI controller is still in wait, timeout=%d\n", timeout);
  160. return -EIO;
  161. }
  162. /*
  163. * smi_write_enable - Enable the flash to do write operation
  164. * @bank: bank number
  165. *
  166. * Set write enable latch with Write Enable command.
  167. * Returns negative if error occurred.
  168. */
  169. static int smi_write_enable(int bank)
  170. {
  171. u32 ctrlreg1;
  172. int timeout = WMODE_TOUT;
  173. /* Store the CTRL REG1 state */
  174. ctrlreg1 = readl(&smicntl->smi_cr1);
  175. /* Program SMI in H/W Mode */
  176. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  177. /* Give the Flash, Write Enable command */
  178. writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
  179. smi_wait_xfer_finish(XFER_FINISH_TOUT);
  180. /* Restore the CTRL REG1 state */
  181. writel(ctrlreg1, &smicntl->smi_cr1);
  182. while (timeout--) {
  183. if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT)))
  184. break;
  185. udelay(1000);
  186. }
  187. if (timeout)
  188. return 0;
  189. return -1;
  190. }
  191. /*
  192. * smi_init - SMI initialization routine
  193. *
  194. * SMI initialization routine. Sets SMI control register1.
  195. */
  196. static void smi_init(void)
  197. {
  198. /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
  199. writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
  200. &smicntl->smi_cr1);
  201. }
  202. /*
  203. * smi_sector_erase - Erase flash sector
  204. * @info: flash_info structure pointer
  205. * @sector: sector number
  206. *
  207. * Set write enable latch with Write Enable command.
  208. * Returns negative if error occurred.
  209. */
  210. static int smi_sector_erase(flash_info_t *info, unsigned int sector)
  211. {
  212. int bank;
  213. unsigned int sect_add;
  214. unsigned int instruction;
  215. switch (info->start[0]) {
  216. case SMIBANK0_BASE:
  217. bank = BANK0;
  218. break;
  219. case SMIBANK1_BASE:
  220. bank = BANK1;
  221. break;
  222. case SMIBANK2_BASE:
  223. bank = BANK2;
  224. break;
  225. case SMIBANK3_BASE:
  226. bank = BANK3;
  227. break;
  228. default:
  229. return -1;
  230. }
  231. sect_add = sector * (info->size / info->sector_count);
  232. instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
  233. writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
  234. if (info->flash_id == ST_M25Pxx_ID) {
  235. /* Wait until finished previous write command. */
  236. if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
  237. return -EBUSY;
  238. /* Send write enable, before erase commands. */
  239. if (smi_write_enable(bank))
  240. return -EIO;
  241. /* Put SMI in SW mode */
  242. writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
  243. /* Send Sector Erase command in SW Mode */
  244. writel(instruction, &smicntl->smi_tr);
  245. writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
  246. &smicntl->smi_cr2);
  247. smi_wait_xfer_finish(XFER_FINISH_TOUT);
  248. if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
  249. return -EBUSY;
  250. /* Put SMI in HW mode */
  251. writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
  252. &smicntl->smi_cr1);
  253. return 0;
  254. } else {
  255. /* Put SMI in HW mode */
  256. writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
  257. &smicntl->smi_cr1);
  258. return -EINVAL;
  259. }
  260. }
  261. /*
  262. * smi_write - Write to SMI flash
  263. * @src_addr: source buffer
  264. * @dst_addr: destination buffer
  265. * @length: length to write in words
  266. * @bank: bank base address
  267. *
  268. * Write to SMI flash
  269. */
  270. static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
  271. unsigned int length, ulong bank_addr)
  272. {
  273. int banknum;
  274. unsigned int WM;
  275. switch (bank_addr) {
  276. case SMIBANK0_BASE:
  277. banknum = BANK0;
  278. WM = WM0;
  279. break;
  280. case SMIBANK1_BASE:
  281. banknum = BANK1;
  282. WM = WM1;
  283. break;
  284. case SMIBANK2_BASE:
  285. banknum = BANK2;
  286. WM = WM2;
  287. break;
  288. case SMIBANK3_BASE:
  289. banknum = BANK3;
  290. WM = WM3;
  291. break;
  292. default:
  293. return -1;
  294. }
  295. if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
  296. return -EBUSY;
  297. /* Set SMI in Hardware Mode */
  298. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  299. if (smi_write_enable(banknum))
  300. return -EIO;
  301. /* Perform the write command */
  302. while (length--) {
  303. if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
  304. if (smi_wait_till_ready(banknum,
  305. CONFIG_SYS_FLASH_WRITE_TOUT))
  306. return -EBUSY;
  307. if (smi_write_enable(banknum))
  308. return -EIO;
  309. }
  310. *dst_addr++ = *src_addr++;
  311. if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
  312. return -EIO;
  313. }
  314. if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
  315. return -EBUSY;
  316. writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
  317. return 0;
  318. }
  319. /*
  320. * write_buff - Write to SMI flash
  321. * @info: flash info structure
  322. * @src: source buffer
  323. * @dest_addr: destination buffer
  324. * @length: length to write in words
  325. *
  326. * Write to SMI flash
  327. */
  328. int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
  329. {
  330. return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
  331. (length + 3) / 4, info->start[0]);
  332. }
  333. /*
  334. * flash_init - SMI flash initialization
  335. *
  336. * SMI flash initialization
  337. */
  338. unsigned long flash_init(void)
  339. {
  340. unsigned long size = 0;
  341. int i, j;
  342. smi_init();
  343. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
  344. flash_info[i].flash_id = FLASH_UNKNOWN;
  345. size += flash_info[i].size = flash_get_size(bank_base[i], i);
  346. }
  347. for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
  348. for (i = 1; i < flash_info[j].sector_count; i++)
  349. flash_info[j].start[i] =
  350. flash_info[j].start[i - 1] +
  351. flash_info->size / flash_info->sector_count;
  352. }
  353. return size;
  354. }
  355. /*
  356. * flash_print_info - Print SMI flash information
  357. *
  358. * Print SMI flash information
  359. */
  360. void flash_print_info(flash_info_t *info)
  361. {
  362. int i;
  363. if (info->flash_id == FLASH_UNKNOWN) {
  364. puts("missing or unknown FLASH type\n");
  365. return;
  366. }
  367. printf(" Size: %ld MB in %d Sectors\n",
  368. info->size >> 20, info->sector_count);
  369. puts(" Sector Start Addresses:");
  370. for (i = 0; i < info->sector_count; ++i) {
  371. #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
  372. int size;
  373. int erased;
  374. u32 *flash;
  375. /*
  376. * Check if whole sector is erased
  377. */
  378. size = (info->size) / (info->sector_count);
  379. flash = (u32 *) info->start[i];
  380. size = size / sizeof(int);
  381. while ((size--) && (*flash++ == ~0))
  382. ;
  383. size++;
  384. if (size)
  385. erased = 0;
  386. else
  387. erased = 1;
  388. if ((i % 5) == 0)
  389. printf("\n");
  390. printf(" %08lX%s%s",
  391. info->start[i],
  392. erased ? " E" : " ", info->protect[i] ? "RO " : " ");
  393. #else
  394. if ((i % 5) == 0)
  395. printf("\n ");
  396. printf(" %08lX%s",
  397. info->start[i], info->protect[i] ? " (RO) " : " ");
  398. #endif
  399. }
  400. putc('\n');
  401. return;
  402. }
  403. /*
  404. * flash_erase - Erase SMI flash
  405. *
  406. * Erase SMI flash
  407. */
  408. int flash_erase(flash_info_t *info, int s_first, int s_last)
  409. {
  410. int rcode = 0;
  411. int prot = 0;
  412. flash_sect_t sect;
  413. if (info->flash_id != ST_M25Pxx_ID) {
  414. puts("Can't erase unknown flash type - aborted\n");
  415. return 1;
  416. }
  417. if ((s_first < 0) || (s_first > s_last)) {
  418. puts("- no sectors to erase\n");
  419. return 1;
  420. }
  421. for (sect = s_first; sect <= s_last; ++sect) {
  422. if (info->protect[sect])
  423. prot++;
  424. }
  425. if (prot) {
  426. printf("- Warning: %d protected sectors will not be erased!\n",
  427. prot);
  428. } else {
  429. putc('\n');
  430. }
  431. for (sect = s_first; sect <= s_last; sect++) {
  432. if (info->protect[sect] == 0) {
  433. if (smi_sector_erase(info, sect))
  434. rcode = 1;
  435. else
  436. putc('.');
  437. }
  438. }
  439. puts(" done\n");
  440. return rcode;
  441. }
  442. #endif