kirkwood_i2c.c 13 KB

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  1. /*
  2. * Driver for the i2c controller on the Marvell line of host bridges
  3. * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family),
  4. * and Kirkwood family.
  5. *
  6. * Based on:
  7. * Author: Mark A. Greer <mgreer@mvista.com>
  8. * 2005 (c) MontaVista, Software, Inc.
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  26. * MA 02110-1301 USA
  27. *
  28. * ported from Linux to u-boot
  29. * (C) Copyright 2009
  30. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  31. */
  32. #include <common.h>
  33. #include <i2c.h>
  34. #include <asm/arch/kirkwood.h>
  35. #include <asm/errno.h>
  36. #include <asm/io.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
  39. #if defined(CONFIG_I2C_MUX)
  40. static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
  41. #endif
  42. /* Register defines */
  43. #define KW_I2C_REG_SLAVE_ADDR 0x00
  44. #define KW_I2C_REG_DATA 0x04
  45. #define KW_I2C_REG_CONTROL 0x08
  46. #define KW_I2C_REG_STATUS 0x0c
  47. #define KW_I2C_REG_BAUD 0x0c
  48. #define KW_I2C_REG_EXT_SLAVE_ADDR 0x10
  49. #define KW_I2C_REG_SOFT_RESET 0x1c
  50. #define KW_I2C_REG_CONTROL_ACK 0x00000004
  51. #define KW_I2C_REG_CONTROL_IFLG 0x00000008
  52. #define KW_I2C_REG_CONTROL_STOP 0x00000010
  53. #define KW_I2C_REG_CONTROL_START 0x00000020
  54. #define KW_I2C_REG_CONTROL_TWSIEN 0x00000040
  55. #define KW_I2C_REG_CONTROL_INTEN 0x00000080
  56. /* Ctlr status values */
  57. #define KW_I2C_STATUS_BUS_ERR 0x00
  58. #define KW_I2C_STATUS_MAST_START 0x08
  59. #define KW_I2C_STATUS_MAST_REPEAT_START 0x10
  60. #define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
  61. #define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
  62. #define KW_I2C_STATUS_MAST_WR_ACK 0x28
  63. #define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30
  64. #define KW_I2C_STATUS_MAST_LOST_ARB 0x38
  65. #define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
  66. #define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
  67. #define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50
  68. #define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
  69. #define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
  70. #define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
  71. #define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
  72. #define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
  73. #define KW_I2C_STATUS_NO_STATUS 0xf8
  74. /* Driver states */
  75. enum {
  76. KW_I2C_STATE_INVALID,
  77. KW_I2C_STATE_IDLE,
  78. KW_I2C_STATE_WAITING_FOR_START_COND,
  79. KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
  80. KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
  81. KW_I2C_STATE_WAITING_FOR_SLAVE_ACK,
  82. KW_I2C_STATE_WAITING_FOR_SLAVE_DATA,
  83. };
  84. /* Driver actions */
  85. enum {
  86. KW_I2C_ACTION_INVALID,
  87. KW_I2C_ACTION_CONTINUE,
  88. KW_I2C_ACTION_SEND_START,
  89. KW_I2C_ACTION_SEND_ADDR_1,
  90. KW_I2C_ACTION_SEND_ADDR_2,
  91. KW_I2C_ACTION_SEND_DATA,
  92. KW_I2C_ACTION_RCV_DATA,
  93. KW_I2C_ACTION_RCV_DATA_STOP,
  94. KW_I2C_ACTION_SEND_STOP,
  95. };
  96. /* defines to get compatible with Linux driver */
  97. #define IRQ_NONE 0x0
  98. #define IRQ_HANDLED 0x01
  99. #define I2C_M_TEN 0x01
  100. #define I2C_M_RD 0x02
  101. #define I2C_M_REV_DIR_ADDR 0x04;
  102. struct i2c_msg {
  103. u32 addr;
  104. u32 flags;
  105. u8 *buf;
  106. u32 len;
  107. };
  108. struct kirkwood_i2c_data {
  109. int irq;
  110. u32 state;
  111. u32 action;
  112. u32 aborting;
  113. u32 cntl_bits;
  114. void *reg_base;
  115. u32 reg_base_p;
  116. u32 reg_size;
  117. u32 addr1;
  118. u32 addr2;
  119. u32 bytes_left;
  120. u32 byte_posn;
  121. u32 block;
  122. int rc;
  123. u32 freq_m;
  124. u32 freq_n;
  125. struct i2c_msg *msg;
  126. };
  127. static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data")));
  128. static struct kirkwood_i2c_data *drv_data = &__drv_data;
  129. static struct i2c_msg __i2c_msg __attribute__ ((section (".data")));
  130. static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg;
  131. /*
  132. *****************************************************************************
  133. *
  134. * Finite State Machine & Interrupt Routines
  135. *
  136. *****************************************************************************
  137. */
  138. static inline int abs(int n)
  139. {
  140. if(n >= 0)
  141. return n;
  142. else
  143. return n * -1;
  144. }
  145. static void kirkwood_calculate_speed(int speed)
  146. {
  147. int calcspeed;
  148. int diff;
  149. int best_diff = CONFIG_SYS_TCLK;
  150. int best_speed = 0;
  151. int m, n;
  152. int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256};
  153. for (n = 0; n < 8; n++) {
  154. for (m = 0; m < 16; m++) {
  155. calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]);
  156. diff = abs((speed - calcspeed));
  157. if ( diff < best_diff) {
  158. best_diff = diff;
  159. best_speed = calcspeed;
  160. drv_data->freq_m = m;
  161. drv_data->freq_n = n;
  162. }
  163. }
  164. }
  165. }
  166. /* Reset hardware and initialize FSM */
  167. static void
  168. kirkwood_i2c_hw_init(int speed, int slaveadd)
  169. {
  170. drv_data->state = KW_I2C_STATE_IDLE;
  171. kirkwood_calculate_speed(speed);
  172. writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET);
  173. writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
  174. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD);
  175. writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR);
  176. writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR);
  177. writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP,
  178. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  179. }
  180. static void
  181. kirkwood_i2c_fsm(u32 status)
  182. {
  183. /*
  184. * If state is idle, then this is likely the remnants of an old
  185. * operation that driver has given up on or the user has killed.
  186. * If so, issue the stop condition and go to idle.
  187. */
  188. if (drv_data->state == KW_I2C_STATE_IDLE) {
  189. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  190. return;
  191. }
  192. /* The status from the ctlr [mostly] tells us what to do next */
  193. switch (status) {
  194. /* Start condition interrupt */
  195. case KW_I2C_STATUS_MAST_START: /* 0x08 */
  196. case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
  197. drv_data->action = KW_I2C_ACTION_SEND_ADDR_1;
  198. drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
  199. break;
  200. /* Performing a write */
  201. case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
  202. if (drv_data->msg->flags & I2C_M_TEN) {
  203. drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
  204. drv_data->state =
  205. KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
  206. break;
  207. }
  208. /* FALLTHRU */
  209. case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
  210. case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
  211. if ((drv_data->bytes_left == 0)
  212. || (drv_data->aborting
  213. && (drv_data->byte_posn != 0))) {
  214. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  215. drv_data->state = KW_I2C_STATE_IDLE;
  216. } else {
  217. drv_data->action = KW_I2C_ACTION_SEND_DATA;
  218. drv_data->state =
  219. KW_I2C_STATE_WAITING_FOR_SLAVE_ACK;
  220. drv_data->bytes_left--;
  221. }
  222. break;
  223. /* Performing a read */
  224. case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
  225. if (drv_data->msg->flags & I2C_M_TEN) {
  226. drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
  227. drv_data->state =
  228. KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
  229. break;
  230. }
  231. /* FALLTHRU */
  232. case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
  233. if (drv_data->bytes_left == 0) {
  234. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  235. drv_data->state = KW_I2C_STATE_IDLE;
  236. break;
  237. }
  238. /* FALLTHRU */
  239. case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
  240. if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK)
  241. drv_data->action = KW_I2C_ACTION_CONTINUE;
  242. else {
  243. drv_data->action = KW_I2C_ACTION_RCV_DATA;
  244. drv_data->bytes_left--;
  245. }
  246. drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA;
  247. if ((drv_data->bytes_left == 1) || drv_data->aborting)
  248. drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK;
  249. break;
  250. case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
  251. drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP;
  252. drv_data->state = KW_I2C_STATE_IDLE;
  253. break;
  254. case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
  255. case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
  256. case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
  257. /* Doesn't seem to be a device at other end */
  258. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  259. drv_data->state = KW_I2C_STATE_IDLE;
  260. drv_data->rc = -ENODEV;
  261. break;
  262. default:
  263. printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, "
  264. "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
  265. drv_data->state, status, drv_data->msg->addr,
  266. drv_data->msg->flags);
  267. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  268. kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  269. drv_data->rc = -EIO;
  270. }
  271. }
  272. static void
  273. kirkwood_i2c_do_action(void)
  274. {
  275. switch(drv_data->action) {
  276. case KW_I2C_ACTION_CONTINUE:
  277. writel(drv_data->cntl_bits,
  278. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  279. break;
  280. case KW_I2C_ACTION_SEND_START:
  281. writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START,
  282. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  283. break;
  284. case KW_I2C_ACTION_SEND_ADDR_1:
  285. writel(drv_data->addr1,
  286. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  287. writel(drv_data->cntl_bits,
  288. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  289. break;
  290. case KW_I2C_ACTION_SEND_ADDR_2:
  291. writel(drv_data->addr2,
  292. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  293. writel(drv_data->cntl_bits,
  294. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  295. break;
  296. case KW_I2C_ACTION_SEND_DATA:
  297. writel(drv_data->msg->buf[drv_data->byte_posn++],
  298. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  299. writel(drv_data->cntl_bits,
  300. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  301. break;
  302. case KW_I2C_ACTION_RCV_DATA:
  303. drv_data->msg->buf[drv_data->byte_posn++] =
  304. readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  305. writel(drv_data->cntl_bits,
  306. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  307. break;
  308. case KW_I2C_ACTION_RCV_DATA_STOP:
  309. drv_data->msg->buf[drv_data->byte_posn++] =
  310. readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  311. drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
  312. writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
  313. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  314. drv_data->block = 0;
  315. break;
  316. case KW_I2C_ACTION_INVALID:
  317. default:
  318. printf("kirkwood_i2c_do_action: Invalid action: %d\n",
  319. drv_data->action);
  320. drv_data->rc = -EIO;
  321. /* FALLTHRU */
  322. case KW_I2C_ACTION_SEND_STOP:
  323. drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
  324. writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
  325. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  326. drv_data->block = 0;
  327. break;
  328. }
  329. }
  330. static int
  331. kirkwood_i2c_intr(void)
  332. {
  333. u32 status;
  334. u32 ctrl;
  335. int rc = IRQ_NONE;
  336. ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  337. while ((ctrl & KW_I2C_REG_CONTROL_IFLG) &&
  338. (drv_data->rc == 0)) {
  339. status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS);
  340. kirkwood_i2c_fsm(status);
  341. kirkwood_i2c_do_action();
  342. rc = IRQ_HANDLED;
  343. ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  344. udelay(1000);
  345. }
  346. return rc;
  347. }
  348. static void
  349. kirkwood_i2c_doio(struct i2c_msg *msg)
  350. {
  351. int ret;
  352. while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) {
  353. /* poll Status register */
  354. ret = kirkwood_i2c_intr();
  355. if (ret == IRQ_NONE)
  356. udelay(10);
  357. }
  358. }
  359. static void
  360. kirkwood_i2c_prepare_for_io(struct i2c_msg *msg)
  361. {
  362. u32 dir = 0;
  363. drv_data->msg = msg;
  364. drv_data->byte_posn = 0;
  365. drv_data->bytes_left = msg->len;
  366. drv_data->aborting = 0;
  367. drv_data->rc = 0;
  368. /* in u-boot we use no IRQs */
  369. drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN;
  370. if (msg->flags & I2C_M_RD)
  371. dir = 1;
  372. if (msg->flags & I2C_M_TEN) {
  373. drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
  374. drv_data->addr2 = (u32)msg->addr & 0xff;
  375. } else {
  376. drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
  377. drv_data->addr2 = 0;
  378. }
  379. /* OK, no start it (from kirkwood_i2c_execute_msg())*/
  380. drv_data->action = KW_I2C_ACTION_SEND_START;
  381. drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND;
  382. drv_data->block = 1;
  383. kirkwood_i2c_do_action();
  384. }
  385. void
  386. i2c_init(int speed, int slaveadd)
  387. {
  388. kirkwood_i2c_hw_init(speed, slaveadd);
  389. }
  390. int
  391. i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
  392. {
  393. kirkwood_i2c_msg->buf = data;
  394. kirkwood_i2c_msg->len = length;
  395. kirkwood_i2c_msg->addr = dev;
  396. kirkwood_i2c_msg->flags = I2C_M_RD;
  397. kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
  398. kirkwood_i2c_doio(kirkwood_i2c_msg);
  399. return drv_data->rc;
  400. }
  401. int
  402. i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
  403. {
  404. kirkwood_i2c_msg->buf = data;
  405. kirkwood_i2c_msg->len = length;
  406. kirkwood_i2c_msg->addr = dev;
  407. kirkwood_i2c_msg->flags = 0;
  408. kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
  409. kirkwood_i2c_doio(kirkwood_i2c_msg);
  410. return drv_data->rc;
  411. }
  412. int
  413. i2c_probe(uchar chip)
  414. {
  415. return i2c_read(chip, 0, 0, NULL, 0);
  416. }
  417. int i2c_set_bus_num(unsigned int bus)
  418. {
  419. #if defined(CONFIG_I2C_MUX)
  420. if (bus < CONFIG_SYS_MAX_I2C_BUS) {
  421. i2c_bus_num = bus;
  422. } else {
  423. int ret;
  424. ret = i2x_mux_select_mux(bus);
  425. if (ret)
  426. return ret;
  427. i2c_bus_num = 0;
  428. }
  429. i2c_bus_num_mux = bus;
  430. #else
  431. if (bus > 0) {
  432. return -1;
  433. }
  434. i2c_bus_num = bus;
  435. #endif
  436. return 0;
  437. }
  438. unsigned int i2c_get_bus_num(void)
  439. {
  440. #if defined(CONFIG_I2C_MUX)
  441. return i2c_bus_num_mux;
  442. #else
  443. return i2c_bus_num;
  444. #endif
  445. }