cache.S 3.6 KB

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  1. /*
  2. * Copyright (C) 2009 Samsung Electronics
  3. * Minkyu Kang <mk7.kang@samsung.com>
  4. *
  5. * based on cpu/arm_cortexa8/omap3/cache.S
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <asm/arch/cpu.h>
  26. .align 5
  27. .global invalidate_dcache
  28. .global l2_cache_enable
  29. .global l2_cache_disable
  30. /*
  31. * invalidate_dcache()
  32. * Invalidate the whole D-cache.
  33. *
  34. * Corrupted registers: r0-r5, r7, r9-r11
  35. */
  36. invalidate_dcache:
  37. stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
  38. cmp r0, #0xC100 @ check if the cpu is s5pc100
  39. beq finished_inval @ s5pc100 doesn't need this
  40. @ routine
  41. mrc p15, 1, r0, c0, c0, 1 @ read clidr
  42. ands r3, r0, #0x7000000 @ extract loc from clidr
  43. mov r3, r3, lsr #23 @ left align loc bit field
  44. beq finished_inval @ if loc is 0, then no need to
  45. @ clean
  46. mov r10, #0 @ start clean at cache level 0
  47. inval_loop1:
  48. add r2, r10, r10, lsr #1 @ work out 3x current cache
  49. @ level
  50. mov r1, r0, lsr r2 @ extract cache type bits from
  51. @ clidr
  52. and r1, r1, #7 @ mask of the bits for current
  53. @ cache only
  54. cmp r1, #2 @ see what cache we have at
  55. @ this level
  56. blt skip_inval @ skip if no cache, or just
  57. @ i-cache
  58. mcr p15, 2, r10, c0, c0, 0 @ select current cache level
  59. @ in cssr
  60. mov r2, #0 @ operand for mcr SBZ
  61. mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
  62. @ sych the new cssr&csidr,
  63. @ with armv7 this is 'isb',
  64. @ but we compile with armv5
  65. mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
  66. and r2, r1, #7 @ extract the length of the
  67. @ cache lines
  68. add r2, r2, #4 @ add 4 (line length offset)
  69. ldr r4, =0x3ff
  70. ands r4, r4, r1, lsr #3 @ find maximum number on the
  71. @ way size
  72. clz r5, r4 @ find bit position of way
  73. @ size increment
  74. ldr r7, =0x7fff
  75. ands r7, r7, r1, lsr #13 @ extract max number of the
  76. @ index size
  77. inval_loop2:
  78. mov r9, r4 @ create working copy of max
  79. @ way size
  80. inval_loop3:
  81. orr r11, r10, r9, lsl r5 @ factor way and cache number
  82. @ into r11
  83. orr r11, r11, r7, lsl r2 @ factor index number into r11
  84. mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
  85. subs r9, r9, #1 @ decrement the way
  86. bge inval_loop3
  87. subs r7, r7, #1 @ decrement the index
  88. bge inval_loop2
  89. skip_inval:
  90. add r10, r10, #2 @ increment cache number
  91. cmp r3, r10
  92. bgt inval_loop1
  93. finished_inval:
  94. mov r10, #0 @ swith back to cache level 0
  95. mcr p15, 2, r10, c0, c0, 0 @ select current cache level
  96. @ in cssr
  97. mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
  98. @ with armv7 this is 'isb',
  99. @ but we compile with armv5
  100. ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
  101. l2_cache_enable:
  102. push {r0, r1, r2, lr}
  103. mrc 15, 0, r3, cr1, cr0, 1
  104. orr r3, r3, #2
  105. mcr 15, 0, r3, cr1, cr0, 1
  106. pop {r1, r2, r3, pc}
  107. l2_cache_disable:
  108. push {r0, r1, r2, lr}
  109. mrc 15, 0, r3, cr1, cr0, 1
  110. bic r3, r3, #2
  111. mcr 15, 0, r3, cr1, cr0, 1
  112. pop {r1, r2, r3, pc}