spr_lowlevel_init.S 3.6 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <config.h>
  24. /*
  25. * platform specific initializations are already done in Xloader
  26. * Initializations already done include
  27. * DDR, PLLs, IP's clock enable and reset release etc
  28. */
  29. .globl lowlevel_init
  30. lowlevel_init:
  31. /* By default, U-Boot switches CPU to low-vector */
  32. /* Revert this as we work in high vector even in U-Boot */
  33. mrc p15, 0, r0, c1, c0, 0
  34. orr r0, r0, #0x00002000
  35. mcr p15, 0, r0, c1, c0, 0
  36. mov pc, lr
  37. /* void setfreq(unsigned int device, unsigned int frequency) */
  38. .global setfreq
  39. setfreq:
  40. stmfd sp!,{r14}
  41. stmfd sp!,{r0-r12}
  42. mov r8,sp
  43. ldr sp,SRAM_STACK_V
  44. /* Saving the function arguements for later use */
  45. mov r4,r0
  46. mov r5,r1
  47. /* Putting DDR into self refresh */
  48. ldr r0,DDR_07_V
  49. ldr r1,[r0]
  50. ldr r2,DDR_ACTIVE_V
  51. bic r1, r1, r2
  52. str r1,[r0]
  53. ldr r0,DDR_57_V
  54. ldr r1,[r0]
  55. ldr r2,CYCLES_MASK_V
  56. bic r1, r1, r2
  57. ldr r2,REFRESH_CYCLES_V
  58. orr r1, r1, r2, lsl #16
  59. str r1,[r0]
  60. ldr r0,DDR_07_V
  61. ldr r1,[r0]
  62. ldr r2,SREFRESH_MASK_V
  63. orr r1, r1, r2
  64. str r1,[r0]
  65. /* flush pipeline */
  66. b flush
  67. .align 5
  68. flush:
  69. /* Delay to ensure self refresh mode */
  70. ldr r0,SREFRESH_DELAY_V
  71. delay:
  72. sub r0,r0,#1
  73. cmp r0,#0
  74. bne delay
  75. /* Putting system in slow mode */
  76. ldr r0,SCCTRL_V
  77. mov r1,#2
  78. str r1,[r0]
  79. /* Changing PLL(1/2) frequency */
  80. mov r0,r4
  81. mov r1,r5
  82. cmp r4,#0
  83. beq pll1_freq
  84. /* Change PLL2 (DDR frequency) */
  85. ldr r6,PLL2_FREQ_V
  86. ldr r7,PLL2_CNTL_V
  87. b pll2_freq
  88. pll1_freq:
  89. /* Change PLL1 (CPU frequency) */
  90. ldr r6,PLL1_FREQ_V
  91. ldr r7,PLL1_CNTL_V
  92. pll2_freq:
  93. mov r0,r6
  94. ldr r1,[r0]
  95. ldr r2,PLLFREQ_MASK_V
  96. bic r1,r1,r2
  97. mov r2,r5,lsr#1
  98. orr r1,r1,r2,lsl#24
  99. str r1,[r0]
  100. mov r0,r7
  101. ldr r1,P1C0A_V
  102. str r1,[r0]
  103. ldr r1,P1C0E_V
  104. str r1,[r0]
  105. ldr r1,P1C06_V
  106. str r1,[r0]
  107. ldr r1,P1C0E_V
  108. str r1,[r0]
  109. lock:
  110. ldr r1,[r0]
  111. and r1,r1,#1
  112. cmp r1,#0
  113. beq lock
  114. /* Putting system back to normal mode */
  115. ldr r0,SCCTRL_V
  116. mov r1,#4
  117. str r1,[r0]
  118. /* Putting DDR back to normal */
  119. ldr r0,DDR_07_V
  120. ldr r1,[R0]
  121. ldr r2,SREFRESH_MASK_V
  122. bic r1, r1, r2
  123. str r1,[r0]
  124. ldr r2,DDR_ACTIVE_V
  125. orr r1, r1, r2
  126. str r1,[r0]
  127. /* Delay to ensure self refresh mode */
  128. ldr r0,SREFRESH_DELAY_V
  129. 1:
  130. sub r0,r0,#1
  131. cmp r0,#0
  132. bne 1b
  133. mov sp,r8
  134. /* Resuming back to code */
  135. ldmia sp!,{r0-r12}
  136. ldmia sp!,{pc}
  137. SCCTRL_V:
  138. .word 0xfca00000
  139. PLL1_FREQ_V:
  140. .word 0xfca8000C
  141. PLL1_CNTL_V:
  142. .word 0xfca80008
  143. PLL2_FREQ_V:
  144. .word 0xfca80018
  145. PLL2_CNTL_V:
  146. .word 0xfca80014
  147. PLLFREQ_MASK_V:
  148. .word 0xff000000
  149. P1C0A_V:
  150. .word 0x1C0A
  151. P1C0E_V:
  152. .word 0x1C0E
  153. P1C06_V:
  154. .word 0x1C06
  155. SREFRESH_DELAY_V:
  156. .word 0x9999
  157. SRAM_STACK_V:
  158. .word 0xD2800600
  159. DDR_07_V:
  160. .word 0xfc60001c
  161. DDR_ACTIVE_V:
  162. .word 0x01000000
  163. DDR_57_V:
  164. .word 0xfc6000e4
  165. CYCLES_MASK_V:
  166. .word 0xffff0000
  167. REFRESH_CYCLES_V:
  168. .word 0xf0f0
  169. SREFRESH_MASK_V:
  170. .word 0x00010000
  171. .global setfreq_sz
  172. setfreq_sz:
  173. .word setfreq_sz - setfreq