meesc.c 7.0 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * (C) Copyright 2009
  7. * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  8. * esd electronic system design gmbh <www.esd.eu>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <asm/arch/at91sam9263.h>
  30. #include <asm/arch/at91sam9_matrix.h>
  31. #include <asm/arch/at91sam9_smc.h>
  32. #include <asm/arch/at91_common.h>
  33. #include <asm/arch/at91_pmc.h>
  34. #include <asm/arch/at91_rstc.h>
  35. #include <asm/arch/clk.h>
  36. #include <asm/arch/gpio.h>
  37. #include <asm/arch/hardware.h>
  38. #include <asm/arch/io.h>
  39. #include <netdev.h>
  40. DECLARE_GLOBAL_DATA_PTR;
  41. /*
  42. * Miscelaneous platform dependent initialisations
  43. */
  44. static int hw_rev = -1; /* hardware revision */
  45. int get_hw_rev(void)
  46. {
  47. if (hw_rev >= 0)
  48. return hw_rev;
  49. hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
  50. hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
  51. hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
  52. hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
  53. if (hw_rev == 15)
  54. hw_rev = 0;
  55. return hw_rev;
  56. }
  57. #ifdef CONFIG_CMD_NAND
  58. static void meesc_nand_hw_init(void)
  59. {
  60. unsigned long csa;
  61. /* Enable CS3 */
  62. csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  63. at91_sys_write(AT91_MATRIX_EBI0CSA,
  64. csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  65. /* Configure SMC CS3 for NAND/SmartMedia */
  66. at91_sys_write(AT91_SMC_SETUP(3),
  67. AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  68. AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  69. at91_sys_write(AT91_SMC_PULSE(3),
  70. AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  71. AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  72. at91_sys_write(AT91_SMC_CYCLE(3),
  73. AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  74. at91_sys_write(AT91_SMC_MODE(3),
  75. AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  76. AT91_SMC_EXNWMODE_DISABLE |
  77. #ifdef CONFIG_SYS_NAND_DBW_16
  78. AT91_SMC_DBW_16 |
  79. #else /* CONFIG_SYS_NAND_DBW_8 */
  80. AT91_SMC_DBW_8 |
  81. #endif
  82. AT91_SMC_TDF_(2));
  83. /* Configure RDY/BSY */
  84. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  85. /* Enable NandFlash */
  86. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  87. }
  88. #endif /* CONFIG_CMD_NAND */
  89. #ifdef CONFIG_MACB
  90. static void meesc_macb_hw_init(void)
  91. {
  92. /* Enable clock */
  93. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
  94. at91_macb_hw_init();
  95. }
  96. #endif
  97. /*
  98. * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
  99. * controller debugging
  100. * The ET1100 is located at physical address 0x70000000
  101. * Its process memory is located at physical address 0x70001000
  102. */
  103. static void meesc_ethercat_hw_init(void)
  104. {
  105. /* Configure SMC EBI1_CS0 for EtherCAT */
  106. at91_sys_write(AT91_SMC1_SETUP(0),
  107. AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  108. AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  109. at91_sys_write(AT91_SMC1_PULSE(0),
  110. AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
  111. AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
  112. at91_sys_write(AT91_SMC1_CYCLE(0),
  113. AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
  114. /*
  115. * Configure behavior at external wait signal, byte-select mode, 16 bit
  116. * data bus width, none data float wait states and TDF optimization
  117. */
  118. at91_sys_write(AT91_SMC1_MODE(0),
  119. AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
  120. AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
  121. AT91_SMC_TDFMODE);
  122. /* Configure RDY/BSY */
  123. at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
  124. }
  125. int dram_init(void)
  126. {
  127. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  128. gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
  129. return 0;
  130. }
  131. int board_eth_init(bd_t *bis)
  132. {
  133. int rc = 0;
  134. #ifdef CONFIG_MACB
  135. rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
  136. #endif
  137. return rc;
  138. }
  139. int checkboard(void)
  140. {
  141. char str[32];
  142. u_char hw_type; /* hardware type */
  143. /* read the "Type" register of the ET1100 controller */
  144. hw_type = readb(CONFIG_ET1100_BASE);
  145. switch (hw_type) {
  146. case 0x11:
  147. case 0x3F:
  148. /* ET1100 present, arch number of MEESC-Board */
  149. gd->bd->bi_arch_number = MACH_TYPE_MEESC;
  150. puts("Board: CAN-EtherCAT Gateway");
  151. break;
  152. case 0xFF:
  153. /* no ET1100 present, arch number of EtherCAN/2-Board */
  154. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  155. puts("Board: EtherCAN/2 Gateway");
  156. /* switch on LED1D */
  157. at91_set_gpio_output(AT91_PIN_PB12, 1);
  158. break;
  159. default:
  160. /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
  161. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  162. printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
  163. puts("Board: EtherCAN/2 Gateway");
  164. break;
  165. }
  166. if (getenv_r("serial#", str, sizeof(str)) > 0) {
  167. puts(", serial# ");
  168. puts(str);
  169. }
  170. printf("\nHardware-revision: 1.%d\n", get_hw_rev());
  171. printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
  172. return 0;
  173. }
  174. #ifdef CONFIG_SERIAL_TAG
  175. void get_board_serial(struct tag_serialnr *serialnr)
  176. {
  177. char *str;
  178. char *serial = getenv("serial#");
  179. if (serial) {
  180. str = strchr(serial, '_');
  181. if (str && (strlen(str) >= 4)) {
  182. serialnr->high = (*(str + 1) << 8) | *(str + 2);
  183. serialnr->low = simple_strtoul(str + 3, NULL, 16);
  184. }
  185. } else {
  186. serialnr->high = 0;
  187. serialnr->low = 0;
  188. }
  189. }
  190. #endif
  191. #ifdef CONFIG_REVISION_TAG
  192. u32 get_board_rev(void)
  193. {
  194. return hw_rev | 0x100;
  195. }
  196. #endif
  197. #ifdef CONFIG_MISC_INIT_R
  198. int misc_init_r(void)
  199. {
  200. char *str;
  201. char buf[32];
  202. /*
  203. * Normally the processor clock has a divisor of 2.
  204. * In some cases this this needs to be set to 4.
  205. * Check the user has set environment mdiv to 4 to change the divisor.
  206. */
  207. if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
  208. at91_sys_write(AT91_PMC_MCKR,
  209. (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
  210. AT91SAM9_PMC_MDIV_4);
  211. at91_clock_init(0);
  212. serial_setbrg();
  213. /* Notify the user that the clock is not default */
  214. printf("Setting master clock to %s MHz\n",
  215. strmhz(buf, get_mck_clk_rate()));
  216. }
  217. return 0;
  218. }
  219. #endif /* CONFIG_MISC_INIT_R */
  220. int board_init(void)
  221. {
  222. /* Peripheral Clock Enable Register */
  223. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
  224. 1 << AT91SAM9263_ID_PIOB |
  225. 1 << AT91SAM9263_ID_PIOCDE);
  226. /* initialize ET1100 Controller */
  227. meesc_ethercat_hw_init();
  228. /* adress of boot parameters */
  229. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  230. at91_serial_hw_init();
  231. #ifdef CONFIG_CMD_NAND
  232. meesc_nand_hw_init();
  233. #endif
  234. #ifdef CONFIG_HAS_DATAFLASH
  235. at91_spi0_hw_init(1 << 0);
  236. #endif
  237. #ifdef CONFIG_MACB
  238. meesc_macb_hw_init();
  239. #endif
  240. #ifdef CONFIG_AT91_CAN
  241. at91_can_hw_init();
  242. #endif
  243. return 0;
  244. }