ds414.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <miiphy.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/soc.h>
  13. #include <linux/bitops.h>
  14. #include <linux/mbus.h>
  15. #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  16. #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  17. #include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
  18. #include "cmd_syno.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
  21. #define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30))
  22. #define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15))
  23. #define DS414_GPP_OUT_VAL_HIGH (0)
  24. #define DS414_GPP_OUT_POL_LOW (0)
  25. #define DS414_GPP_OUT_POL_MID (0)
  26. #define DS414_GPP_OUT_POL_HIGH (0)
  27. #define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30)))
  28. #define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \
  29. BIT(13) | BIT(14) | BIT(15)))
  30. #define DS414_GPP_OUT_ENA_HIGH (~0)
  31. static const u32 ds414_mpp_control[] = {
  32. 0x11111111,
  33. 0x22221111,
  34. 0x22222222,
  35. 0x00000000,
  36. 0x11110000,
  37. 0x00004000,
  38. 0x00000000,
  39. 0x00000000,
  40. 0x00000000
  41. };
  42. /* DDR3 static MC configuration */
  43. /* 1G_v1 (4x2Gbits) adapted by DS414 */
  44. MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
  45. {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */
  46. {0x00001404, 0x30000800}, /*Dunit Control Low Register */
  47. {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */
  48. {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */
  49. {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */
  50. {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
  51. {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
  52. {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
  53. {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */
  54. {0x00001428, 0x000F8830}, /*Dunit Control High Register */
  55. {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */
  56. {0x0000147C, 0x0000C671},
  57. {0x000014a0, 0x00000001},
  58. {0x000014a8, 0x00000100}, /*2:1 */
  59. {0x00020220, 0x00000006},
  60. {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */
  61. {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */
  62. {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */
  63. {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
  64. {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
  65. {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
  66. {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
  67. {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
  68. {0x000150C, 0x00000000}, /* CS1 Size */
  69. {0x0001514, 0x00000000}, /* CS2 Size */
  70. {0x000151C, 0x00000000}, /* CS3 Size */
  71. {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
  72. {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */
  73. {0x000015D0, 0x00000650}, /*MR0 */
  74. {0x000015D4, 0x00000044}, /*MR1 */
  75. {0x000015D8, 0x00000010}, /*MR2 */
  76. {0x000015DC, 0x00000000}, /*MR3 */
  77. {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */
  78. {0x000015EC, 0xF800A225}, /*DDR PHY */
  79. {0x0, 0x0}
  80. };
  81. MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
  82. {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
  83. };
  84. extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
  85. MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
  86. { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
  87. { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
  88. PEX_BUS_DISABLED },
  89. 0x0040, serdes_change_m_phy
  90. }
  91. };
  92. MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
  93. {
  94. return &ds414_ddr_modes[0];
  95. }
  96. MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
  97. {
  98. return &ds414_serdes_cfg[0];
  99. }
  100. u8 board_sat_r_get(u8 dev_num, u8 reg)
  101. {
  102. return 0xf; /* All PEX ports support PCIe Gen2 */
  103. }
  104. int board_early_init_f(void)
  105. {
  106. int i;
  107. /* Set GPP Out value */
  108. reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
  109. reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
  110. reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
  111. /* set GPP polarity */
  112. reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
  113. reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
  114. reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
  115. /* Set GPP Out Enable */
  116. reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
  117. reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
  118. reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
  119. for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
  120. reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
  121. return 0;
  122. }
  123. int board_init(void)
  124. {
  125. u32 pwr_mng_ctrl_reg;
  126. /* Adress of boot parameters */
  127. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  128. /* Gate unused clocks
  129. *
  130. * Note: Disabling unused PCIe lanes will hang PCI bus scan.
  131. * Once this is resolved, bits 10-12, 26 and 27 can be
  132. * unset here as well.
  133. */
  134. pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
  135. pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
  136. pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */
  137. pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */
  138. pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
  139. pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
  140. pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */
  141. pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */
  142. reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
  143. return 0;
  144. }
  145. int misc_init_r(void)
  146. {
  147. if (!env_get("ethaddr")) {
  148. puts("Incomplete environment, populating from SPI flash\n");
  149. do_syno_populate(0, NULL);
  150. }
  151. return 0;
  152. }
  153. int checkboard(void)
  154. {
  155. puts("Board: DS414\n");
  156. return 0;
  157. }