socrates.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003, Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. */
  12. #include <common.h>
  13. #include <clock_legacy.h>
  14. #include <env.h>
  15. #include <pci.h>
  16. #include <asm/processor.h>
  17. #include <asm/immap_85xx.h>
  18. #include <ioports.h>
  19. #include <flash.h>
  20. #include <linux/libfdt.h>
  21. #include <fdt_support.h>
  22. #include <asm/io.h>
  23. #include <i2c.h>
  24. #include <mb862xx.h>
  25. #include <video_fb.h>
  26. #include "upm_table.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. extern flash_info_t flash_info[]; /* FLASH chips info */
  29. extern GraphicDevice mb862xx;
  30. void local_bus_init (void);
  31. ulong flash_get_size (ulong base, int banknum);
  32. int checkboard (void)
  33. {
  34. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35. char buf[64];
  36. int f;
  37. int i = env_get_f("serial#", buf, sizeof(buf));
  38. #ifdef CONFIG_PCI
  39. char *src;
  40. #endif
  41. puts("Board: Socrates");
  42. if (i > 0) {
  43. puts(", serial# ");
  44. puts(buf);
  45. }
  46. putc('\n');
  47. #if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
  48. /* Check the PCI_clk sel bit */
  49. if (in_be32(&gur->porpllsr) & (1<<15)) {
  50. src = "SYSCLK";
  51. f = CONFIG_SYS_CLK_FREQ;
  52. } else {
  53. src = "PCI_CLK";
  54. f = CONFIG_PCI_CLK_FREQ;
  55. }
  56. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  57. #else
  58. printf ("PCI1: disabled\n");
  59. #endif
  60. /*
  61. * Initialize local bus.
  62. */
  63. local_bus_init ();
  64. return 0;
  65. }
  66. int misc_init_r (void)
  67. {
  68. /*
  69. * Adjust flash start and offset to detected values
  70. */
  71. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  72. gd->bd->bi_flashoffset = 0;
  73. /*
  74. * Check if boot FLASH isn't max size
  75. */
  76. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  77. set_lbc_or(0, gd->bd->bi_flashstart |
  78. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  79. set_lbc_br(0, gd->bd->bi_flashstart |
  80. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  81. /*
  82. * Re-check to get correct base address
  83. */
  84. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  85. }
  86. /*
  87. * Check if only one FLASH bank is available
  88. */
  89. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  90. set_lbc_or(1, 0);
  91. set_lbc_br(1, 0);
  92. /*
  93. * Re-do flash protection upon new addresses
  94. */
  95. flash_protect(FLAG_PROTECT_CLEAR,
  96. gd->bd->bi_flashstart, 0xffffffff,
  97. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  98. /* Monitor protection ON by default */
  99. flash_protect(FLAG_PROTECT_SET,
  100. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
  101. monitor_flash_len - 1,
  102. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  103. /* Environment protection ON by default */
  104. flash_protect(FLAG_PROTECT_SET,
  105. CONFIG_ENV_ADDR,
  106. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  107. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  108. /* Redundant environment protection ON by default */
  109. flash_protect(FLAG_PROTECT_SET,
  110. CONFIG_ENV_ADDR_REDUND,
  111. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  112. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  113. }
  114. #if defined(CONFIG_DM_PCI)
  115. pci_init();
  116. #endif
  117. return 0;
  118. }
  119. /*
  120. * Initialize Local Bus
  121. */
  122. void local_bus_init (void)
  123. {
  124. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  125. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  126. sys_info_t sysinfo;
  127. uint clkdiv;
  128. uint lbc_mhz;
  129. uint lcrr = CONFIG_SYS_LBC_LCRR;
  130. get_sys_info (&sysinfo);
  131. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  132. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  133. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  134. if (lbc_mhz >= 66)
  135. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  136. else
  137. lcrr |= LCRR_DBYP; /* DLL Bypass */
  138. out_be32 (&lbc->lcrr, lcrr);
  139. asm ("sync;isync;msync");
  140. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  141. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  142. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  143. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  144. /* Init UPMA for FPGA access */
  145. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  146. upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
  147. /* Init UPMB for Lime controller access */
  148. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  149. upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
  150. }
  151. #ifdef CONFIG_BOARD_EARLY_INIT_R
  152. int board_early_init_r (void)
  153. {
  154. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  155. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  156. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  157. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  158. udelay(200);
  159. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  160. return (0);
  161. }
  162. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  163. #ifdef CONFIG_OF_BOARD_SETUP
  164. int ft_board_setup(void *blob, bd_t *bd)
  165. {
  166. u32 val[12];
  167. int rc, i = 0;
  168. ft_cpu_setup(blob, bd);
  169. /* Fixup NOR FLASH mapping */
  170. val[i++] = 0; /* chip select number */
  171. val[i++] = 0; /* always 0 */
  172. val[i++] = gd->bd->bi_flashstart;
  173. val[i++] = gd->bd->bi_flashsize;
  174. #if defined(CONFIG_VIDEO_MB862xx)
  175. if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
  176. /* Fixup LIME mapping */
  177. val[i++] = 2; /* chip select number */
  178. val[i++] = 0; /* always 0 */
  179. val[i++] = CONFIG_SYS_LIME_BASE;
  180. val[i++] = CONFIG_SYS_LIME_SIZE;
  181. }
  182. #endif
  183. /* Fixup FPGA mapping */
  184. val[i++] = 3; /* chip select number */
  185. val[i++] = 0; /* always 0 */
  186. val[i++] = CONFIG_SYS_FPGA_BASE;
  187. val[i++] = CONFIG_SYS_FPGA_SIZE;
  188. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  189. val, i * sizeof(u32), 1);
  190. if (rc)
  191. printf("Unable to update localbus ranges, err=%s\n",
  192. fdt_strerror(rc));
  193. return 0;
  194. }
  195. #endif /* CONFIG_OF_BOARD_SETUP */
  196. #if defined(CONFIG_OF_SEPARATE)
  197. void *board_fdt_blob_setup(void)
  198. {
  199. void *fw_dtb;
  200. fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
  201. if (fdt_magic(fw_dtb) != FDT_MAGIC) {
  202. printf("DTB is not passed via %x\n", (u32)fw_dtb);
  203. return NULL;
  204. }
  205. return fw_dtb;
  206. }
  207. #endif
  208. int get_serial_clock(void)
  209. {
  210. return 333333330;
  211. }