epic2.S 4.7 KB

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  1. /**************************************
  2. *
  3. * copyright @ Motorola, 1999
  4. *
  5. **************************************/
  6. #include <ppc_asm.tmpl>
  7. #include <ppc_defs.h>
  8. #include <asm/processor.h>
  9. /*********************************************
  10. * function: CoreExtIntEnable
  11. *
  12. * description: Enable 603e core external interrupt
  13. *
  14. * note: mtmsr is context-synchronization
  15. **********************************************/
  16. .text
  17. .align 2
  18. .global CoreExtIntEnable
  19. CoreExtIntEnable:
  20. mfmsr r3
  21. ori r3,r3,0x8000 /* enable external interrupt */
  22. mtmsr r3
  23. bclr 20, 0
  24. /*******************************************
  25. * function: CoreExtIntDisable
  26. *
  27. * description: Disable 603e core external interrupt
  28. *
  29. * note:
  30. *******************************************/
  31. .text
  32. .align 2
  33. .global CoreExtIntDisable
  34. CoreExtIntDisable:
  35. mfmsr r4
  36. xor r3,r3,r3
  37. or r3,r3,r4
  38. andis. r4,r4,0xffff
  39. andi. r3,r3,0x7fff /* disable external interrupt */
  40. or r3,r3,r4
  41. mtmsr r3
  42. bclr 20, 0
  43. /*********************************************************
  44. * function: epicEOI
  45. *
  46. * description: signal the EOI and restore machine status
  47. * Input: r3 - value of eumbbar
  48. * Output: r3 - value of eumbbar
  49. * r4 - ISR vector value
  50. * note:
  51. ********************************************************/
  52. .text
  53. .align 2
  54. .global epicEOI
  55. epicEOI:
  56. lis r5,0x0006 /* Build End Of Interrupt Register offset */
  57. ori r5,r5,0x00b0
  58. xor r7,r7,r7 /* Clear r7 */
  59. stwbrx r7,r5,r3 /* Save r7, writing to this register will
  60. * intidate the end of processing the
  61. * highest interrupt.
  62. */
  63. sync
  64. /* ---RESTORE MACHINE STATE */
  65. mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */
  66. or r7,r7,r13
  67. andis. r7,r7,0xffff
  68. andi. r13,r13,0x7ffd /* (and disable interrupts) */
  69. or r13,r13,r7
  70. mtmsr r13
  71. lwz r13,0x1c(r1) /* pull ctr */
  72. mtctr r13
  73. lwz r13,0x18(r1) /* pull xer */
  74. mtctr r13
  75. lwz r13,0x14(r1) /* pull lr */
  76. mtctr r13
  77. lwz r13,0x10(r1) /* Pull SRR1 from stack */
  78. mtspr SRR1,r13 /* Restore SRR1 */
  79. lwz r13,0xc(r1) /* Pull SRR0 from stack */
  80. mtspr SRR0,r13 /* Restore SRR0 */
  81. lwz r13,0x8(r1) /* Pull User stack pointer from stack */
  82. mtspr SPRG1,r13 /* Restore SPRG1 */
  83. lwz r4,0x4(r1) /* vector value */
  84. lwz r3,0x0(r1) /* eumbbar */
  85. sync
  86. addi r1,r1,0x20 /* Deallocate stack */
  87. mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */
  88. mfspr r1,SPRG1 /* Restore User stack pointer */
  89. bclr 20,0
  90. /***********************************************************
  91. * function: exception routine called by exception vector
  92. * at 0x500, external interrupt
  93. *
  94. * description: Kahlua EPIC controller
  95. *
  96. * input: r3 - content of eumbbar
  97. * output: r3 - ISR return value
  98. * r4 - Interrupt vector number
  99. * note:
  100. ***********************************************************/
  101. .text
  102. .align 2
  103. .global epic_exception
  104. epic_exception:
  105. /*---SAVE MACHINE STATE TO A STACK */
  106. mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */
  107. mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */
  108. stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */
  109. mfspr r3,SPRG1 /* Push User stack pointer onto stack */
  110. stw r3,0x8(r1)
  111. mfspr r3,SRR0 /* Push SRR0 onto stack */
  112. stw r1,0xc(r1)
  113. mfspr r3,SRR1 /* Push SRR1 onto stack */
  114. stw r3,0x10(r1)
  115. mflr r3
  116. stw r3,0x14(r1) /* Push LR */
  117. mfxer r3
  118. stw r3,0x18(r1) /* Push Xer */
  119. mfctr r3
  120. stw r3,0x1c(r1) /* Push CTR */
  121. mtspr SPRG0,r1 /* Save updated Supervisor stack pointer
  122. * value to SPRG0
  123. */
  124. mfmsr r3
  125. ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */
  126. mtmsr r3
  127. /* ---READ IN THE EUMBAR REGISTER */
  128. lwz r6,0(r1) /* this is eumbbar */
  129. sync
  130. /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */
  131. lis r5,0x0006 /* Build Interrupt Acknowledge Register
  132. * offset
  133. */
  134. ori r5,r5,0x00a0
  135. lwbrx r7,r5,r6 /* Load interrupt vector into r7 */
  136. sync
  137. /* --MASK OFF ALL BITS EXCEPT THE VECTOR */
  138. xor r3,r3,r3
  139. xor r4,r4,r4
  140. or r3, r3, r6 /* eumbbar in r3 */
  141. andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */
  142. stw r4,0x04(r1) /* save the vector value */
  143. lis r5,epicISR@ha
  144. ori r5,r5,epicISR@l
  145. mtlr r5
  146. blrl
  147. xor r30,r30,r30
  148. or r30,r30,r3 /* save the r3 which containts the return value from epicISR */
  149. /* ---READ IN THE EUMBAR REGISTER */
  150. lwz r3,0(r1)
  151. sync
  152. lis r5,epicEOI@ha
  153. ori r5,r5,epicEOI@l
  154. mtlr r5
  155. blrl
  156. xor r3,r3,r3
  157. or r3,r3,r30 /* restore the ISR return value */
  158. bclr 20,0