uart.c 3.0 KB

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  1. /*
  2. * (C) Copyright 2004, Freescale, Inc
  3. * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. /*
  25. * Minimal serial functions needed to use one of the PSC ports
  26. * as serial console interface.
  27. */
  28. #include <common.h>
  29. #include <mpc8220.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define PSC_BASE MMAP_PSC1
  32. #if defined(CONFIG_PSC_CONSOLE)
  33. int serial_init (void)
  34. {
  35. volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
  36. u32 counter;
  37. /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
  38. psc->cr = 0;
  39. psc->ipcr_acr = 0;
  40. psc->isr_imr = 0;
  41. /* write to CSR: RX/TX baud rate from timers */
  42. psc->sr_csr = 0xdd000000;
  43. psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;
  44. /* Setting up BaudRate */
  45. counter = ((gd->bus_clk / gd->baudrate)) >> 5;
  46. counter++;
  47. /* write to CTUR: divide counter upper byte */
  48. psc->ctur = ((counter & 0xff00) << 16);
  49. /* write to CTLR: divide counter lower byte */
  50. psc->ctlr = ((counter & 0x00ff) << 24);
  51. psc->cr = PSC_CR_RST_RX_CMD;
  52. psc->cr = PSC_CR_RST_TX_CMD;
  53. psc->cr = PSC_CR_RST_ERR_STS_CMD;
  54. psc->cr = PSC_CR_RST_BRK_INT_CMD;
  55. psc->cr = PSC_CR_RST_MR_PTR_CMD;
  56. psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
  57. return (0);
  58. }
  59. void serial_putc (const char c)
  60. {
  61. volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
  62. if (c == '\n')
  63. serial_putc ('\r');
  64. /* Wait for last character to go. */
  65. while (!(psc->sr_csr & PSC_SR_TXRDY));
  66. psc->xmitbuf[0] = c;
  67. }
  68. void serial_puts (const char *s)
  69. {
  70. while (*s) {
  71. serial_putc (*s++);
  72. }
  73. }
  74. int serial_getc (void)
  75. {
  76. volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
  77. /* Wait for a character to arrive. */
  78. while (!(psc->sr_csr & PSC_SR_RXRDY));
  79. return psc->xmitbuf[2];
  80. }
  81. int serial_tstc (void)
  82. {
  83. volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
  84. return (psc->sr_csr & PSC_SR_RXRDY);
  85. }
  86. void serial_setbrg (void)
  87. {
  88. volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
  89. u32 counter;
  90. counter = ((gd->bus_clk / gd->baudrate)) >> 5;
  91. counter++;
  92. /* write to CTUR: divide counter upper byte */
  93. psc->ctur = ((counter & 0xff00) << 16);
  94. /* write to CTLR: divide counter lower byte */
  95. psc->ctlr = ((counter & 0x00ff) << 24);
  96. psc->cr = PSC_CR_RST_RX_CMD;
  97. psc->cr = PSC_CR_RST_TX_CMD;
  98. psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
  99. }
  100. #endif /* CONFIG_PSC_CONSOLE */