dramSetup.c 20 KB

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  1. /*
  2. * (C) Copyright 2004, Freescale, Inc
  3. * TsiChung Liew, Tsi-Chung.Liew@freescale.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. DESCRIPTION
  25. Read Dram spd and base on its information to calculate the memory size,
  26. characteristics to initialize the dram on MPC8220
  27. */
  28. #include <common.h>
  29. #include <mpc8220.h>
  30. #include "i2cCore.h"
  31. #include "dramSetup.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define SPD_SIZE CONFIG_SYS_SDRAM_SPD_SIZE
  34. #define DRAM_SPD (CONFIG_SYS_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */
  35. #define TOTAL_BANK CONFIG_SYS_SDRAM_TOTAL_BANKS
  36. int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
  37. {
  38. int i;
  39. for (i = 0; i < I2C_POLL_COUNT; i++) {
  40. if ((pi2c->sr & sta_bit) == (truefalse ? sta_bit : 0))
  41. return (OK);
  42. }
  43. return (ERROR);
  44. }
  45. int spd_clear (volatile i2c8220_t * pi2c)
  46. {
  47. pi2c->adr = 0;
  48. pi2c->fdr = 0;
  49. pi2c->cr = 0;
  50. pi2c->sr = 0;
  51. return (OK);
  52. }
  53. int spd_stop (volatile i2c8220_t * pi2c)
  54. {
  55. pi2c->cr &= ~I2C_CTL_STA; /* Generate stop signal */
  56. if (spd_status (pi2c, I2C_STA_BB, 0) != OK)
  57. return ERROR;
  58. return (OK);
  59. }
  60. int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index)
  61. {
  62. pi2c->sr &= ~I2C_STA_IF; /* Clear Interrupt Bit */
  63. *readb = pi2c->dr; /* Read a byte */
  64. /*
  65. Set I2C_CTRL_TXAK will cause Transfer pending and
  66. set I2C_CTRL_STA will cause Interrupt pending
  67. */
  68. if (*index != 2) {
  69. if (spd_status (pi2c, I2C_STA_CF, 1) != OK) /* Transfer not complete? */
  70. return ERROR;
  71. }
  72. if (*index != 1) {
  73. if (spd_status (pi2c, I2C_STA_IF, 1) != OK)
  74. return ERROR;
  75. }
  76. return (OK);
  77. }
  78. int readSpdData (u8 * spdData)
  79. {
  80. volatile i2c8220_t *pi2cReg;
  81. volatile pcfg8220_t *pcfg;
  82. u8 slvAdr = DRAM_SPD;
  83. u8 Tmp;
  84. int Length = SPD_SIZE;
  85. int i = 0;
  86. /* Enable Port Configuration for SDA and SDL signals */
  87. pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
  88. __asm__ ("sync");
  89. pcfg->pcfg3 &= ~CONFIG_SYS_I2C_PORT3_CONFIG;
  90. __asm__ ("sync");
  91. /* Points the structure to I2c mbar memory offset */
  92. pi2cReg = (volatile i2c8220_t *) (MMAP_I2C);
  93. /* Clear FDR, ADR, SR and CR reg */
  94. pi2cReg->adr = 0;
  95. pi2cReg->fdr = 0;
  96. pi2cReg->cr = 0;
  97. pi2cReg->sr = 0;
  98. /* Set for fix XLB Bus Frequency */
  99. switch (gd->bus_clk) {
  100. case 60000000:
  101. pi2cReg->fdr = 0x15;
  102. break;
  103. case 70000000:
  104. pi2cReg->fdr = 0x16;
  105. break;
  106. case 80000000:
  107. pi2cReg->fdr = 0x3a;
  108. break;
  109. case 90000000:
  110. pi2cReg->fdr = 0x17;
  111. break;
  112. case 100000000:
  113. pi2cReg->fdr = 0x3b;
  114. break;
  115. case 110000000:
  116. pi2cReg->fdr = 0x18;
  117. break;
  118. case 120000000:
  119. pi2cReg->fdr = 0x19;
  120. break;
  121. case 130000000:
  122. pi2cReg->fdr = 0x1a;
  123. break;
  124. }
  125. pi2cReg->adr = CONFIG_SYS_I2C_SLAVE<<1;
  126. pi2cReg->cr = I2C_CTL_EN; /* Set Enable */
  127. /*
  128. The I2C bus should be in Idle state. If the bus is busy,
  129. clear the STA bit in control register
  130. */
  131. if (spd_status (pi2cReg, I2C_STA_BB, 0) != OK) {
  132. if ((pi2cReg->cr & I2C_CTL_STA) == I2C_CTL_STA)
  133. pi2cReg->cr &= ~I2C_CTL_STA;
  134. /* Check again if it is still busy, return error if found */
  135. if (spd_status (pi2cReg, I2C_STA_BB, 1) == OK)
  136. return ERROR;
  137. }
  138. pi2cReg->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */
  139. pi2cReg->cr |= I2C_CTL_STA; /* Generate start signal */
  140. if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK)
  141. return ERROR;
  142. /* Write slave address */
  143. pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
  144. pi2cReg->dr = slvAdr; /* Write a byte */
  145. if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
  146. spd_stop (pi2cReg);
  147. return ERROR;
  148. }
  149. if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
  150. spd_stop (pi2cReg);
  151. return ERROR;
  152. }
  153. /* Issue the offset to start */
  154. pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
  155. pi2cReg->dr = 0; /* Write a byte */
  156. if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
  157. spd_stop (pi2cReg);
  158. return ERROR;
  159. }
  160. if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
  161. spd_stop (pi2cReg);
  162. return ERROR;
  163. }
  164. /* Set repeat start */
  165. pi2cReg->cr |= I2C_CTL_RSTA; /* Repeat Start */
  166. pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
  167. pi2cReg->dr = slvAdr | 1; /* Write a byte */
  168. if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
  169. spd_stop (pi2cReg);
  170. return ERROR;
  171. }
  172. if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
  173. spd_stop (pi2cReg);
  174. return ERROR;
  175. }
  176. if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
  177. return ERROR;
  178. pi2cReg->cr &= ~I2C_CTL_TX; /* Set receive mode */
  179. if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
  180. return ERROR;
  181. /* Dummy Read */
  182. if (spd_readbyte (pi2cReg, &Tmp, &i) != OK) {
  183. spd_stop (pi2cReg);
  184. return ERROR;
  185. }
  186. i = 0;
  187. while (Length) {
  188. if (Length == 2)
  189. pi2cReg->cr |= I2C_CTL_TXAK;
  190. if (Length == 1)
  191. pi2cReg->cr &= ~I2C_CTL_STA;
  192. if (spd_readbyte (pi2cReg, spdData, &Length) != OK) {
  193. return spd_stop (pi2cReg);
  194. }
  195. i++;
  196. Length--;
  197. spdData++;
  198. }
  199. /* Stop the service */
  200. spd_stop (pi2cReg);
  201. return OK;
  202. }
  203. int getBankInfo (int bank, draminfo_t * pBank)
  204. {
  205. int status;
  206. int checksum;
  207. int count;
  208. u8 spdData[SPD_SIZE];
  209. if (bank > 2 || pBank == 0) {
  210. /* illegal values */
  211. return (-42);
  212. }
  213. status = readSpdData (&spdData[0]);
  214. if (status < 0)
  215. return (-1);
  216. /* check the checksum */
  217. for (count = 0, checksum = 0; count < LOC_CHECKSUM; count++)
  218. checksum += spdData[count];
  219. checksum = checksum - ((checksum / 256) * 256);
  220. if (checksum != spdData[LOC_CHECKSUM])
  221. return (-2);
  222. /* Get the memory type */
  223. if (!
  224. ((spdData[LOC_TYPE] == TYPE_DDR)
  225. || (spdData[LOC_TYPE] == TYPE_SDR)))
  226. /* not one of the types we support */
  227. return (-3);
  228. pBank->type = spdData[LOC_TYPE];
  229. /* Set logical banks */
  230. pBank->banks = spdData[LOC_LOGICAL_BANKS];
  231. /* Check that we have enough physical banks to cover the bank we are
  232. * figuring out. Odd-numbered banks correspond to the second bank
  233. * on the device.
  234. */
  235. if (bank & 1) {
  236. /* Second bank of a "device" */
  237. if (spdData[LOC_PHYS_BANKS] < 2)
  238. /* this bank doesn't exist on the "device" */
  239. return (-4);
  240. if (spdData[LOC_ROWS] & 0xf0)
  241. /* Two asymmetric banks */
  242. pBank->rows = spdData[LOC_ROWS] >> 4;
  243. else
  244. pBank->rows = spdData[LOC_ROWS];
  245. if (spdData[LOC_COLS] & 0xf0)
  246. /* Two asymmetric banks */
  247. pBank->cols = spdData[LOC_COLS] >> 4;
  248. else
  249. pBank->cols = spdData[LOC_COLS];
  250. } else {
  251. /* First bank of a "device" */
  252. pBank->rows = spdData[LOC_ROWS];
  253. pBank->cols = spdData[LOC_COLS];
  254. }
  255. pBank->width = spdData[LOC_WIDTH_HIGH] << 8 | spdData[LOC_WIDTH_LOW];
  256. pBank->bursts = spdData[LOC_BURSTS];
  257. pBank->CAS = spdData[LOC_CAS];
  258. pBank->CS = spdData[LOC_CS];
  259. pBank->WE = spdData[LOC_WE];
  260. pBank->Trp = spdData[LOC_Trp];
  261. pBank->Trcd = spdData[LOC_Trcd];
  262. pBank->buffered = spdData[LOC_Buffered] & 1;
  263. pBank->refresh = spdData[LOC_REFRESH];
  264. return (0);
  265. }
  266. /* checkMuxSetting -- given a row/column device geometry, return a mask
  267. * of the valid DRAM controller addr_mux settings for
  268. * that geometry.
  269. *
  270. * Arguments: u8 rows: number of row addresses in this device
  271. * u8 columns: number of column addresses in this device
  272. *
  273. * Returns: a mask of the allowed addr_mux settings for this
  274. * geometry. Each bit in the mask represents a
  275. * possible addr_mux settings (for example, the
  276. * (1<<2) bit in the mask represents the 0b10 setting)/
  277. *
  278. */
  279. u8 checkMuxSetting (u8 rows, u8 columns)
  280. {
  281. muxdesc_t *pIdx, *pMux;
  282. u8 mask;
  283. int lrows, lcolumns;
  284. u32 mux[4] = { 0x00080c04, 0x01080d03, 0x02080e02, 0xffffffff };
  285. /* Setup MuxDescriptor in SRAM space */
  286. /* MUXDESC AddressRuns [] = {
  287. { 0, 8, 12, 4 }, / setting, columns, rows, extra columns /
  288. { 1, 8, 13, 3 }, / setting, columns, rows, extra columns /
  289. { 2, 8, 14, 2 }, / setting, columns, rows, extra columns /
  290. { 0xff } / list terminator /
  291. }; */
  292. pIdx = (muxdesc_t *) & mux[0];
  293. /* Check rows x columns against each possible address mux setting */
  294. for (pMux = pIdx, mask = 0;; pMux++) {
  295. lrows = rows;
  296. lcolumns = columns;
  297. if (pMux->MuxValue == 0xff)
  298. break; /* end of list */
  299. /* For a given mux setting, since we want all the memory in a
  300. * device to be contiguous, we want the device "use up" the
  301. * address lines such that there are no extra column or row
  302. * address lines on the device.
  303. */
  304. lcolumns -= pMux->Columns;
  305. if (lcolumns < 0)
  306. /* Not enough columns to get to the rows */
  307. continue;
  308. lrows -= pMux->Rows;
  309. if (lrows > 0)
  310. /* we have extra rows left -- can't do that! */
  311. continue;
  312. /* At this point, we either have to have used up all the
  313. * rows or we have to have no columns left.
  314. */
  315. if (lcolumns != 0 && lrows != 0)
  316. /* rows AND columns are left. Bad! */
  317. continue;
  318. lcolumns -= pMux->MoreColumns;
  319. if (lcolumns <= 0)
  320. mask |= (1 << pMux->MuxValue);
  321. }
  322. return (mask);
  323. }
  324. u32 dramSetup (void)
  325. {
  326. draminfo_t DramInfo[TOTAL_BANK];
  327. draminfo_t *pDramInfo;
  328. u32 size, temp, cfg_value, mode_value, refresh;
  329. u8 *ptr;
  330. u8 bursts, Trp, Trcd, type, buffered;
  331. u8 muxmask, rows, columns;
  332. int count, banknum;
  333. u32 *prefresh, *pIdx;
  334. u32 refrate[8] = { 15625, 3900, 7800, 31300,
  335. 62500, 125000, 0xffffffff, 0xffffffff
  336. };
  337. volatile sysconf8220_t *sysconf;
  338. volatile memctl8220_t *memctl;
  339. sysconf = (volatile sysconf8220_t *) MMAP_MBAR;
  340. memctl = (volatile memctl8220_t *) MMAP_MEMCTL;
  341. /* Set everything in the descriptions to zero */
  342. ptr = (u8 *) & DramInfo[0];
  343. for (count = 0; count < sizeof (DramInfo); count++)
  344. *ptr++ = 0;
  345. for (banknum = 0; banknum < TOTAL_BANK; banknum++)
  346. sysconf->cscfg[banknum];
  347. /* Descriptions of row/column address muxing for various
  348. * addr_mux settings.
  349. */
  350. pIdx = prefresh = (u32 *) & refrate[0];
  351. /* Get all the info for all three logical banks */
  352. bursts = 0xff;
  353. Trp = 0;
  354. Trcd = 0;
  355. type = 0;
  356. buffered = 0xff;
  357. refresh = 0xffffffff;
  358. muxmask = 0xff;
  359. /* Two bank, CS0 and CS1 */
  360. for (banknum = 0, pDramInfo = &DramInfo[0];
  361. banknum < TOTAL_BANK; banknum++, pDramInfo++) {
  362. pDramInfo->ordinal = banknum; /* initial sorting */
  363. if (getBankInfo (banknum, pDramInfo) < 0)
  364. continue;
  365. /* get cumulative parameters of all three banks */
  366. if (type && pDramInfo->type != type)
  367. return 0;
  368. type = pDramInfo->type;
  369. rows = pDramInfo->rows;
  370. columns = pDramInfo->cols;
  371. /* This chip only supports 13 DRAM memory lines, but some devices
  372. * have 14 rows. To deal with this, ignore the 14th address line
  373. * by limiting the number of rows (and columns) to 13. This will
  374. * mean that for 14-row devices we will only be able to use
  375. * half of the memory, but it's better than nothing.
  376. */
  377. if (rows > 13)
  378. rows = 13;
  379. if (columns > 13)
  380. columns = 13;
  381. pDramInfo->size =
  382. ((1 << (rows + columns)) * pDramInfo->width);
  383. pDramInfo->size *= pDramInfo->banks;
  384. pDramInfo->size >>= 3;
  385. /* figure out which addr_mux configurations will support this device */
  386. muxmask &= checkMuxSetting (rows, columns);
  387. if (muxmask == 0)
  388. return 0;
  389. buffered = pDramInfo->buffered;
  390. bursts &= pDramInfo->bursts; /* union of all bursts */
  391. if (pDramInfo->Trp > Trp) /* worst case (longest) Trp */
  392. Trp = pDramInfo->Trp;
  393. if (pDramInfo->Trcd > Trcd) /* worst case (longest) Trcd */
  394. Trcd = pDramInfo->Trcd;
  395. prefresh = pIdx;
  396. /* worst case (shortest) Refresh period */
  397. if (refresh > prefresh[pDramInfo->refresh & 7])
  398. refresh = prefresh[pDramInfo->refresh & 7];
  399. } /* for loop */
  400. /* We only allow a burst length of 8! */
  401. if (!(bursts & 8))
  402. bursts = 8;
  403. /* Sort the devices. In order to get each chip select region
  404. * aligned properly, put the biggest device at the lowest address.
  405. * A simple bubble sort will do the trick.
  406. */
  407. for (banknum = 0, pDramInfo = &DramInfo[0];
  408. banknum < TOTAL_BANK; banknum++, pDramInfo++) {
  409. int i;
  410. for (i = 0; i < TOTAL_BANK; i++) {
  411. if (pDramInfo->size < DramInfo[i].size &&
  412. pDramInfo->ordinal < DramInfo[i].ordinal) {
  413. /* If the current bank is smaller, but if the ordinal is also
  414. * smaller, swap the ordinals
  415. */
  416. u8 temp8;
  417. temp8 = DramInfo[i].ordinal;
  418. DramInfo[i].ordinal = pDramInfo->ordinal;
  419. pDramInfo->ordinal = temp8;
  420. }
  421. }
  422. }
  423. /* Now figure out the base address for each bank. While
  424. * we're at it, figure out how much memory there is.
  425. *
  426. */
  427. size = 0;
  428. for (banknum = 0; banknum < TOTAL_BANK; banknum++) {
  429. int i;
  430. for (i = 0; i < TOTAL_BANK; i++) {
  431. if (DramInfo[i].ordinal == banknum
  432. && DramInfo[i].size != 0) {
  433. DramInfo[i].base = size;
  434. size += DramInfo[i].size;
  435. }
  436. }
  437. }
  438. /* Set up the Drive Strength register */
  439. sysconf->sdramds = CONFIG_SYS_SDRAM_DRIVE_STRENGTH;
  440. /* ********************** Cfg 1 ************************* */
  441. /* Set the single read to read/write/precharge delay */
  442. cfg_value = CFG1_SRD2RWP ((type == TYPE_DDR) ? 7 : 0xb);
  443. /* Set the single write to read/write/precharge delay.
  444. * This may or may not be correct. The controller spec
  445. * says "tWR", but "tWR" does not appear in the SPD. It
  446. * always seems to be 15nsec for the class of device we're
  447. * using, which turns out to be 2 clock cycles at 133MHz,
  448. * so that's what we're going to use.
  449. *
  450. * HOWEVER, because of a bug in the controller, for DDR
  451. * we need to set this to be the same as the value
  452. * calculated for bwt2rwp.
  453. */
  454. cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2);
  455. /* Set the Read CAS latency. We're going to use a CL of
  456. * 2.5 for DDR and 2 SDR.
  457. */
  458. cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2);
  459. /* Set the Active to Read/Write delay. This depends
  460. * on Trcd which is reported as nanoseconds times 4.
  461. * We want to calculate Trcd (in nanoseconds) times XLB clock (in Hz)
  462. * which gives us a dimensionless quantity. Play games with
  463. * the divisions so we don't run out of dynamic ranges.
  464. */
  465. /* account for megaherz and the times 4 */
  466. temp = (Trcd * (gd->bus_clk / 1000000)) / 4;
  467. /* account for nanoseconds and round up, with a minimum value of 2 */
  468. temp = ((temp + 999) / 1000) - 1;
  469. if (temp < 2)
  470. temp = 2;
  471. cfg_value |= CFG1_ACT2WR (temp);
  472. /* Set the precharge to active delay. This depends
  473. * on Trp which is reported as nanoseconds times 4.
  474. * We want to calculate Trp (in nanoseconds) times XLB clock (in Hz)
  475. * which gives us a dimensionless quantity. Play games with
  476. * the divisions so we don't run out of dynamic ranges.
  477. */
  478. /* account for megaherz and the times 4 */
  479. temp = (Trp * (gd->bus_clk / 1000000)) / 4;
  480. /* account for nanoseconds and round up, then subtract 1, with a
  481. * minumum value of 1 and a maximum value of 7.
  482. */
  483. temp = (((temp + 999) / 1000) - 1) & 7;
  484. if (temp < 1)
  485. temp = 1;
  486. cfg_value |= CFG1_PRE2ACT (temp);
  487. /* Set refresh to active delay. This depends
  488. * on Trfc which is not reported in the SPD.
  489. * We'll use a nominal value of 75nsec which is
  490. * what the controller spec uses.
  491. */
  492. temp = (75 * (gd->bus_clk / 1000000));
  493. /* account for nanoseconds and round up, then subtract 1 */
  494. cfg_value |= CFG1_REF2ACT (((temp + 999) / 1000) - 1);
  495. /* Set the write latency, using the values given in the controller spec */
  496. cfg_value |= CFG1_WLATENCY ((type == TYPE_DDR) ? 3 : 0);
  497. memctl->cfg1 = cfg_value; /* cfg 1 */
  498. asm volatile ("sync");
  499. /* ********************** Cfg 2 ************************* */
  500. /* Set the burst read to read/precharge delay */
  501. cfg_value = CFG2_BRD2RP ((type == TYPE_DDR) ? 5 : 8);
  502. /* Set the burst write to read/precharge delay. Semi-magic numbers
  503. * based on the controller spec recommendations, assuming tWR is
  504. * two clock cycles.
  505. */
  506. cfg_value |= CFG2_BWT2RWP ((type == TYPE_DDR) ? 7 : 10);
  507. /* Set the Burst read to write delay. Semi-magic numbers
  508. * based on the DRAM controller documentation.
  509. */
  510. cfg_value |= CFG2_BRD2WT ((type == TYPE_DDR) ? 7 : 0xb);
  511. /* Set the burst length -- must be 8!! Well, 7, actually, becuase
  512. * it's burst lenght minus 1.
  513. */
  514. cfg_value |= CFG2_BURSTLEN (7);
  515. memctl->cfg2 = cfg_value; /* cfg 2 */
  516. asm volatile ("sync");
  517. /* ********************** mode ************************* */
  518. /* Set enable bit, CKE high/low bits, and the DDR/SDR mode bit,
  519. * disable automatic refresh.
  520. */
  521. cfg_value = CTL_MODE_ENABLE | CTL_CKE_HIGH |
  522. ((type == TYPE_DDR) ? CTL_DDR_MODE : 0);
  523. /* Set the address mux based on whichever setting(s) is/are common
  524. * to all the devices we have. If there is more than one, choose
  525. * one arbitrarily.
  526. */
  527. if (muxmask & 0x4)
  528. cfg_value |= CTL_ADDRMUX (2);
  529. else if (muxmask & 0x2)
  530. cfg_value |= CTL_ADDRMUX (1);
  531. else
  532. cfg_value |= CTL_ADDRMUX (0);
  533. /* Set the refresh interval. */
  534. temp = ((refresh * (gd->bus_clk / 1000000)) / (1000 * 64)) - 1;
  535. cfg_value |= CTL_REFRESH_INTERVAL (temp);
  536. /* Set buffered/non-buffered memory */
  537. if (buffered)
  538. cfg_value |= CTL_BUFFERED;
  539. memctl->ctrl = cfg_value; /* ctrl */
  540. asm volatile ("sync");
  541. if (type == TYPE_DDR) {
  542. /* issue precharge all */
  543. temp = cfg_value | CTL_PRECHARGE_CMD;
  544. memctl->ctrl = temp; /* ctrl */
  545. asm volatile ("sync");
  546. }
  547. /* Set up mode value for CAS latency */
  548. #if (CONFIG_SYS_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
  549. mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
  550. MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
  551. #else
  552. mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
  553. MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD);
  554. #endif
  555. asm volatile ("sync");
  556. /* Write Extended Mode - enable DLL */
  557. if (type == TYPE_DDR) {
  558. temp = MODE_EXTENDED | MODE_X_DLL_ENABLE |
  559. MODE_X_DS_NORMAL | MODE_CMD;
  560. memctl->mode = (temp >> 16); /* mode */
  561. asm volatile ("sync");
  562. /* Write Mode - reset DLL, set CAS latency */
  563. temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL);
  564. memctl->mode = (temp >> 16); /* mode */
  565. asm volatile ("sync");
  566. }
  567. /* Program the chip selects. */
  568. for (banknum = 0; banknum < TOTAL_BANK; banknum++) {
  569. if (DramInfo[banknum].size != 0) {
  570. u32 mask;
  571. int i;
  572. for (i = 0, mask = 1; i < 32; mask <<= 1, i++) {
  573. if (DramInfo[banknum].size & mask)
  574. break;
  575. }
  576. temp = (DramInfo[banknum].base & 0xfff00000) | (i -
  577. 1);
  578. sysconf->cscfg[banknum] = temp;
  579. asm volatile ("sync");
  580. }
  581. }
  582. /* Wait for DLL lock */
  583. udelay (200);
  584. temp = cfg_value | CTL_PRECHARGE_CMD; /* issue precharge all */
  585. memctl->ctrl = temp; /* ctrl */
  586. asm volatile ("sync");
  587. temp = cfg_value | CTL_REFRESH_CMD; /* issue precharge all */
  588. memctl->ctrl = temp; /* ctrl */
  589. asm volatile ("sync");
  590. memctl->ctrl = temp; /* ctrl */
  591. asm volatile ("sync");
  592. /* Write Mode - DLL normal */
  593. temp = mode_value | MODE_OPMODE (MODE_OPMODE_NORMAL);
  594. memctl->mode = (temp >> 16); /* mode */
  595. asm volatile ("sync");
  596. /* Enable refresh, enable DQS's (if DDR), and lock the control register */
  597. cfg_value &= ~CTL_MODE_ENABLE; /* lock register */
  598. cfg_value |= CTL_REFRESH_ENABLE; /* enable refresh */
  599. if (type == TYPE_DDR)
  600. cfg_value |= CTL_DQSOEN (0xf); /* enable DQS's for DDR */
  601. memctl->ctrl = cfg_value; /* ctrl */
  602. asm volatile ("sync");
  603. return size;
  604. }