usb_ohci.c 44 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
  3. *
  4. * (C) Copyright 2003-2004
  5. * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  6. *
  7. * (C) Copyright 2004
  8. * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
  9. *
  10. * Note: Much of this code has been derived from Linux 2.4
  11. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  12. * (C) Copyright 2000-2002 David Brownell
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - this driver is intended for use with USB Mass Storage Devices
  36. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  37. */
  38. #include <common.h>
  39. #ifdef CONFIG_USB_OHCI
  40. #include <malloc.h>
  41. #include <usb.h>
  42. #include "usb_ohci.h"
  43. #include <mpc5xxx.h>
  44. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  45. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  46. #undef DEBUG
  47. #undef SHOW_INFO
  48. #undef OHCI_FILL_TRACE
  49. /* For initializing controller (mask in an HCFS mode too) */
  50. #define OHCI_CONTROL_INIT \
  51. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  52. #define readl(a) (*((volatile u32 *)(a)))
  53. #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
  54. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  55. #ifdef DEBUG
  56. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  57. #else
  58. #define dbg(format, arg...) do {} while(0)
  59. #endif /* DEBUG */
  60. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  61. #ifdef SHOW_INFO
  62. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  63. #else
  64. #define info(format, arg...) do {} while(0)
  65. #endif
  66. #define m16_swap(x) swap_16(x)
  67. #define m32_swap(x) swap_32(x)
  68. #define ohci_cpu_to_le16(x) (x)
  69. #define ohci_cpu_to_le32(x) (x)
  70. /* global ohci_t */
  71. static ohci_t gohci;
  72. /* this must be aligned to a 256 byte boundary */
  73. struct ohci_hcca ghcca[1];
  74. /* a pointer to the aligned storage */
  75. struct ohci_hcca *phcca;
  76. /* this allocates EDs for all possible endpoints */
  77. struct ohci_device ohci_dev;
  78. /* urb_priv */
  79. urb_priv_t urb_priv;
  80. /* RHSC flag */
  81. int got_rhsc;
  82. /* device which was disconnected */
  83. struct usb_device *devgone;
  84. /* flag guarding URB transation */
  85. int urb_finished = 0;
  86. /*-------------------------------------------------------------------------*/
  87. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  88. * The erratum (#4) description is incorrect. AMD's workaround waits
  89. * till some bits (mostly reserved) are clear; ok for all revs.
  90. */
  91. #define OHCI_QUIRK_AMD756 0xabcd
  92. #define read_roothub(hc, register, mask) ({ \
  93. u32 temp = readl (&hc->regs->roothub.register); \
  94. if (hc->flags & OHCI_QUIRK_AMD756) \
  95. while (temp & mask) \
  96. temp = readl (&hc->regs->roothub.register); \
  97. temp; })
  98. static u32 roothub_a (struct ohci *hc)
  99. { return read_roothub (hc, a, 0xfc0fe000); }
  100. static inline u32 roothub_b (struct ohci *hc)
  101. { return readl (&hc->regs->roothub.b); }
  102. static inline u32 roothub_status (struct ohci *hc)
  103. { return readl (&hc->regs->roothub.status); }
  104. static u32 roothub_portstatus (struct ohci *hc, int i)
  105. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  106. /* forward declaration */
  107. static int hc_interrupt (void);
  108. static void
  109. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  110. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  111. /*-------------------------------------------------------------------------*
  112. * URB support functions
  113. *-------------------------------------------------------------------------*/
  114. /* free HCD-private data associated with this URB */
  115. static void urb_free_priv (urb_priv_t * urb)
  116. {
  117. int i;
  118. int last;
  119. struct td * td;
  120. last = urb->length - 1;
  121. if (last >= 0) {
  122. for (i = 0; i <= last; i++) {
  123. td = urb->td[i];
  124. if (td) {
  125. td->usb_dev = NULL;
  126. urb->td[i] = NULL;
  127. }
  128. }
  129. }
  130. }
  131. /*-------------------------------------------------------------------------*/
  132. #ifdef DEBUG
  133. static int sohci_get_current_frame_number (struct usb_device * dev);
  134. /* debug| print the main components of an URB
  135. * small: 0) header + data packets 1) just header */
  136. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  137. int transfer_len, struct devrequest * setup, char * str, int small)
  138. {
  139. urb_priv_t * purb = &urb_priv;
  140. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  141. str,
  142. sohci_get_current_frame_number (dev),
  143. usb_pipedevice (pipe),
  144. usb_pipeendpoint (pipe),
  145. usb_pipeout (pipe)? 'O': 'I',
  146. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  147. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  148. purb->actual_length,
  149. transfer_len, dev->status);
  150. #ifdef OHCI_VERBOSE_DEBUG
  151. if (!small) {
  152. int i, len;
  153. if (usb_pipecontrol (pipe)) {
  154. printf (__FILE__ ": cmd(8):");
  155. for (i = 0; i < 8 ; i++)
  156. printf (" %02x", ((__u8 *) setup) [i]);
  157. printf ("\n");
  158. }
  159. if (transfer_len > 0 && buffer) {
  160. printf (__FILE__ ": data(%d/%d):",
  161. purb->actual_length,
  162. transfer_len);
  163. len = usb_pipeout (pipe)?
  164. transfer_len: purb->actual_length;
  165. for (i = 0; i < 16 && i < len; i++)
  166. printf (" %02x", ((__u8 *) buffer) [i]);
  167. printf ("%s\n", i < len? "...": "");
  168. }
  169. }
  170. #endif
  171. }
  172. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  173. void ep_print_int_eds (ohci_t *ohci, char * str) {
  174. int i, j;
  175. __u32 * ed_p;
  176. for (i= 0; i < 32; i++) {
  177. j = 5;
  178. ed_p = &(ohci->hcca->int_table [i]);
  179. if (*ed_p == 0)
  180. continue;
  181. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  182. while (*ed_p != 0 && j--) {
  183. ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
  184. printf (" ed: %4x;", ed->hwINFO);
  185. ed_p = &ed->hwNextED;
  186. }
  187. printf ("\n");
  188. }
  189. }
  190. static void ohci_dump_intr_mask (char *label, __u32 mask)
  191. {
  192. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  193. label,
  194. mask,
  195. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  196. (mask & OHCI_INTR_OC) ? " OC" : "",
  197. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  198. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  199. (mask & OHCI_INTR_UE) ? " UE" : "",
  200. (mask & OHCI_INTR_RD) ? " RD" : "",
  201. (mask & OHCI_INTR_SF) ? " SF" : "",
  202. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  203. (mask & OHCI_INTR_SO) ? " SO" : ""
  204. );
  205. }
  206. static void maybe_print_eds (char *label, __u32 value)
  207. {
  208. ed_t *edp = (ed_t *)value;
  209. if (value) {
  210. dbg ("%s %08x", label, value);
  211. dbg ("%08x", edp->hwINFO);
  212. dbg ("%08x", edp->hwTailP);
  213. dbg ("%08x", edp->hwHeadP);
  214. dbg ("%08x", edp->hwNextED);
  215. }
  216. }
  217. static char * hcfs2string (int state)
  218. {
  219. switch (state) {
  220. case OHCI_USB_RESET: return "reset";
  221. case OHCI_USB_RESUME: return "resume";
  222. case OHCI_USB_OPER: return "operational";
  223. case OHCI_USB_SUSPEND: return "suspend";
  224. }
  225. return "?";
  226. }
  227. /* dump control and status registers */
  228. static void ohci_dump_status (ohci_t *controller)
  229. {
  230. struct ohci_regs *regs = controller->regs;
  231. __u32 temp;
  232. temp = readl (&regs->revision) & 0xff;
  233. if (temp != 0x10)
  234. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  235. temp = readl (&regs->control);
  236. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  237. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  238. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  239. (temp & OHCI_CTRL_IR) ? " IR" : "",
  240. hcfs2string (temp & OHCI_CTRL_HCFS),
  241. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  242. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  243. (temp & OHCI_CTRL_IE) ? " IE" : "",
  244. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  245. temp & OHCI_CTRL_CBSR
  246. );
  247. temp = readl (&regs->cmdstatus);
  248. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  249. (temp & OHCI_SOC) >> 16,
  250. (temp & OHCI_OCR) ? " OCR" : "",
  251. (temp & OHCI_BLF) ? " BLF" : "",
  252. (temp & OHCI_CLF) ? " CLF" : "",
  253. (temp & OHCI_HCR) ? " HCR" : ""
  254. );
  255. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  256. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  257. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  258. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  259. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  260. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  261. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  262. maybe_print_eds ("donehead", readl (&regs->donehead));
  263. }
  264. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  265. {
  266. __u32 temp, ndp, i;
  267. temp = roothub_a (controller);
  268. ndp = (temp & RH_A_NDP);
  269. if (verbose) {
  270. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  271. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  272. (temp & RH_A_NOCP) ? " NOCP" : "",
  273. (temp & RH_A_OCPM) ? " OCPM" : "",
  274. (temp & RH_A_DT) ? " DT" : "",
  275. (temp & RH_A_NPS) ? " NPS" : "",
  276. (temp & RH_A_PSM) ? " PSM" : "",
  277. ndp
  278. );
  279. temp = roothub_b (controller);
  280. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  281. temp,
  282. (temp & RH_B_PPCM) >> 16,
  283. (temp & RH_B_DR)
  284. );
  285. temp = roothub_status (controller);
  286. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  287. temp,
  288. (temp & RH_HS_CRWE) ? " CRWE" : "",
  289. (temp & RH_HS_OCIC) ? " OCIC" : "",
  290. (temp & RH_HS_LPSC) ? " LPSC" : "",
  291. (temp & RH_HS_DRWE) ? " DRWE" : "",
  292. (temp & RH_HS_OCI) ? " OCI" : "",
  293. (temp & RH_HS_LPS) ? " LPS" : ""
  294. );
  295. }
  296. for (i = 0; i < ndp; i++) {
  297. temp = roothub_portstatus (controller, i);
  298. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  299. i,
  300. temp,
  301. (temp & RH_PS_PRSC) ? " PRSC" : "",
  302. (temp & RH_PS_OCIC) ? " OCIC" : "",
  303. (temp & RH_PS_PSSC) ? " PSSC" : "",
  304. (temp & RH_PS_PESC) ? " PESC" : "",
  305. (temp & RH_PS_CSC) ? " CSC" : "",
  306. (temp & RH_PS_LSDA) ? " LSDA" : "",
  307. (temp & RH_PS_PPS) ? " PPS" : "",
  308. (temp & RH_PS_PRS) ? " PRS" : "",
  309. (temp & RH_PS_POCI) ? " POCI" : "",
  310. (temp & RH_PS_PSS) ? " PSS" : "",
  311. (temp & RH_PS_PES) ? " PES" : "",
  312. (temp & RH_PS_CCS) ? " CCS" : ""
  313. );
  314. }
  315. }
  316. static void ohci_dump (ohci_t *controller, int verbose)
  317. {
  318. dbg ("OHCI controller usb-%s state", controller->slot_name);
  319. /* dumps some of the state we know about */
  320. ohci_dump_status (controller);
  321. if (verbose)
  322. ep_print_int_eds (controller, "hcca");
  323. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  324. ohci_dump_roothub (controller, 1);
  325. }
  326. #endif /* DEBUG */
  327. /*-------------------------------------------------------------------------*
  328. * Interface functions (URB)
  329. *-------------------------------------------------------------------------*/
  330. /* get a transfer request */
  331. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  332. int transfer_len, struct devrequest *setup, int interval)
  333. {
  334. ohci_t *ohci;
  335. ed_t * ed;
  336. urb_priv_t *purb_priv;
  337. int i, size = 0;
  338. ohci = &gohci;
  339. /* when controller's hung, permit only roothub cleanup attempts
  340. * such as powering down ports */
  341. if (ohci->disabled) {
  342. err("sohci_submit_job: EPIPE");
  343. return -1;
  344. }
  345. /* if we have an unfinished URB from previous transaction let's
  346. * fail and scream as quickly as possible so as not to corrupt
  347. * further communication */
  348. if (!urb_finished) {
  349. err("sohci_submit_job: URB NOT FINISHED");
  350. return -1;
  351. }
  352. /* we're about to begin a new transaction here so mark the URB unfinished */
  353. urb_finished = 0;
  354. /* every endpoint has a ed, locate and fill it */
  355. if (!(ed = ep_add_ed (dev, pipe))) {
  356. err("sohci_submit_job: ENOMEM");
  357. return -1;
  358. }
  359. /* for the private part of the URB we need the number of TDs (size) */
  360. switch (usb_pipetype (pipe)) {
  361. case PIPE_BULK: /* one TD for every 4096 Byte */
  362. size = (transfer_len - 1) / 4096 + 1;
  363. break;
  364. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  365. size = (transfer_len == 0)? 2:
  366. (transfer_len - 1) / 4096 + 3;
  367. break;
  368. }
  369. if (size >= (N_URB_TD - 1)) {
  370. err("need %d TDs, only have %d", size, N_URB_TD);
  371. return -1;
  372. }
  373. purb_priv = &urb_priv;
  374. purb_priv->pipe = pipe;
  375. /* fill the private part of the URB */
  376. purb_priv->length = size;
  377. purb_priv->ed = ed;
  378. purb_priv->actual_length = 0;
  379. /* allocate the TDs */
  380. /* note that td[0] was allocated in ep_add_ed */
  381. for (i = 0; i < size; i++) {
  382. purb_priv->td[i] = td_alloc (dev);
  383. if (!purb_priv->td[i]) {
  384. purb_priv->length = i;
  385. urb_free_priv (purb_priv);
  386. err("sohci_submit_job: ENOMEM");
  387. return -1;
  388. }
  389. }
  390. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  391. urb_free_priv (purb_priv);
  392. err("sohci_submit_job: EINVAL");
  393. return -1;
  394. }
  395. /* link the ed into a chain if is not already */
  396. if (ed->state != ED_OPER)
  397. ep_link (ohci, ed);
  398. /* fill the TDs and link it to the ed */
  399. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  400. return 0;
  401. }
  402. /*-------------------------------------------------------------------------*/
  403. #ifdef DEBUG
  404. /* tell us the current USB frame number */
  405. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  406. {
  407. ohci_t *ohci = &gohci;
  408. return ohci_cpu_to_le16 (ohci->hcca->frame_no);
  409. }
  410. #endif
  411. /*-------------------------------------------------------------------------*
  412. * ED handling functions
  413. *-------------------------------------------------------------------------*/
  414. /* link an ed into one of the HC chains */
  415. static int ep_link (ohci_t *ohci, ed_t *edi)
  416. {
  417. volatile ed_t *ed = edi;
  418. ed->state = ED_OPER;
  419. switch (ed->type) {
  420. case PIPE_CONTROL:
  421. ed->hwNextED = 0;
  422. if (ohci->ed_controltail == NULL) {
  423. writel (ed, &ohci->regs->ed_controlhead);
  424. } else {
  425. ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  426. }
  427. ed->ed_prev = ohci->ed_controltail;
  428. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  429. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  430. ohci->hc_control |= OHCI_CTRL_CLE;
  431. writel (ohci->hc_control, &ohci->regs->control);
  432. }
  433. ohci->ed_controltail = edi;
  434. break;
  435. case PIPE_BULK:
  436. ed->hwNextED = 0;
  437. if (ohci->ed_bulktail == NULL) {
  438. writel (ed, &ohci->regs->ed_bulkhead);
  439. } else {
  440. ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  441. }
  442. ed->ed_prev = ohci->ed_bulktail;
  443. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  444. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  445. ohci->hc_control |= OHCI_CTRL_BLE;
  446. writel (ohci->hc_control, &ohci->regs->control);
  447. }
  448. ohci->ed_bulktail = edi;
  449. break;
  450. }
  451. return 0;
  452. }
  453. /*-------------------------------------------------------------------------*/
  454. /* unlink an ed from one of the HC chains.
  455. * just the link to the ed is unlinked.
  456. * the link from the ed still points to another operational ed or 0
  457. * so the HC can eventually finish the processing of the unlinked ed */
  458. static int ep_unlink (ohci_t *ohci, ed_t *edi)
  459. {
  460. volatile ed_t *ed = edi;
  461. ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
  462. switch (ed->type) {
  463. case PIPE_CONTROL:
  464. if (ed->ed_prev == NULL) {
  465. if (!ed->hwNextED) {
  466. ohci->hc_control &= ~OHCI_CTRL_CLE;
  467. writel (ohci->hc_control, &ohci->regs->control);
  468. }
  469. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  470. } else {
  471. ed->ed_prev->hwNextED = ed->hwNextED;
  472. }
  473. if (ohci->ed_controltail == ed) {
  474. ohci->ed_controltail = ed->ed_prev;
  475. } else {
  476. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  477. }
  478. break;
  479. case PIPE_BULK:
  480. if (ed->ed_prev == NULL) {
  481. if (!ed->hwNextED) {
  482. ohci->hc_control &= ~OHCI_CTRL_BLE;
  483. writel (ohci->hc_control, &ohci->regs->control);
  484. }
  485. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  486. } else {
  487. ed->ed_prev->hwNextED = ed->hwNextED;
  488. }
  489. if (ohci->ed_bulktail == ed) {
  490. ohci->ed_bulktail = ed->ed_prev;
  491. } else {
  492. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  493. }
  494. break;
  495. }
  496. ed->state = ED_UNLINK;
  497. return 0;
  498. }
  499. /*-------------------------------------------------------------------------*/
  500. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  501. * but the USB stack is a little bit stateless so we do it at every transaction
  502. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  503. * in all other cases the state is left unchanged
  504. * the ed info fields are setted anyway even though most of them should not change */
  505. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  506. {
  507. td_t *td;
  508. ed_t *ed_ret;
  509. volatile ed_t *ed;
  510. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  511. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  512. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  513. err("ep_add_ed: pending delete");
  514. /* pending delete request */
  515. return NULL;
  516. }
  517. if (ed->state == ED_NEW) {
  518. ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
  519. /* dummy td; end of td list for ed */
  520. td = td_alloc (usb_dev);
  521. ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
  522. ed->hwHeadP = ed->hwTailP;
  523. ed->state = ED_UNLINK;
  524. ed->type = usb_pipetype (pipe);
  525. ohci_dev.ed_cnt++;
  526. }
  527. ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
  528. | usb_pipeendpoint (pipe) << 7
  529. | (usb_pipeisoc (pipe)? 0x8000: 0)
  530. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  531. | usb_pipeslow (pipe) << 13
  532. | usb_maxpacket (usb_dev, pipe) << 16);
  533. return ed_ret;
  534. }
  535. /*-------------------------------------------------------------------------*
  536. * TD handling functions
  537. *-------------------------------------------------------------------------*/
  538. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  539. static void td_fill (ohci_t *ohci, unsigned int info,
  540. void *data, int len,
  541. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  542. {
  543. volatile td_t *td, *td_pt;
  544. #ifdef OHCI_FILL_TRACE
  545. int i;
  546. #endif
  547. if (index > urb_priv->length) {
  548. err("index > length");
  549. return;
  550. }
  551. /* use this td as the next dummy */
  552. td_pt = urb_priv->td [index];
  553. td_pt->hwNextTD = 0;
  554. /* fill the old dummy TD */
  555. td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
  556. td->ed = urb_priv->ed;
  557. td->next_dl_td = NULL;
  558. td->index = index;
  559. td->data = (__u32)data;
  560. #ifdef OHCI_FILL_TRACE
  561. if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
  562. for (i = 0; i < len; i++)
  563. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  564. printf("\n");
  565. }
  566. #endif
  567. if (!len)
  568. data = 0;
  569. td->hwINFO = ohci_cpu_to_le32 (info);
  570. td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
  571. if (data)
  572. td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
  573. else
  574. td->hwBE = 0;
  575. td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
  576. /* append to queue */
  577. td->ed->hwTailP = td->hwNextTD;
  578. }
  579. /*-------------------------------------------------------------------------*/
  580. /* prepare all TDs of a transfer */
  581. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  582. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  583. {
  584. ohci_t *ohci = &gohci;
  585. int data_len = transfer_len;
  586. void *data;
  587. int cnt = 0;
  588. __u32 info = 0;
  589. unsigned int toggle = 0;
  590. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  591. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  592. toggle = TD_T_TOGGLE;
  593. } else {
  594. toggle = TD_T_DATA0;
  595. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  596. }
  597. urb->td_cnt = 0;
  598. if (data_len)
  599. data = buffer;
  600. else
  601. data = 0;
  602. switch (usb_pipetype (pipe)) {
  603. case PIPE_BULK:
  604. info = usb_pipeout (pipe)?
  605. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  606. while(data_len > 4096) {
  607. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  608. data += 4096; data_len -= 4096; cnt++;
  609. }
  610. info = usb_pipeout (pipe)?
  611. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  612. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  613. cnt++;
  614. if (!ohci->sleeping)
  615. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  616. break;
  617. case PIPE_CONTROL:
  618. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  619. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  620. if (data_len > 0) {
  621. info = usb_pipeout (pipe)?
  622. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  623. /* NOTE: mishandles transfers >8K, some >4K */
  624. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  625. }
  626. info = usb_pipeout (pipe)?
  627. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  628. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  629. if (!ohci->sleeping)
  630. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  631. break;
  632. }
  633. if (urb->length != cnt)
  634. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  635. }
  636. /*-------------------------------------------------------------------------*
  637. * Done List handling functions
  638. *-------------------------------------------------------------------------*/
  639. /* calculate the transfer length and update the urb */
  640. static void dl_transfer_length(td_t * td)
  641. {
  642. __u32 tdINFO, tdBE, tdCBP;
  643. urb_priv_t *lurb_priv = &urb_priv;
  644. tdINFO = ohci_cpu_to_le32 (td->hwINFO);
  645. tdBE = ohci_cpu_to_le32 (td->hwBE);
  646. tdCBP = ohci_cpu_to_le32 (td->hwCBP);
  647. if (!(usb_pipecontrol(lurb_priv->pipe) &&
  648. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  649. if (tdBE != 0) {
  650. if (td->hwCBP == 0)
  651. lurb_priv->actual_length += tdBE - td->data + 1;
  652. else
  653. lurb_priv->actual_length += tdCBP - td->data;
  654. }
  655. }
  656. }
  657. /*-------------------------------------------------------------------------*/
  658. /* replies to the request have to be on a FIFO basis so
  659. * we reverse the reversed done-list */
  660. static td_t * dl_reverse_done_list (ohci_t *ohci)
  661. {
  662. __u32 td_list_hc;
  663. td_t *td_rev = NULL;
  664. td_t *td_list = NULL;
  665. urb_priv_t *lurb_priv = NULL;
  666. td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
  667. ohci->hcca->done_head = 0;
  668. while (td_list_hc) {
  669. td_list = (td_t *)td_list_hc;
  670. if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
  671. lurb_priv = &urb_priv;
  672. dbg(" USB-error/status: %x : %p",
  673. TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
  674. if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
  675. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  676. td_list->ed->hwHeadP =
  677. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
  678. (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
  679. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  680. } else
  681. td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
  682. }
  683. td_list->hwNextTD = 0;
  684. }
  685. td_list->next_dl_td = td_rev;
  686. td_rev = td_list;
  687. td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
  688. }
  689. return td_list;
  690. }
  691. /*-------------------------------------------------------------------------*/
  692. /* td done list */
  693. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  694. {
  695. td_t *td_list_next = NULL;
  696. ed_t *ed;
  697. int cc = 0;
  698. int stat = 0;
  699. /* urb_t *urb; */
  700. urb_priv_t *lurb_priv;
  701. __u32 tdINFO, edHeadP, edTailP;
  702. while (td_list) {
  703. td_list_next = td_list->next_dl_td;
  704. lurb_priv = &urb_priv;
  705. tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
  706. ed = td_list->ed;
  707. dl_transfer_length(td_list);
  708. /* error code of transfer */
  709. cc = TD_CC_GET (tdINFO);
  710. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  711. if ((ed->state & (ED_OPER | ED_UNLINK))
  712. && (lurb_priv->state != URB_DEL)) {
  713. dbg("ConditionCode %#x", cc);
  714. stat = cc_to_error[cc];
  715. urb_finished = 1;
  716. }
  717. }
  718. if (ed->state != ED_NEW) {
  719. edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
  720. edTailP = ohci_cpu_to_le32 (ed->hwTailP);
  721. /* unlink eds if they are not busy */
  722. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  723. ep_unlink (ohci, ed);
  724. }
  725. td_list = td_list_next;
  726. }
  727. return stat;
  728. }
  729. /*-------------------------------------------------------------------------*
  730. * Virtual Root Hub
  731. *-------------------------------------------------------------------------*/
  732. /* Device descriptor */
  733. static __u8 root_hub_dev_des[] =
  734. {
  735. 0x12, /* __u8 bLength; */
  736. 0x01, /* __u8 bDescriptorType; Device */
  737. 0x10, /* __u16 bcdUSB; v1.1 */
  738. 0x01,
  739. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  740. 0x00, /* __u8 bDeviceSubClass; */
  741. 0x00, /* __u8 bDeviceProtocol; */
  742. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  743. 0x00, /* __u16 idVendor; */
  744. 0x00,
  745. 0x00, /* __u16 idProduct; */
  746. 0x00,
  747. 0x00, /* __u16 bcdDevice; */
  748. 0x00,
  749. 0x00, /* __u8 iManufacturer; */
  750. 0x01, /* __u8 iProduct; */
  751. 0x00, /* __u8 iSerialNumber; */
  752. 0x01 /* __u8 bNumConfigurations; */
  753. };
  754. /* Configuration descriptor */
  755. static __u8 root_hub_config_des[] =
  756. {
  757. 0x09, /* __u8 bLength; */
  758. 0x02, /* __u8 bDescriptorType; Configuration */
  759. 0x19, /* __u16 wTotalLength; */
  760. 0x00,
  761. 0x01, /* __u8 bNumInterfaces; */
  762. 0x01, /* __u8 bConfigurationValue; */
  763. 0x00, /* __u8 iConfiguration; */
  764. 0x40, /* __u8 bmAttributes;
  765. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  766. 0x00, /* __u8 MaxPower; */
  767. /* interface */
  768. 0x09, /* __u8 if_bLength; */
  769. 0x04, /* __u8 if_bDescriptorType; Interface */
  770. 0x00, /* __u8 if_bInterfaceNumber; */
  771. 0x00, /* __u8 if_bAlternateSetting; */
  772. 0x01, /* __u8 if_bNumEndpoints; */
  773. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  774. 0x00, /* __u8 if_bInterfaceSubClass; */
  775. 0x00, /* __u8 if_bInterfaceProtocol; */
  776. 0x00, /* __u8 if_iInterface; */
  777. /* endpoint */
  778. 0x07, /* __u8 ep_bLength; */
  779. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  780. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  781. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  782. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  783. 0x00,
  784. 0xff /* __u8 ep_bInterval; 255 ms */
  785. };
  786. static unsigned char root_hub_str_index0[] =
  787. {
  788. 0x04, /* __u8 bLength; */
  789. 0x03, /* __u8 bDescriptorType; String-descriptor */
  790. 0x09, /* __u8 lang ID */
  791. 0x04, /* __u8 lang ID */
  792. };
  793. static unsigned char root_hub_str_index1[] =
  794. {
  795. 28, /* __u8 bLength; */
  796. 0x03, /* __u8 bDescriptorType; String-descriptor */
  797. 'O', /* __u8 Unicode */
  798. 0, /* __u8 Unicode */
  799. 'H', /* __u8 Unicode */
  800. 0, /* __u8 Unicode */
  801. 'C', /* __u8 Unicode */
  802. 0, /* __u8 Unicode */
  803. 'I', /* __u8 Unicode */
  804. 0, /* __u8 Unicode */
  805. ' ', /* __u8 Unicode */
  806. 0, /* __u8 Unicode */
  807. 'R', /* __u8 Unicode */
  808. 0, /* __u8 Unicode */
  809. 'o', /* __u8 Unicode */
  810. 0, /* __u8 Unicode */
  811. 'o', /* __u8 Unicode */
  812. 0, /* __u8 Unicode */
  813. 't', /* __u8 Unicode */
  814. 0, /* __u8 Unicode */
  815. ' ', /* __u8 Unicode */
  816. 0, /* __u8 Unicode */
  817. 'H', /* __u8 Unicode */
  818. 0, /* __u8 Unicode */
  819. 'u', /* __u8 Unicode */
  820. 0, /* __u8 Unicode */
  821. 'b', /* __u8 Unicode */
  822. 0, /* __u8 Unicode */
  823. };
  824. /* Hub class-specific descriptor is constructed dynamically */
  825. /*-------------------------------------------------------------------------*/
  826. #define OK(x) len = (x); break
  827. #ifdef DEBUG
  828. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  829. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  830. #else
  831. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  832. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  833. #endif
  834. #define RD_RH_STAT roothub_status(&gohci)
  835. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  836. /* request to virtual root hub */
  837. int rh_check_port_status(ohci_t *controller)
  838. {
  839. __u32 temp, ndp, i;
  840. int res;
  841. res = -1;
  842. temp = roothub_a (controller);
  843. ndp = (temp & RH_A_NDP);
  844. for (i = 0; i < ndp; i++) {
  845. temp = roothub_portstatus (controller, i);
  846. /* check for a device disconnect */
  847. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  848. (RH_PS_PESC | RH_PS_CSC)) &&
  849. ((temp & RH_PS_CCS) == 0)) {
  850. res = i;
  851. break;
  852. }
  853. }
  854. return res;
  855. }
  856. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  857. void *buffer, int transfer_len, struct devrequest *cmd)
  858. {
  859. void * data = buffer;
  860. int leni = transfer_len;
  861. int len = 0;
  862. int stat = 0;
  863. __u32 datab[4];
  864. __u8 *data_buf = (__u8 *)datab;
  865. __u16 bmRType_bReq;
  866. __u16 wValue;
  867. __u16 wIndex;
  868. __u16 wLength;
  869. #ifdef DEBUG
  870. urb_priv.actual_length = 0;
  871. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  872. #endif
  873. if (usb_pipeint(pipe)) {
  874. info("Root-Hub submit IRQ: NOT implemented");
  875. return 0;
  876. }
  877. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  878. wValue = m16_swap (cmd->value);
  879. wIndex = m16_swap (cmd->index);
  880. wLength = m16_swap (cmd->length);
  881. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  882. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  883. switch (bmRType_bReq) {
  884. /* Request Destination:
  885. without flags: Device,
  886. RH_INTERFACE: interface,
  887. RH_ENDPOINT: endpoint,
  888. RH_CLASS means HUB here,
  889. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  890. */
  891. case RH_GET_STATUS:
  892. *(__u16 *) data_buf = m16_swap (1); OK (2);
  893. case RH_GET_STATUS | RH_INTERFACE:
  894. *(__u16 *) data_buf = m16_swap (0); OK (2);
  895. case RH_GET_STATUS | RH_ENDPOINT:
  896. *(__u16 *) data_buf = m16_swap (0); OK (2);
  897. case RH_GET_STATUS | RH_CLASS:
  898. *(__u32 *) data_buf = m32_swap (
  899. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  900. OK (4);
  901. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  902. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  903. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  904. switch (wValue) {
  905. case (RH_ENDPOINT_STALL): OK (0);
  906. }
  907. break;
  908. case RH_CLEAR_FEATURE | RH_CLASS:
  909. switch (wValue) {
  910. case RH_C_HUB_LOCAL_POWER:
  911. OK(0);
  912. case (RH_C_HUB_OVER_CURRENT):
  913. WR_RH_STAT(RH_HS_OCIC); OK (0);
  914. }
  915. break;
  916. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  917. switch (wValue) {
  918. case (RH_PORT_ENABLE):
  919. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  920. case (RH_PORT_SUSPEND):
  921. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  922. case (RH_PORT_POWER):
  923. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  924. case (RH_C_PORT_CONNECTION):
  925. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  926. case (RH_C_PORT_ENABLE):
  927. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  928. case (RH_C_PORT_SUSPEND):
  929. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  930. case (RH_C_PORT_OVER_CURRENT):
  931. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  932. case (RH_C_PORT_RESET):
  933. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  934. }
  935. break;
  936. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  937. switch (wValue) {
  938. case (RH_PORT_SUSPEND):
  939. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  940. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  941. if (RD_RH_PORTSTAT & RH_PS_CCS)
  942. WR_RH_PORTSTAT (RH_PS_PRS);
  943. OK (0);
  944. case (RH_PORT_POWER):
  945. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  946. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  947. if (RD_RH_PORTSTAT & RH_PS_CCS)
  948. WR_RH_PORTSTAT (RH_PS_PES );
  949. OK (0);
  950. }
  951. break;
  952. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  953. case RH_GET_DESCRIPTOR:
  954. switch ((wValue & 0xff00) >> 8) {
  955. case (0x01): /* device descriptor */
  956. len = min_t(unsigned int,
  957. leni,
  958. min_t(unsigned int,
  959. sizeof (root_hub_dev_des),
  960. wLength));
  961. data_buf = root_hub_dev_des; OK(len);
  962. case (0x02): /* configuration descriptor */
  963. len = min_t(unsigned int,
  964. leni,
  965. min_t(unsigned int,
  966. sizeof (root_hub_config_des),
  967. wLength));
  968. data_buf = root_hub_config_des; OK(len);
  969. case (0x03): /* string descriptors */
  970. if(wValue==0x0300) {
  971. len = min_t(unsigned int,
  972. leni,
  973. min_t(unsigned int,
  974. sizeof (root_hub_str_index0),
  975. wLength));
  976. data_buf = root_hub_str_index0;
  977. OK(len);
  978. }
  979. if(wValue==0x0301) {
  980. len = min_t(unsigned int,
  981. leni,
  982. min_t(unsigned int,
  983. sizeof (root_hub_str_index1),
  984. wLength));
  985. data_buf = root_hub_str_index1;
  986. OK(len);
  987. }
  988. default:
  989. stat = USB_ST_STALLED;
  990. }
  991. break;
  992. case RH_GET_DESCRIPTOR | RH_CLASS:
  993. {
  994. __u32 temp = roothub_a (&gohci);
  995. data_buf [0] = 9; /* min length; */
  996. data_buf [1] = 0x29;
  997. data_buf [2] = temp & RH_A_NDP;
  998. data_buf [3] = 0;
  999. if (temp & RH_A_PSM) /* per-port power switching? */
  1000. data_buf [3] |= 0x1;
  1001. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1002. data_buf [3] |= 0x10;
  1003. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1004. data_buf [3] |= 0x8;
  1005. /* corresponds to data_buf[4-7] */
  1006. datab [1] = 0;
  1007. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1008. temp = roothub_b (&gohci);
  1009. data_buf [7] = temp & RH_B_DR;
  1010. if (data_buf [2] < 7) {
  1011. data_buf [8] = 0xff;
  1012. } else {
  1013. data_buf [0] += 2;
  1014. data_buf [8] = (temp & RH_B_DR) >> 8;
  1015. data_buf [10] = data_buf [9] = 0xff;
  1016. }
  1017. len = min_t(unsigned int, leni,
  1018. min_t(unsigned int, data_buf [0], wLength));
  1019. OK (len);
  1020. }
  1021. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1022. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1023. default:
  1024. dbg ("unsupported root hub command");
  1025. stat = USB_ST_STALLED;
  1026. }
  1027. #ifdef DEBUG
  1028. ohci_dump_roothub (&gohci, 1);
  1029. #endif
  1030. len = min_t(int, len, leni);
  1031. if (data != data_buf)
  1032. memcpy (data, data_buf, len);
  1033. dev->act_len = len;
  1034. dev->status = stat;
  1035. #ifdef DEBUG
  1036. if (transfer_len)
  1037. urb_priv.actual_length = transfer_len;
  1038. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1039. #endif
  1040. return stat;
  1041. }
  1042. /*-------------------------------------------------------------------------*/
  1043. /* common code for handling submit messages - used for all but root hub */
  1044. /* accesses. */
  1045. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1046. int transfer_len, struct devrequest *setup, int interval)
  1047. {
  1048. int stat = 0;
  1049. int maxsize = usb_maxpacket(dev, pipe);
  1050. int timeout;
  1051. /* device pulled? Shortcut the action. */
  1052. if (devgone == dev) {
  1053. dev->status = USB_ST_CRC_ERR;
  1054. return 0;
  1055. }
  1056. #ifdef DEBUG
  1057. urb_priv.actual_length = 0;
  1058. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1059. #endif
  1060. if (!maxsize) {
  1061. err("submit_common_message: pipesize for pipe %lx is zero",
  1062. pipe);
  1063. return -1;
  1064. }
  1065. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1066. err("sohci_submit_job failed");
  1067. return -1;
  1068. }
  1069. /* allow more time for a BULK device to react - some are slow */
  1070. #define BULK_TO 5000 /* timeout in milliseconds */
  1071. if (usb_pipebulk(pipe))
  1072. timeout = BULK_TO;
  1073. else
  1074. timeout = 100;
  1075. /* wait for it to complete */
  1076. for (;;) {
  1077. /* check whether the controller is done */
  1078. stat = hc_interrupt();
  1079. if (stat < 0) {
  1080. stat = USB_ST_CRC_ERR;
  1081. break;
  1082. }
  1083. /* NOTE: since we are not interrupt driven in U-Boot and always
  1084. * handle only one URB at a time, we cannot assume the
  1085. * transaction finished on the first successful return from
  1086. * hc_interrupt().. unless the flag for current URB is set,
  1087. * meaning that all TD's to/from device got actually
  1088. * transferred and processed. If the current URB is not
  1089. * finished we need to re-iterate this loop so as
  1090. * hc_interrupt() gets called again as there needs to be some
  1091. * more TD's to process still */
  1092. if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
  1093. /* 0xff is returned for an SF-interrupt */
  1094. break;
  1095. }
  1096. if (--timeout) {
  1097. wait_ms(1);
  1098. if (!urb_finished)
  1099. dbg("\%");
  1100. } else {
  1101. err("CTL:TIMEOUT ");
  1102. dbg("submit_common_msg: TO status %x\n", stat);
  1103. stat = USB_ST_CRC_ERR;
  1104. urb_finished = 1;
  1105. break;
  1106. }
  1107. }
  1108. #if 0
  1109. /* we got an Root Hub Status Change interrupt */
  1110. if (got_rhsc) {
  1111. #ifdef DEBUG
  1112. ohci_dump_roothub (&gohci, 1);
  1113. #endif
  1114. got_rhsc = 0;
  1115. /* abuse timeout */
  1116. timeout = rh_check_port_status(&gohci);
  1117. if (timeout >= 0) {
  1118. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1119. /* the called routine adds 1 to the passed value */
  1120. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1121. #endif
  1122. /*
  1123. * XXX
  1124. * This is potentially dangerous because it assumes
  1125. * that only one device is ever plugged in!
  1126. */
  1127. devgone = dev;
  1128. }
  1129. }
  1130. #endif
  1131. dev->status = stat;
  1132. dev->act_len = transfer_len;
  1133. #ifdef DEBUG
  1134. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1135. #endif
  1136. /* free TDs in urb_priv */
  1137. urb_free_priv (&urb_priv);
  1138. return 0;
  1139. }
  1140. /* submit routines called from usb.c */
  1141. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1142. int transfer_len)
  1143. {
  1144. info("submit_bulk_msg");
  1145. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1146. }
  1147. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1148. int transfer_len, struct devrequest *setup)
  1149. {
  1150. int maxsize = usb_maxpacket(dev, pipe);
  1151. info("submit_control_msg");
  1152. #ifdef DEBUG
  1153. urb_priv.actual_length = 0;
  1154. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1155. #endif
  1156. if (!maxsize) {
  1157. err("submit_control_message: pipesize for pipe %lx is zero",
  1158. pipe);
  1159. return -1;
  1160. }
  1161. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1162. gohci.rh.dev = dev;
  1163. /* root hub - redirect */
  1164. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1165. setup);
  1166. }
  1167. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1168. }
  1169. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1170. int transfer_len, int interval)
  1171. {
  1172. info("submit_int_msg");
  1173. return -1;
  1174. }
  1175. /*-------------------------------------------------------------------------*
  1176. * HC functions
  1177. *-------------------------------------------------------------------------*/
  1178. /* reset the HC and BUS */
  1179. static int hc_reset (ohci_t *ohci)
  1180. {
  1181. int timeout = 30;
  1182. int smm_timeout = 50; /* 0,5 sec */
  1183. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1184. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1185. info("USB HC TakeOver from SMM");
  1186. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1187. wait_ms (10);
  1188. if (--smm_timeout == 0) {
  1189. err("USB HC TakeOver failed!");
  1190. return -1;
  1191. }
  1192. }
  1193. }
  1194. /* Disable HC interrupts */
  1195. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1196. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1197. ohci->slot_name,
  1198. readl (&ohci->regs->control));
  1199. /* Reset USB (needed by some controllers) */
  1200. ohci->hc_control = 0;
  1201. writel (ohci->hc_control, &ohci->regs->control);
  1202. /* HC Reset requires max 10 us delay */
  1203. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1204. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1205. if (--timeout == 0) {
  1206. err("USB HC reset timed out!");
  1207. return -1;
  1208. }
  1209. udelay (1);
  1210. }
  1211. return 0;
  1212. }
  1213. /*-------------------------------------------------------------------------*/
  1214. /* Start an OHCI controller, set the BUS operational
  1215. * enable interrupts
  1216. * connect the virtual root hub */
  1217. static int hc_start (ohci_t * ohci)
  1218. {
  1219. __u32 mask;
  1220. unsigned int fminterval;
  1221. ohci->disabled = 1;
  1222. /* Tell the controller where the control and bulk lists are
  1223. * The lists are empty now. */
  1224. writel (0, &ohci->regs->ed_controlhead);
  1225. writel (0, &ohci->regs->ed_bulkhead);
  1226. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1227. fminterval = 0x2edf;
  1228. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1229. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1230. writel (fminterval, &ohci->regs->fminterval);
  1231. writel (0x628, &ohci->regs->lsthresh);
  1232. /* start controller operations */
  1233. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1234. ohci->disabled = 0;
  1235. writel (ohci->hc_control, &ohci->regs->control);
  1236. /* disable all interrupts */
  1237. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1238. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1239. OHCI_INTR_OC | OHCI_INTR_MIE);
  1240. writel (mask, &ohci->regs->intrdisable);
  1241. /* clear all interrupts */
  1242. mask &= ~OHCI_INTR_MIE;
  1243. writel (mask, &ohci->regs->intrstatus);
  1244. /* Choose the interrupts we care about now - but w/o MIE */
  1245. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1246. writel (mask, &ohci->regs->intrenable);
  1247. #ifdef OHCI_USE_NPS
  1248. /* required for AMD-756 and some Mac platforms */
  1249. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1250. &ohci->regs->roothub.a);
  1251. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1252. #endif /* OHCI_USE_NPS */
  1253. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1254. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1255. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1256. /* connect the virtual root hub */
  1257. ohci->rh.devnum = 0;
  1258. return 0;
  1259. }
  1260. /*-------------------------------------------------------------------------*/
  1261. /* an interrupt happens */
  1262. static int
  1263. hc_interrupt (void)
  1264. {
  1265. ohci_t *ohci = &gohci;
  1266. struct ohci_regs *regs = ohci->regs;
  1267. int ints;
  1268. int stat = -1;
  1269. if ((ohci->hcca->done_head != 0) &&
  1270. !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
  1271. ints = OHCI_INTR_WDH;
  1272. } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
  1273. ohci->disabled++;
  1274. err ("%s device removed!", ohci->slot_name);
  1275. return -1;
  1276. } else if ((ints &= readl (&regs->intrenable)) == 0) {
  1277. dbg("hc_interrupt: returning..\n");
  1278. return 0xff;
  1279. }
  1280. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1281. if (ints & OHCI_INTR_RHSC) {
  1282. got_rhsc = 1;
  1283. stat = 0xff;
  1284. }
  1285. if (ints & OHCI_INTR_UE) {
  1286. ohci->disabled++;
  1287. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1288. ohci->slot_name);
  1289. /* e.g. due to PCI Master/Target Abort */
  1290. #ifdef DEBUG
  1291. ohci_dump (ohci, 1);
  1292. #endif
  1293. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1294. /* Make some non-interrupt context restart the controller. */
  1295. /* Count and limit the retries though; either hardware or */
  1296. /* software errors can go forever... */
  1297. hc_reset (ohci);
  1298. return -1;
  1299. }
  1300. if (ints & OHCI_INTR_WDH) {
  1301. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1302. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1303. writel (OHCI_INTR_WDH, &regs->intrenable);
  1304. }
  1305. if (ints & OHCI_INTR_SO) {
  1306. dbg("USB Schedule overrun\n");
  1307. writel (OHCI_INTR_SO, &regs->intrenable);
  1308. stat = -1;
  1309. }
  1310. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1311. if (ints & OHCI_INTR_SF) {
  1312. unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
  1313. wait_ms(1);
  1314. writel (OHCI_INTR_SF, &regs->intrdisable);
  1315. if (ohci->ed_rm_list[frame] != NULL)
  1316. writel (OHCI_INTR_SF, &regs->intrenable);
  1317. stat = 0xff;
  1318. }
  1319. writel (ints, &regs->intrstatus);
  1320. return stat;
  1321. }
  1322. /*-------------------------------------------------------------------------*/
  1323. /*-------------------------------------------------------------------------*/
  1324. /* De-allocate all resources.. */
  1325. static void hc_release_ohci (ohci_t *ohci)
  1326. {
  1327. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1328. if (!ohci->disabled)
  1329. hc_reset (ohci);
  1330. }
  1331. /*-------------------------------------------------------------------------*/
  1332. /*
  1333. * low level initalisation routine, called from usb.c
  1334. */
  1335. static char ohci_inited = 0;
  1336. int usb_lowlevel_init(void)
  1337. {
  1338. /* Set the USB Clock */
  1339. *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
  1340. #ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
  1341. /* remove all PSC3 USB bits first before ORing in ours */
  1342. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
  1343. #else
  1344. /* remove all USB bits first before ORing in ours */
  1345. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
  1346. #endif
  1347. /* Activate USB port */
  1348. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
  1349. memset (&gohci, 0, sizeof (ohci_t));
  1350. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1351. /* align the storage */
  1352. if ((__u32)&ghcca[0] & 0xff) {
  1353. err("HCCA not aligned!!");
  1354. return -1;
  1355. }
  1356. phcca = &ghcca[0];
  1357. info("aligned ghcca %p", phcca);
  1358. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1359. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1360. err("EDs not aligned!!");
  1361. return -1;
  1362. }
  1363. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1364. if ((__u32)gtd & 0x7) {
  1365. err("TDs not aligned!!");
  1366. return -1;
  1367. }
  1368. ptd = gtd;
  1369. gohci.hcca = phcca;
  1370. memset (phcca, 0, sizeof (struct ohci_hcca));
  1371. gohci.disabled = 1;
  1372. gohci.sleeping = 0;
  1373. gohci.irq = -1;
  1374. gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
  1375. gohci.flags = 0;
  1376. gohci.slot_name = "mpc5200";
  1377. if (hc_reset (&gohci) < 0) {
  1378. hc_release_ohci (&gohci);
  1379. return -1;
  1380. }
  1381. if (hc_start (&gohci) < 0) {
  1382. err ("can't start usb-%s", gohci.slot_name);
  1383. hc_release_ohci (&gohci);
  1384. return -1;
  1385. }
  1386. #ifdef DEBUG
  1387. ohci_dump (&gohci, 1);
  1388. #endif
  1389. ohci_inited = 1;
  1390. urb_finished = 1;
  1391. return 0;
  1392. }
  1393. int usb_lowlevel_stop(void)
  1394. {
  1395. /* this gets called really early - before the controller has */
  1396. /* even been initialized! */
  1397. if (!ohci_inited)
  1398. return 0;
  1399. /* TODO release any interrupts, etc. */
  1400. /* call hc_release_ohci() here ? */
  1401. hc_reset (&gohci);
  1402. return 0;
  1403. }
  1404. #endif /* CONFIG_USB_OHCI */