cpu_init.c 7.1 KB

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  1. /*
  2. * (C) Copyright 2000-2010
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc5xxx.h>
  25. #include <asm/io.h>
  26. #include <watchdog.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * Breath some life into the CPU...
  30. *
  31. * Set up the memory map,
  32. * initialize a bunch of registers.
  33. */
  34. void cpu_init_f (void)
  35. {
  36. volatile struct mpc5xxx_mmap_ctl *mm =
  37. (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
  38. volatile struct mpc5xxx_lpb *lpb =
  39. (struct mpc5xxx_lpb *) MPC5XXX_LPB;
  40. volatile struct mpc5xxx_gpio *gpio =
  41. (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
  42. volatile struct mpc5xxx_xlb *xlb =
  43. (struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
  44. #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
  45. volatile struct mpc5xxx_cdm *cdm =
  46. (struct mpc5xxx_cdm *) MPC5XXX_CDM;
  47. #endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
  48. #if defined(CONFIG_WATCHDOG)
  49. volatile struct mpc5xxx_gpt *gpt0 =
  50. (struct mpc5xxx_gpt *) MPC5XXX_GPT;
  51. #endif /* CONFIG_WATCHDOG */
  52. unsigned long addecr = (1 << 25); /* Boot_CS */
  53. /* Pointer is writable since we allocated a register for it */
  54. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  55. /* Clear initial global data */
  56. memset ((void *) gd, 0, sizeof (gd_t));
  57. /*
  58. * Memory Controller: configure chip selects and enable them
  59. */
  60. #if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
  61. out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
  62. out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
  63. CONFIG_SYS_BOOTCS_SIZE));
  64. #endif
  65. #if defined(CONFIG_SYS_BOOTCS_CFG)
  66. out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
  67. #endif
  68. #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
  69. out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
  70. out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
  71. CONFIG_SYS_CS0_SIZE));
  72. /* CS0 and BOOT_CS cannot be enabled at once. */
  73. /* addecr |= (1 << 16); */
  74. #endif
  75. #if defined(CONFIG_SYS_CS0_CFG)
  76. out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
  77. #endif
  78. #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
  79. out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
  80. out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
  81. CONFIG_SYS_CS1_SIZE));
  82. addecr |= (1 << 17);
  83. #endif
  84. #if defined(CONFIG_SYS_CS1_CFG)
  85. out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
  86. #endif
  87. #if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
  88. out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
  89. out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
  90. CONFIG_SYS_CS2_SIZE));
  91. addecr |= (1 << 18);
  92. #endif
  93. #if defined(CONFIG_SYS_CS2_CFG)
  94. out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
  95. #endif
  96. #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
  97. out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
  98. out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
  99. CONFIG_SYS_CS3_SIZE));
  100. addecr |= (1 << 19);
  101. #endif
  102. #if defined(CONFIG_SYS_CS3_CFG)
  103. out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
  104. #endif
  105. #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
  106. out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
  107. out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
  108. CONFIG_SYS_CS4_SIZE));
  109. addecr |= (1 << 20);
  110. #endif
  111. #if defined(CONFIG_SYS_CS4_CFG)
  112. out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
  113. #endif
  114. #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
  115. out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
  116. out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
  117. CONFIG_SYS_CS5_SIZE));
  118. addecr |= (1 << 21);
  119. #endif
  120. #if defined(CONFIG_SYS_CS5_CFG)
  121. out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
  122. #endif
  123. addecr |= 1;
  124. #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
  125. out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
  126. out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
  127. CONFIG_SYS_CS6_SIZE));
  128. addecr |= (1 << 26);
  129. #endif
  130. #if defined(CONFIG_SYS_CS6_CFG)
  131. out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
  132. #endif
  133. #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
  134. out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
  135. out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
  136. CONFIG_SYS_CS7_SIZE));
  137. addecr |= (1 << 27);
  138. #endif
  139. #if defined(CONFIG_SYS_CS7_CFG)
  140. out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
  141. #endif
  142. #if defined(CONFIG_SYS_CS_BURST)
  143. out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
  144. #endif
  145. #if defined(CONFIG_SYS_CS_DEADCYCLE)
  146. out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
  147. #endif
  148. /* Enable chip selects */
  149. out_be32(&mm->ipbi_ws_ctrl, addecr);
  150. out_be32(&lpb->cs_ctrl, (1 << 24));
  151. /* Setup pin multiplexing */
  152. #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
  153. out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
  154. #endif
  155. /* enable timebase */
  156. setbits_be32(&xlb->config, (1 << 13));
  157. /* Enable snooping for RAM */
  158. setbits_be32(&xlb->config, (1 << 15));
  159. out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
  160. #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
  161. /* Motorola reports IPB should better run at 133 MHz. */
  162. setbits_be32(&mm->ipbi_ws_ctrl, 1);
  163. /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
  164. addecr = in_be32(&cdm->cfg);
  165. addecr &= ~0x103;
  166. # if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
  167. /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
  168. addecr |= 0x01;
  169. # else
  170. /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
  171. addecr |= 0x02;
  172. # endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
  173. out_be32(&cdm->cfg, addecr);
  174. #endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
  175. /* Configure the XLB Arbiter */
  176. out_be32(&xlb->master_pri_enable, 0xff);
  177. out_be32(&xlb->master_priority, 0x11111111);
  178. #if defined(CONFIG_SYS_XLB_PIPELINING)
  179. /* Enable piplining */
  180. clrbits_be32(&xlb->config, (1 << 31));
  181. #endif
  182. #if defined(CONFIG_WATCHDOG)
  183. /* Charge the watchdog timer - prescaler = 64k, count = 64k*/
  184. out_be32(&gpt0->cir, 0x0000ffff);
  185. out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */
  186. reset_5xxx_watchdog();
  187. #endif /* CONFIG_WATCHDOG */
  188. }
  189. /*
  190. * initialize higher level parts of CPU like time base and timers
  191. */
  192. int cpu_init_r (void)
  193. {
  194. volatile struct mpc5xxx_intr *intr =
  195. (struct mpc5xxx_intr *) MPC5XXX_ICTL;
  196. /* mask all interrupts */
  197. out_be32(&intr->per_mask, 0xffffff00);
  198. setbits_be32(&intr->main_mask, 0x0001ffff);
  199. clrbits_be32(&intr->ctrl, 0x00000f00);
  200. /* route critical ints to normal ints */
  201. setbits_be32(&intr->ctrl, 0x00000001);
  202. #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
  203. /* load FEC microcode */
  204. loadtask(0, 2);
  205. #endif
  206. return (0);
  207. }