serial.c 4.9 KB

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  1. /*
  2. * (C) Copyright 2000 - 2010
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * Based ont the MPC5200 PSC driver.
  24. * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
  25. */
  26. /*
  27. * Minimal serial functions needed to use one of the PSC ports
  28. * as serial console interface.
  29. */
  30. #include <common.h>
  31. #include <asm/io.h>
  32. #include <asm/processor.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #if defined(CONFIG_PSC_CONSOLE)
  35. static void fifo_init (volatile psc512x_t *psc)
  36. {
  37. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  38. /* reset Rx & Tx fifo slice */
  39. out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
  40. out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
  41. /* disable Tx & Rx FIFO interrupts */
  42. out_be32(&psc->rfintmask, 0);
  43. out_be32(&psc->tfintmask, 0);
  44. out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
  45. out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
  46. /* enable Tx & Rx FIFO slice */
  47. out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
  48. out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
  49. out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
  50. __asm__ volatile ("sync");
  51. }
  52. void serial_setbrg(void)
  53. {
  54. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  55. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  56. unsigned long baseclk, div;
  57. /* calculate dividor for setting PSC CTUR and CTLR registers */
  58. baseclk = (gd->ips_clk + 8) / 16;
  59. div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
  60. out_8(&psc->ctur, (div >> 8) & 0xff);
  61. out_8(&psc->ctlr, div & 0xff); /* set baudrate */
  62. }
  63. int serial_init(void)
  64. {
  65. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  66. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  67. fifo_init (psc);
  68. /* set MR register to point to MR1 */
  69. out_8(&psc->command, PSC_SEL_MODE_REG_1);
  70. /* disable Tx/Rx */
  71. out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
  72. /* choose the prescaler by 16 for the Tx/Rx clock generation */
  73. out_be16(&psc->psc_clock_select, 0xdd00);
  74. /* switch to UART mode */
  75. out_be32(&psc->sicr, 0);
  76. /* mode register points to mr1 */
  77. /* configure parity, bit length and so on in mode register 1*/
  78. out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
  79. /* now, mode register points to mr2 */
  80. out_8(&psc->mode, PSC_MODE_1_STOPBIT);
  81. /* set baudrate */
  82. serial_setbrg();
  83. /* disable all interrupts */
  84. out_be16(&psc->psc_imr, 0);
  85. /* reset and enable Rx/Tx */
  86. out_8(&psc->command, PSC_RST_RX);
  87. out_8(&psc->command, PSC_RST_TX);
  88. out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
  89. return 0;
  90. }
  91. void serial_putc (const char c)
  92. {
  93. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  94. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  95. if (c == '\n')
  96. serial_putc ('\r');
  97. /* Wait for last character to go. */
  98. while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
  99. ;
  100. out_8(&psc->tfdata_8, c);
  101. }
  102. void serial_putc_raw (const char c)
  103. {
  104. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  105. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  106. /* Wait for last character to go. */
  107. while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
  108. ;
  109. out_8(&psc->tfdata_8, c);
  110. }
  111. void serial_puts (const char *s)
  112. {
  113. while (*s) {
  114. serial_putc (*s++);
  115. }
  116. }
  117. int serial_getc (void)
  118. {
  119. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  120. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  121. /* Wait for a character to arrive. */
  122. while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
  123. ;
  124. return in_8(&psc->rfdata_8);
  125. }
  126. int serial_tstc (void)
  127. {
  128. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  129. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  130. return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
  131. }
  132. void serial_setrts(int s)
  133. {
  134. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  135. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  136. if (s) {
  137. /* Assert RTS (become LOW) */
  138. out_8(&psc->op1, 0x1);
  139. }
  140. else {
  141. /* Negate RTS (become HIGH) */
  142. out_8(&psc->op0, 0x1);
  143. }
  144. }
  145. int serial_getcts(void)
  146. {
  147. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  148. volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
  149. return (in_8(&psc->ip) & 0x1) ? 0 : 1;
  150. }
  151. #endif /* CONFIG_PSC_CONSOLE */