fixed_sdram.c 5.5 KB

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  1. /*
  2. * (C) Copyright 2007-2009 DENX Software Engineering
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <common.h>
  24. #include <asm/io.h>
  25. #include <asm/mpc512x.h>
  26. /*
  27. * MDDRC Config Runtime Settings
  28. */
  29. ddr512x_config_t default_mddrc_config = {
  30. .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG,
  31. .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
  32. .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
  33. .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
  34. };
  35. u32 default_init_seq[] = {
  36. CONFIG_SYS_DDRCMD_NOP,
  37. CONFIG_SYS_DDRCMD_NOP,
  38. CONFIG_SYS_DDRCMD_NOP,
  39. CONFIG_SYS_DDRCMD_NOP,
  40. CONFIG_SYS_DDRCMD_NOP,
  41. CONFIG_SYS_DDRCMD_NOP,
  42. CONFIG_SYS_DDRCMD_NOP,
  43. CONFIG_SYS_DDRCMD_NOP,
  44. CONFIG_SYS_DDRCMD_NOP,
  45. CONFIG_SYS_DDRCMD_NOP,
  46. CONFIG_SYS_DDRCMD_PCHG_ALL,
  47. CONFIG_SYS_DDRCMD_NOP,
  48. CONFIG_SYS_DDRCMD_RFSH,
  49. CONFIG_SYS_DDRCMD_NOP,
  50. CONFIG_SYS_DDRCMD_RFSH,
  51. CONFIG_SYS_DDRCMD_NOP,
  52. CONFIG_SYS_MICRON_INIT_DEV_OP,
  53. CONFIG_SYS_DDRCMD_NOP,
  54. CONFIG_SYS_DDRCMD_EM2,
  55. CONFIG_SYS_DDRCMD_NOP,
  56. CONFIG_SYS_DDRCMD_PCHG_ALL,
  57. CONFIG_SYS_DDRCMD_EM2,
  58. CONFIG_SYS_DDRCMD_EM3,
  59. CONFIG_SYS_DDRCMD_EN_DLL,
  60. CONFIG_SYS_MICRON_INIT_DEV_OP,
  61. CONFIG_SYS_DDRCMD_PCHG_ALL,
  62. CONFIG_SYS_DDRCMD_RFSH,
  63. CONFIG_SYS_MICRON_INIT_DEV_OP,
  64. CONFIG_SYS_DDRCMD_OCD_DEFAULT,
  65. CONFIG_SYS_DDRCMD_PCHG_ALL,
  66. CONFIG_SYS_DDRCMD_NOP
  67. };
  68. /*
  69. * fixed sdram init:
  70. * The board doesn't use memory modules that have serial presence
  71. * detect or similar mechanism for discovery of the DRAM settings
  72. */
  73. long int fixed_sdram(ddr512x_config_t *mddrc_config,
  74. u32 *dram_init_seq, int seq_sz)
  75. {
  76. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  77. u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  78. u32 msize_log2 = __ilog2(msize);
  79. u32 i;
  80. /* take default settings and init sequence if necessary */
  81. if (mddrc_config == NULL)
  82. mddrc_config = &default_mddrc_config;
  83. if (dram_init_seq == NULL) {
  84. dram_init_seq = default_init_seq;
  85. seq_sz = sizeof(default_init_seq)/sizeof(u32);
  86. }
  87. /* Initialize IO Control */
  88. out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
  89. /* Initialize DDR Local Window */
  90. out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
  91. out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
  92. sync_law(&im->sysconf.ddrlaw.ar);
  93. /* DDR Enable */
  94. out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
  95. /* Initialize DDR Priority Manager */
  96. out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
  97. out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
  98. out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
  99. out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
  100. out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
  101. out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
  102. out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
  103. out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
  104. out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
  105. out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
  106. out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
  107. out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
  108. out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
  109. out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
  110. out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
  111. out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
  112. out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
  113. out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
  114. out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
  115. out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
  116. out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
  117. out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
  118. out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
  119. /*
  120. * Initialize MDDRC
  121. * put MDDRC in CMD mode and
  122. * set the max time between refreshes to 0 during init process
  123. */
  124. out_be32(&im->mddrc.ddr_sys_config,
  125. mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
  126. out_be32(&im->mddrc.ddr_time_config0,
  127. mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
  128. out_be32(&im->mddrc.ddr_time_config1,
  129. mddrc_config->ddr_time_config1);
  130. out_be32(&im->mddrc.ddr_time_config2,
  131. mddrc_config->ddr_time_config2);
  132. /* Initialize DDR with either default or supplied init sequence */
  133. for (i = 0; i < seq_sz; i++)
  134. out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
  135. /* Start MDDRC */
  136. out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
  137. out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
  138. return msize;
  139. }