cpu.c 4.8 KB

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  1. /*
  2. * (C) Copyright 2007-2010 DENX Software Engineering
  3. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * CPU specific code for the MPC512x family.
  25. *
  26. * Derived from the MPC83xx code.
  27. */
  28. #include <common.h>
  29. #include <command.h>
  30. #include <net.h>
  31. #include <netdev.h>
  32. #include <asm/processor.h>
  33. #include <asm/io.h>
  34. #if defined(CONFIG_OF_LIBFDT)
  35. #include <fdt_support.h>
  36. #endif
  37. DECLARE_GLOBAL_DATA_PTR;
  38. int checkcpu (void)
  39. {
  40. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  41. ulong clock = gd->cpu_clk;
  42. u32 pvr = get_pvr ();
  43. u32 spridr = in_be32(&immr->sysconf.spridr);
  44. char buf1[32], buf2[32];
  45. puts ("CPU: ");
  46. switch (spridr & 0xffff0000) {
  47. case SPR_5121E:
  48. puts ("MPC5121e ");
  49. break;
  50. default:
  51. printf ("Unknown part ID %08x ", spridr & 0xffff0000);
  52. }
  53. printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
  54. switch (pvr & 0xffff0000) {
  55. case PVR_E300C4:
  56. puts ("e300c4 ");
  57. break;
  58. default:
  59. puts ("unknown ");
  60. }
  61. printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
  62. strmhz(buf1, clock),
  63. strmhz(buf2, gd->csb_clk),
  64. gd->reset_status & 0xffff);
  65. return 0;
  66. }
  67. int
  68. do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  69. {
  70. ulong msr;
  71. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  72. /* Interrupts and MMU off */
  73. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  74. msr &= ~( MSR_EE | MSR_IR | MSR_DR);
  75. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  76. /*
  77. * Enable Reset Control Reg - "RSTE" is the magic word that let us go
  78. */
  79. out_be32(&immap->reset.rpr, 0x52535445);
  80. /* Verify Reset Control Reg is enabled */
  81. while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
  82. ;
  83. printf ("Resetting the board.\n");
  84. udelay(200);
  85. /* Perform reset */
  86. out_be32(&immap->reset.rcr, RCR_SWHR);
  87. /* Unreached... */
  88. return 1;
  89. }
  90. /*
  91. * Get timebase clock frequency (like cpu_clk in Hz)
  92. */
  93. unsigned long get_tbclk (void)
  94. {
  95. ulong tbclk;
  96. tbclk = (gd->bus_clk + 3L) / 4L;
  97. return tbclk;
  98. }
  99. #if defined(CONFIG_WATCHDOG)
  100. void watchdog_reset (void)
  101. {
  102. int re_enable = disable_interrupts ();
  103. /* Reset watchdog */
  104. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  105. out_be32(&immr->wdt.swsrr, 0x556c);
  106. out_be32(&immr->wdt.swsrr, 0xaa39);
  107. if (re_enable)
  108. enable_interrupts ();
  109. }
  110. #endif
  111. #ifdef CONFIG_OF_LIBFDT
  112. #ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
  113. /*
  114. * fdt setup for old device trees
  115. * fix up
  116. * cpu clocks
  117. * soc clocks
  118. * ethernet addresses
  119. */
  120. static void old_ft_cpu_setup(void *blob, bd_t *bd)
  121. {
  122. /*
  123. * avoid fixing up by path because that
  124. * produces scary error messages
  125. */
  126. uchar enetaddr[6];
  127. /*
  128. * old device trees have ethernet nodes with
  129. * device_type = "network"
  130. */
  131. eth_getenv_enetaddr("ethaddr", enetaddr);
  132. do_fixup_by_prop(blob, "device_type", "network", 8,
  133. "local-mac-address", enetaddr, 6, 0);
  134. do_fixup_by_prop(blob, "device_type", "network", 8,
  135. "address", enetaddr, 6, 0);
  136. /*
  137. * old device trees have soc nodes with
  138. * device_type = "soc"
  139. */
  140. do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
  141. "bus-frequency", bd->bi_ipsfreq, 0);
  142. }
  143. #endif
  144. static void ft_clock_setup(void *blob, bd_t *bd)
  145. {
  146. char *cpu_path = "/cpus/" OF_CPU;
  147. /*
  148. * fixup cpu clocks using path
  149. */
  150. do_fixup_by_path_u32(blob, cpu_path,
  151. "timebase-frequency", OF_TBCLK, 1);
  152. do_fixup_by_path_u32(blob, cpu_path,
  153. "bus-frequency", bd->bi_busfreq, 1);
  154. do_fixup_by_path_u32(blob, cpu_path,
  155. "clock-frequency", bd->bi_intfreq, 1);
  156. /*
  157. * fixup soc clocks using compatible
  158. */
  159. do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
  160. "bus-frequency", bd->bi_ipsfreq, 1);
  161. }
  162. void ft_cpu_setup(void *blob, bd_t *bd)
  163. {
  164. #ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
  165. old_ft_cpu_setup(blob, bd);
  166. #endif
  167. ft_clock_setup(blob, bd);
  168. #ifdef CONFIG_HAS_ETH0
  169. fdt_fixup_ethernet(blob);
  170. #endif
  171. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  172. }
  173. #endif
  174. #ifdef CONFIG_MPC512x_FEC
  175. /* Default initializations for FEC controllers. To override,
  176. * create a board-specific function called:
  177. * int board_eth_init(bd_t *bis)
  178. */
  179. int cpu_eth_init(bd_t *bis)
  180. {
  181. return mpc512x_fec_initialize(bis);
  182. }
  183. #endif