MPC8313ERDB.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
  4. */
  5. /*
  6. * mpc8313epb board configuration file
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1
  14. #define CONFIG_MPC831x 1
  15. #define CONFIG_MPC8313 1
  16. #define CONFIG_MPC8313ERDB 1
  17. #ifdef CONFIG_NAND
  18. #define CONFIG_SPL_INIT_MINIMAL
  19. #define CONFIG_SPL_FLUSH_IMAGE
  20. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  21. #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  22. #ifdef CONFIG_SPL_BUILD
  23. #define CONFIG_NS16550_MIN_FUNCTIONS
  24. #endif
  25. #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  26. #define CONFIG_SPL_MAX_SIZE (4 * 1024)
  27. #define CONFIG_SPL_PAD_TO 0x4000
  28. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
  29. #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
  30. #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  31. #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
  32. #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  33. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  34. #ifdef CONFIG_SPL_BUILD
  35. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  36. #endif
  37. #endif /* CONFIG_NAND */
  38. #ifndef CONFIG_SYS_MONITOR_BASE
  39. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  40. #endif
  41. #define CONFIG_PCI_INDIRECT_BRIDGE
  42. #define CONFIG_FSL_ELBC 1
  43. /*
  44. * On-board devices
  45. *
  46. * TSEC1 is VSC switch
  47. * TSEC2 is SoC TSEC
  48. */
  49. #define CONFIG_VSC7385_ENET
  50. #define CONFIG_TSEC2
  51. #ifdef CONFIG_SYS_66MHZ
  52. #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
  53. #elif defined(CONFIG_SYS_33MHZ)
  54. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  55. #else
  56. #error Unknown oscillator frequency.
  57. #endif
  58. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  59. #define CONFIG_SYS_IMMR 0xE0000000
  60. #if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
  61. #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
  62. #endif
  63. #define CONFIG_SYS_MEMTEST_START 0x00001000
  64. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  65. /* Early revs of this board will lock up hard when attempting
  66. * to access the PMC registers, unless a JTAG debugger is
  67. * connected, or some resistor modifications are made.
  68. */
  69. #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  70. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  71. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  72. /*
  73. * Device configurations
  74. */
  75. /* Vitesse 7385 */
  76. #ifdef CONFIG_VSC7385_ENET
  77. #define CONFIG_TSEC1
  78. /* The flash address and size of the VSC7385 firmware image */
  79. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  80. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  81. #endif
  82. /*
  83. * DDR Setup
  84. */
  85. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  86. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  87. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  88. /*
  89. * Manually set up DDR parameters, as this board does not
  90. * seem to have the SPD connected to I2C.
  91. */
  92. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  93. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  94. | CSCONFIG_ODT_RD_NEVER \
  95. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  96. | CSCONFIG_ROW_BIT_13 \
  97. | CSCONFIG_COL_BIT_10)
  98. /* 0x80010102 */
  99. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  100. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  101. | (0 << TIMING_CFG0_WRT_SHIFT) \
  102. | (0 << TIMING_CFG0_RRT_SHIFT) \
  103. | (0 << TIMING_CFG0_WWT_SHIFT) \
  104. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  105. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  106. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  107. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  108. /* 0x00220802 */
  109. #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  110. | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  111. | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  112. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  113. | (10 << TIMING_CFG1_REFREC_SHIFT) \
  114. | (3 << TIMING_CFG1_WRREC_SHIFT) \
  115. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  116. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  117. /* 0x3835a322 */
  118. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  119. | (5 << TIMING_CFG2_CPO_SHIFT) \
  120. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  121. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  122. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  123. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  124. | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  125. /* 0x129048c6 */ /* P9-45,may need tuning */
  126. #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
  127. | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  128. /* 0x05100500 */
  129. #if defined(CONFIG_DDR_2T_TIMING)
  130. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  131. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  132. | SDRAM_CFG_DBW_32 \
  133. | SDRAM_CFG_2T_EN)
  134. /* 0x43088000 */
  135. #else
  136. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  137. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  138. | SDRAM_CFG_DBW_32)
  139. /* 0x43080000 */
  140. #endif
  141. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  142. /* set burst length to 8 for 32-bit data path */
  143. #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  144. | (0x0632 << SDRAM_MODE_SD_SHIFT))
  145. /* 0x44480632 */
  146. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  147. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  148. /*0x02000000*/
  149. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  150. | DDRCDR_PZ_NOMZ \
  151. | DDRCDR_NZ_NOMZ \
  152. | DDRCDR_M_ODR)
  153. /*
  154. * FLASH on the Local Bus
  155. */
  156. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  157. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  158. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  159. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  160. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  161. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  162. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
  163. #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
  164. | BR_PS_16 /* 16 bit port */ \
  165. | BR_MS_GPCM /* MSEL = GPCM */ \
  166. | BR_V) /* valid */
  167. #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  168. | OR_GPCM_XACS \
  169. | OR_GPCM_SCY_9 \
  170. | OR_GPCM_EHTR \
  171. | OR_GPCM_EAD)
  172. /* 0xFF006FF7 TODO SLOW 16 MB flash size */
  173. /* window base at flash base */
  174. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  175. /* 16 MB window size */
  176. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
  177. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  178. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
  179. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  180. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  181. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
  182. !defined(CONFIG_SPL_BUILD)
  183. #define CONFIG_SYS_RAMBOOT
  184. #endif
  185. #define CONFIG_SYS_INIT_RAM_LOCK 1
  186. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  187. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  188. #define CONFIG_SYS_GBL_DATA_OFFSET \
  189. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  190. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  191. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  192. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  193. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  194. /*
  195. * Local Bus LCRR and LBCR regs
  196. */
  197. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  198. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  199. #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
  200. | (0xFF << LBCR_BMT_SHIFT) \
  201. | 0xF) /* 0x0004ff0f */
  202. /* LB refresh timer prescal, 266MHz/32 */
  203. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
  204. /* drivers/mtd/nand/raw/nand.c */
  205. #if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
  206. #define CONFIG_SYS_NAND_BASE 0xFFF00000
  207. #else
  208. #define CONFIG_SYS_NAND_BASE 0xE2800000
  209. #endif
  210. #define CONFIG_MTD_PARTITION
  211. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  212. #define CONFIG_NAND_FSL_ELBC 1
  213. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  214. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
  215. #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
  216. | BR_DECC_CHK_GEN /* Use HW ECC */ \
  217. | BR_PS_8 /* 8 bit port */ \
  218. | BR_MS_FCM /* MSEL = FCM */ \
  219. | BR_V) /* valid */
  220. #define CONFIG_SYS_NAND_OR_PRELIM \
  221. (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
  222. | OR_FCM_CSCT \
  223. | OR_FCM_CST \
  224. | OR_FCM_CHT \
  225. | OR_FCM_SCY_1 \
  226. | OR_FCM_TRLX \
  227. | OR_FCM_EHTR)
  228. /* 0xFFFF8396 */
  229. #ifdef CONFIG_NAND
  230. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  231. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  232. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  233. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  234. #else
  235. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  236. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  237. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  238. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  239. #endif
  240. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  241. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  242. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  243. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  244. /* local bus write LED / read status buffer (BCSR) mapping */
  245. #define CONFIG_SYS_BCSR_ADDR 0xFA000000
  246. #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
  247. /* map at 0xFA000000 on LCS3 */
  248. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR \
  249. | BR_PS_8 /* 8 bit port */ \
  250. | BR_MS_GPCM /* MSEL = GPCM */ \
  251. | BR_V) /* valid */
  252. /* 0xFA000801 */
  253. #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
  254. | OR_GPCM_CSNT \
  255. | OR_GPCM_ACS_DIV2 \
  256. | OR_GPCM_XACS \
  257. | OR_GPCM_SCY_15 \
  258. | OR_GPCM_TRLX_SET \
  259. | OR_GPCM_EHTR_SET \
  260. | OR_GPCM_EAD)
  261. /* 0xFFFF8FF7 */
  262. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR
  263. #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  264. /* Vitesse 7385 */
  265. #ifdef CONFIG_VSC7385_ENET
  266. /* VSC7385 Base address on LCS2 */
  267. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  268. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  269. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
  270. | BR_PS_8 /* 8 bit port */ \
  271. | BR_MS_GPCM /* MSEL = GPCM */ \
  272. | BR_V) /* valid */
  273. #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
  274. | OR_GPCM_CSNT \
  275. | OR_GPCM_XACS \
  276. | OR_GPCM_SCY_15 \
  277. | OR_GPCM_SETA \
  278. | OR_GPCM_TRLX_SET \
  279. | OR_GPCM_EHTR_SET \
  280. | OR_GPCM_EAD)
  281. /* 0xFFFE09FF */
  282. /* Access window base at VSC7385 base */
  283. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
  284. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
  285. #endif
  286. #define CONFIG_MPC83XX_GPIO 1
  287. /*
  288. * Serial Port
  289. */
  290. #define CONFIG_SYS_NS16550_SERIAL
  291. #define CONFIG_SYS_NS16550_REG_SIZE 1
  292. #define CONFIG_SYS_BAUDRATE_TABLE \
  293. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  294. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  295. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  296. /* I2C */
  297. #define CONFIG_SYS_I2C
  298. #define CONFIG_SYS_I2C_FSL
  299. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  300. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  301. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  302. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  303. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  304. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  305. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  306. /*
  307. * General PCI
  308. * Addresses are mapped 1-1.
  309. */
  310. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  311. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  312. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  313. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  314. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  315. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  316. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  317. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  318. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  319. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  320. /*
  321. * TSEC
  322. */
  323. #define CONFIG_GMII /* MII PHY management */
  324. #ifdef CONFIG_TSEC1
  325. #define CONFIG_HAS_ETH0
  326. #define CONFIG_TSEC1_NAME "TSEC0"
  327. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  328. #define TSEC1_PHY_ADDR 0x1c
  329. #define TSEC1_FLAGS TSEC_GIGABIT
  330. #define TSEC1_PHYIDX 0
  331. #endif
  332. #ifdef CONFIG_TSEC2
  333. #define CONFIG_HAS_ETH1
  334. #define CONFIG_TSEC2_NAME "TSEC1"
  335. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  336. #define TSEC2_PHY_ADDR 4
  337. #define TSEC2_FLAGS TSEC_GIGABIT
  338. #define TSEC2_PHYIDX 0
  339. #endif
  340. /* Options are: TSEC[0-1] */
  341. #define CONFIG_ETHPRIME "TSEC1"
  342. /*
  343. * Configure on-board RTC
  344. */
  345. #define CONFIG_RTC_DS1337
  346. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  347. /*
  348. * Environment
  349. */
  350. #if defined(CONFIG_NAND)
  351. #define CONFIG_ENV_OFFSET (512 * 1024)
  352. #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  353. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  354. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  355. #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
  356. #define CONFIG_ENV_OFFSET_REDUND \
  357. (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  358. #elif !defined(CONFIG_SYS_RAMBOOT)
  359. #define CONFIG_ENV_ADDR \
  360. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  361. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  362. #define CONFIG_ENV_SIZE 0x2000
  363. /* Address and size of Redundant Environment Sector */
  364. #else
  365. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  366. #define CONFIG_ENV_SIZE 0x2000
  367. #endif
  368. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  369. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  370. /*
  371. * BOOTP options
  372. */
  373. #define CONFIG_BOOTP_BOOTFILESIZE
  374. /*
  375. * Command line configuration.
  376. */
  377. /*
  378. * Miscellaneous configurable options
  379. */
  380. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  381. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  382. /* Boot Argument Buffer Size */
  383. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  384. /*
  385. * For booting Linux, the board info and command line data
  386. * have to be in the first 256 MB of memory, since this is
  387. * the maximum mapped by the Linux kernel during initialization.
  388. */
  389. /* Initial Memory map for Linux*/
  390. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  391. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  392. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  393. #ifdef CONFIG_SYS_66MHZ
  394. /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
  395. /* 0x62040000 */
  396. #define CONFIG_SYS_HRCW_LOW (\
  397. 0x20000000 /* reserved, must be set */ |\
  398. HRCWL_DDRCM |\
  399. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  400. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  401. HRCWL_CSB_TO_CLKIN_2X1 |\
  402. HRCWL_CORE_TO_CSB_2X1)
  403. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  404. #elif defined(CONFIG_SYS_33MHZ)
  405. /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
  406. /* 0x65040000 */
  407. #define CONFIG_SYS_HRCW_LOW (\
  408. 0x20000000 /* reserved, must be set */ |\
  409. HRCWL_DDRCM |\
  410. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  411. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  412. HRCWL_CSB_TO_CLKIN_5X1 |\
  413. HRCWL_CORE_TO_CSB_2X1)
  414. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
  415. #endif
  416. #define CONFIG_SYS_HRCW_HIGH_BASE (\
  417. HRCWH_PCI_HOST |\
  418. HRCWH_PCI1_ARBITER_ENABLE |\
  419. HRCWH_CORE_ENABLE |\
  420. HRCWH_BOOTSEQ_DISABLE |\
  421. HRCWH_SW_WATCHDOG_DISABLE |\
  422. HRCWH_TSEC1M_IN_RGMII |\
  423. HRCWH_TSEC2M_IN_RGMII |\
  424. HRCWH_BIG_ENDIAN)
  425. #ifdef CONFIG_NAND
  426. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  427. HRCWH_FROM_0XFFF00100 |\
  428. HRCWH_ROM_LOC_NAND_SP_8BIT |\
  429. HRCWH_RL_EXT_NAND)
  430. #else
  431. #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  432. HRCWH_FROM_0X00000100 |\
  433. HRCWH_ROM_LOC_LOCAL_16BIT |\
  434. HRCWH_RL_EXT_LEGACY)
  435. #endif
  436. /* System IO Config */
  437. #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
  438. /* Enable Internal USB Phy and GPIO on LCD Connector */
  439. #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
  440. #define CONFIG_SYS_HID0_INIT 0x000000000
  441. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  442. HID0_ENABLE_INSTRUCTION_CACHE | \
  443. HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  444. #define CONFIG_SYS_HID2 HID2_HBE
  445. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  446. /* DDR @ 0x00000000 */
  447. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
  448. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  449. | BATU_BL_256M \
  450. | BATU_VS \
  451. | BATU_VP)
  452. /* PCI @ 0x80000000 */
  453. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
  454. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  455. | BATU_BL_256M \
  456. | BATU_VS \
  457. | BATU_VP)
  458. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  459. | BATL_PP_RW \
  460. | BATL_CACHEINHIBIT \
  461. | BATL_GUARDEDSTORAGE)
  462. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  463. | BATU_BL_256M \
  464. | BATU_VS \
  465. | BATU_VP)
  466. /* PCI2 not supported on 8313 */
  467. #define CONFIG_SYS_IBAT3L (0)
  468. #define CONFIG_SYS_IBAT3U (0)
  469. #define CONFIG_SYS_IBAT4L (0)
  470. #define CONFIG_SYS_IBAT4U (0)
  471. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  472. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  473. | BATL_PP_RW \
  474. | BATL_CACHEINHIBIT \
  475. | BATL_GUARDEDSTORAGE)
  476. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  477. | BATU_BL_256M \
  478. | BATU_VS \
  479. | BATU_VP)
  480. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  481. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  482. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  483. #define CONFIG_SYS_IBAT7L (0)
  484. #define CONFIG_SYS_IBAT7U (0)
  485. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  486. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  487. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  488. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  489. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  490. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  491. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  492. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  493. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  494. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  495. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  496. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  497. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  498. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  499. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  500. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  501. /*
  502. * Environment Configuration
  503. */
  504. #define CONFIG_ENV_OVERWRITE
  505. #define CONFIG_NETDEV "eth1"
  506. #define CONFIG_HOSTNAME "mpc8313erdb"
  507. #define CONFIG_ROOTPATH "/nfs/root/path"
  508. #define CONFIG_BOOTFILE "uImage"
  509. /* U-Boot image on TFTP server */
  510. #define CONFIG_UBOOTPATH "u-boot.bin"
  511. #define CONFIG_FDTFILE "mpc8313erdb.dtb"
  512. /* default location for tftp and bootm */
  513. #define CONFIG_LOADADDR 800000
  514. #define CONFIG_EXTRA_ENV_SETTINGS \
  515. "netdev=" CONFIG_NETDEV "\0" \
  516. "ethprime=TSEC1\0" \
  517. "uboot=" CONFIG_UBOOTPATH "\0" \
  518. "tftpflash=tftpboot $loadaddr $uboot; " \
  519. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  520. " +$filesize; " \
  521. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  522. " +$filesize; " \
  523. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  524. " $filesize; " \
  525. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  526. " +$filesize; " \
  527. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
  528. " $filesize\0" \
  529. "fdtaddr=780000\0" \
  530. "fdtfile=" CONFIG_FDTFILE "\0" \
  531. "console=ttyS0\0" \
  532. "setbootargs=setenv bootargs " \
  533. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  534. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  535. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
  536. "$netdev:off " \
  537. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  538. #define CONFIG_NFSBOOTCOMMAND \
  539. "setenv rootdev /dev/nfs;" \
  540. "run setbootargs;" \
  541. "run setipargs;" \
  542. "tftp $loadaddr $bootfile;" \
  543. "tftp $fdtaddr $fdtfile;" \
  544. "bootm $loadaddr - $fdtaddr"
  545. #define CONFIG_RAMBOOTCOMMAND \
  546. "setenv rootdev /dev/ram;" \
  547. "run setbootargs;" \
  548. "tftp $ramdiskaddr $ramdiskfile;" \
  549. "tftp $loadaddr $bootfile;" \
  550. "tftp $fdtaddr $fdtfile;" \
  551. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  552. #endif /* __CONFIG_H */