zynq_nand.c 35 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq NAND Flash Controller Driver
  6. * This driver is based on plat_nand.c and mxc_nand.c drivers
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <nand.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/rawnand.h>
  15. #include <linux/mtd/partitions.h>
  16. #include <linux/mtd/nand_ecc.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/sys_proto.h>
  19. /* The NAND flash driver defines */
  20. #define ZYNQ_NAND_CMD_PHASE 1
  21. #define ZYNQ_NAND_DATA_PHASE 2
  22. #define ZYNQ_NAND_ECC_SIZE 512
  23. #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
  24. #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
  25. #define ZYNQ_NAND_ECC_STATUS (1 << 6)
  26. #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
  27. #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
  28. #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
  29. #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
  30. /* Flash memory controller operating parameters */
  31. #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
  32. (0x1 << 4) | /* Clear interrupt */ \
  33. (0x1 << 6)) /* Disable ECC interrupt */
  34. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  35. /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  36. #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
  37. (0x2 << 17) | /* t_ar from nand_cycles */ \
  38. (0x1 << 14) | /* t_clr from nand_cycles */ \
  39. (0x3 << 11) | /* t_wp from nand_cycles */ \
  40. (0x2 << 8) | /* t_rea from nand_cycles */ \
  41. (0x5 << 4) | /* t_wc from nand_cycles */ \
  42. (0x5 << 0)) /* t_rc from nand_cycles */
  43. #endif
  44. #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
  45. (0x2 << 21)) /* UpdateRegs operation */
  46. #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
  47. (0x1 << 4) | /* ECC read at end of page */ \
  48. (0x0 << 5)) /* No Jumping */
  49. #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
  50. (0x00 << 8) | /* Read command */ \
  51. (0x30 << 16) | /* Read End command */ \
  52. (0x1 << 24)) /* Read End command calid */
  53. #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
  54. (0x05 << 8) | /* Read col change cmd */ \
  55. (0xE0 << 16) | /* Read col change end cmd */ \
  56. (0x1 << 24)) /* Read col change
  57. end cmd valid */
  58. /* AXI Address definitions */
  59. #define START_CMD_SHIFT 3
  60. #define END_CMD_SHIFT 11
  61. #define END_CMD_VALID_SHIFT 20
  62. #define ADDR_CYCLES_SHIFT 21
  63. #define CLEAR_CS_SHIFT 21
  64. #define ECC_LAST_SHIFT 10
  65. #define COMMAND_PHASE (0 << 19)
  66. #define DATA_PHASE (1 << 19)
  67. #define ONDIE_ECC_FEATURE_ADDR 0x90
  68. #define ONDIE_ECC_FEATURE_ENABLE 0x08
  69. #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
  70. #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
  71. /* ECC block registers bit position and bit mask */
  72. #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
  73. #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
  74. #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F
  75. #define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0
  76. #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13
  77. #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8
  78. enum zynq_nand_bus_width {
  79. NAND_BW_UNKNOWN = -1,
  80. NAND_BW_8BIT,
  81. NAND_BW_16BIT,
  82. };
  83. #ifndef NAND_CMD_LOCK_TIGHT
  84. #define NAND_CMD_LOCK_TIGHT 0x2c
  85. #endif
  86. #ifndef NAND_CMD_LOCK_STATUS
  87. #define NAND_CMD_LOCK_STATUS 0x7a
  88. #endif
  89. /* SMC register set */
  90. struct zynq_nand_smc_regs {
  91. u32 csr; /* 0x00 */
  92. u32 reserved0[2];
  93. u32 cfr; /* 0x0C */
  94. u32 dcr; /* 0x10 */
  95. u32 scr; /* 0x14 */
  96. u32 sor; /* 0x18 */
  97. u32 reserved1[249];
  98. u32 esr; /* 0x400 */
  99. u32 emcr; /* 0x404 */
  100. u32 emcmd1r; /* 0x408 */
  101. u32 emcmd2r; /* 0x40C */
  102. u32 reserved2[2];
  103. u32 eval0r; /* 0x418 */
  104. };
  105. #define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\
  106. ZYNQ_SMC_BASEADDR)
  107. /*
  108. * struct zynq_nand_info - Defines the NAND flash driver instance
  109. * @parts: Pointer to the mtd_partition structure
  110. * @nand_base: Virtual address of the NAND flash device
  111. * @end_cmd_pending: End command is pending
  112. * @end_cmd: End command
  113. */
  114. struct zynq_nand_info {
  115. void __iomem *nand_base;
  116. u8 end_cmd_pending;
  117. u8 end_cmd;
  118. };
  119. /*
  120. * struct zynq_nand_command_format - Defines NAND flash command format
  121. * @start_cmd: First cycle command (Start command)
  122. * @end_cmd: Second cycle command (Last command)
  123. * @addr_cycles: Number of address cycles required to send the address
  124. * @end_cmd_valid: The second cycle command is valid for cmd or data phase
  125. */
  126. struct zynq_nand_command_format {
  127. u8 start_cmd;
  128. u8 end_cmd;
  129. u8 addr_cycles;
  130. u8 end_cmd_valid;
  131. };
  132. /* The NAND flash operations command format */
  133. static const struct zynq_nand_command_format zynq_nand_commands[] = {
  134. {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
  135. {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
  136. {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
  137. {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
  138. {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
  139. {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
  140. {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
  141. {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
  142. {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
  143. {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
  144. {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
  145. {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
  146. {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
  147. {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
  148. {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
  149. {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
  150. {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
  151. /* Add all the flash commands supported by the flash device */
  152. };
  153. /* Define default oob placement schemes for large and small page devices */
  154. static struct nand_ecclayout nand_oob_16 = {
  155. .eccbytes = 3,
  156. .eccpos = {0, 1, 2},
  157. .oobfree = {
  158. { .offset = 8, .length = 8 }
  159. }
  160. };
  161. static struct nand_ecclayout nand_oob_64 = {
  162. .eccbytes = 12,
  163. .eccpos = {
  164. 52, 53, 54, 55, 56, 57,
  165. 58, 59, 60, 61, 62, 63},
  166. .oobfree = {
  167. { .offset = 2, .length = 50 }
  168. }
  169. };
  170. static struct nand_ecclayout ondie_nand_oob_64 = {
  171. .eccbytes = 32,
  172. .eccpos = {
  173. 8, 9, 10, 11, 12, 13, 14, 15,
  174. 24, 25, 26, 27, 28, 29, 30, 31,
  175. 40, 41, 42, 43, 44, 45, 46, 47,
  176. 56, 57, 58, 59, 60, 61, 62, 63
  177. },
  178. .oobfree = {
  179. { .offset = 4, .length = 4 },
  180. { .offset = 20, .length = 4 },
  181. { .offset = 36, .length = 4 },
  182. { .offset = 52, .length = 4 }
  183. }
  184. };
  185. /* bbt decriptors for chips with on-die ECC and
  186. chips with 64-byte OOB */
  187. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  188. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  189. static struct nand_bbt_descr bbt_main_descr = {
  190. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  191. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  192. .offs = 4,
  193. .len = 4,
  194. .veroffs = 20,
  195. .maxblocks = 4,
  196. .pattern = bbt_pattern
  197. };
  198. static struct nand_bbt_descr bbt_mirror_descr = {
  199. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  200. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  201. .offs = 4,
  202. .len = 4,
  203. .veroffs = 20,
  204. .maxblocks = 4,
  205. .pattern = mirror_pattern
  206. };
  207. /*
  208. * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
  209. *
  210. * returns: status for command completion, -1 for Timeout
  211. */
  212. static int zynq_nand_waitfor_ecc_completion(void)
  213. {
  214. unsigned long timeout;
  215. u32 status;
  216. /* Wait max 10us */
  217. timeout = 10;
  218. status = readl(&zynq_nand_smc_base->esr);
  219. while (status & ZYNQ_NAND_ECC_BUSY) {
  220. status = readl(&zynq_nand_smc_base->esr);
  221. if (timeout == 0)
  222. return -1;
  223. timeout--;
  224. udelay(1);
  225. }
  226. return status;
  227. }
  228. /*
  229. * zynq_nand_init_nand_flash - Initialize NAND controller
  230. * @option: Device property flags
  231. *
  232. * This function initializes the NAND flash interface on the NAND controller.
  233. *
  234. * returns: 0 on success or error value on failure
  235. */
  236. static int zynq_nand_init_nand_flash(int option)
  237. {
  238. u32 status;
  239. /* disable interrupts */
  240. writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
  241. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  242. /* Initialize the NAND interface by setting cycles and operation mode */
  243. writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
  244. #endif
  245. if (option & NAND_BUSWIDTH_16)
  246. writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
  247. else
  248. writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
  249. writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
  250. /* Wait till the ECC operation is complete */
  251. status = zynq_nand_waitfor_ecc_completion();
  252. if (status < 0) {
  253. printf("%s: Timeout\n", __func__);
  254. return status;
  255. }
  256. /* Set the command1 and command2 register */
  257. writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
  258. writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
  259. return 0;
  260. }
  261. /*
  262. * zynq_nand_calculate_hwecc - Calculate Hardware ECC
  263. * @mtd: Pointer to the mtd_info structure
  264. * @data: Pointer to the page data
  265. * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
  266. *
  267. * This function retrieves the Hardware ECC data from the controller and returns
  268. * ECC data back to the MTD subsystem.
  269. *
  270. * returns: 0 on success or error value on failure
  271. */
  272. static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
  273. u8 *ecc_code)
  274. {
  275. u32 ecc_value = 0;
  276. u8 ecc_reg, ecc_byte;
  277. u32 ecc_status;
  278. /* Wait till the ECC operation is complete */
  279. ecc_status = zynq_nand_waitfor_ecc_completion();
  280. if (ecc_status < 0) {
  281. printf("%s: Timeout\n", __func__);
  282. return ecc_status;
  283. }
  284. for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
  285. /* Read ECC value for each block */
  286. ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
  287. /* Get the ecc status from ecc read value */
  288. ecc_status = (ecc_value >> 24) & 0xFF;
  289. /* ECC value valid */
  290. if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
  291. for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
  292. /* Copy ECC bytes to MTD buffer */
  293. *ecc_code = ecc_value & 0xFF;
  294. ecc_value = ecc_value >> 8;
  295. ecc_code++;
  296. }
  297. } else {
  298. debug("%s: ecc status failed\n", __func__);
  299. }
  300. }
  301. return 0;
  302. }
  303. /*
  304. * onehot - onehot function
  305. * @value: value to check for onehot
  306. *
  307. * This function checks whether a value is onehot or not.
  308. * onehot is if and only if one bit is set.
  309. *
  310. * FIXME: Try to move this in common.h
  311. */
  312. static bool onehot(unsigned short value)
  313. {
  314. bool onehot;
  315. onehot = value && !(value & (value - 1));
  316. return onehot;
  317. }
  318. /*
  319. * zynq_nand_correct_data - ECC correction function
  320. * @mtd: Pointer to the mtd_info structure
  321. * @buf: Pointer to the page data
  322. * @read_ecc: Pointer to the ECC value read from spare data area
  323. * @calc_ecc: Pointer to the calculated ECC value
  324. *
  325. * This function corrects the ECC single bit errors & detects 2-bit errors.
  326. *
  327. * returns: 0 if no ECC errors found
  328. * 1 if single bit error found and corrected.
  329. * -1 if multiple ECC errors found.
  330. */
  331. static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
  332. unsigned char *read_ecc, unsigned char *calc_ecc)
  333. {
  334. unsigned char bit_addr;
  335. unsigned int byte_addr;
  336. unsigned short ecc_odd, ecc_even;
  337. unsigned short read_ecc_lower, read_ecc_upper;
  338. unsigned short calc_ecc_lower, calc_ecc_upper;
  339. read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
  340. read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
  341. calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
  342. calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
  343. ecc_odd = read_ecc_lower ^ calc_ecc_lower;
  344. ecc_even = read_ecc_upper ^ calc_ecc_upper;
  345. if ((ecc_odd == 0) && (ecc_even == 0))
  346. return 0; /* no error */
  347. if (ecc_odd == (~ecc_even & 0xfff)) {
  348. /* bits [11:3] of error code is byte offset */
  349. byte_addr = (ecc_odd >> 3) & 0x1ff;
  350. /* bits [2:0] of error code is bit offset */
  351. bit_addr = ecc_odd & 0x7;
  352. /* Toggling error bit */
  353. buf[byte_addr] ^= (1 << bit_addr);
  354. return 1;
  355. }
  356. if (onehot(ecc_odd | ecc_even))
  357. return 1; /* one error in parity */
  358. return -1; /* Uncorrectable error */
  359. }
  360. /*
  361. * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
  362. * @mtd: mtd info structure
  363. * @chip: nand chip info structure
  364. * @page: page number to read
  365. * @sndcmd: flag whether to issue read command or not
  366. */
  367. static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  368. int page)
  369. {
  370. unsigned long data_phase_addr = 0;
  371. int data_width = 4;
  372. u8 *p;
  373. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  374. p = chip->oob_poi;
  375. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  376. p += mtd->oobsize - data_width;
  377. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  378. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  379. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  380. chip->read_buf(mtd, p, data_width);
  381. return 0;
  382. }
  383. /*
  384. * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
  385. * @mtd: mtd info structure
  386. * @chip: nand chip info structure
  387. * @page: page number to write
  388. */
  389. static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  390. int page)
  391. {
  392. int status = 0, data_width = 4;
  393. const u8 *buf = chip->oob_poi;
  394. unsigned long data_phase_addr = 0;
  395. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  396. chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
  397. buf += mtd->oobsize - data_width;
  398. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  399. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  400. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  401. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  402. chip->write_buf(mtd, buf, data_width);
  403. /* Send command to program the OOB data */
  404. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  405. status = chip->waitfunc(mtd, chip);
  406. return status & NAND_STATUS_FAIL ? -EIO : 0;
  407. }
  408. /*
  409. * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
  410. * @mtd: mtd info structure
  411. * @chip: nand chip info structure
  412. * @buf: buffer to store read data
  413. * @oob_required: must write chip->oob_poi to OOB
  414. * @page: page number to read
  415. */
  416. static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  417. u8 *buf, int oob_required, int page)
  418. {
  419. unsigned long data_width = 4;
  420. unsigned long data_phase_addr = 0;
  421. u8 *p;
  422. chip->read_buf(mtd, buf, mtd->writesize);
  423. p = chip->oob_poi;
  424. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  425. p += (mtd->oobsize - data_width);
  426. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  427. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  428. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  429. chip->read_buf(mtd, p, data_width);
  430. return 0;
  431. }
  432. static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
  433. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  434. {
  435. chip->read_buf(mtd, buf, mtd->writesize);
  436. return 0;
  437. }
  438. static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
  439. struct nand_chip *chip, u32 data_offs,
  440. u32 readlen, u8 *buf, int page)
  441. {
  442. if (data_offs != 0) {
  443. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
  444. buf += data_offs;
  445. }
  446. chip->read_buf(mtd, buf, readlen);
  447. return 0;
  448. }
  449. /*
  450. * zynq_nand_write_page_raw - [Intern] raw page write function
  451. * @mtd: mtd info structure
  452. * @chip: nand chip info structure
  453. * @buf: data buffer
  454. * @oob_required: must write chip->oob_poi to OOB
  455. */
  456. static int zynq_nand_write_page_raw(struct mtd_info *mtd,
  457. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  458. {
  459. unsigned long data_width = 4;
  460. unsigned long data_phase_addr = 0;
  461. u8 *p;
  462. chip->write_buf(mtd, buf, mtd->writesize);
  463. p = chip->oob_poi;
  464. chip->write_buf(mtd, p, (mtd->oobsize - data_width));
  465. p += (mtd->oobsize - data_width);
  466. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  467. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  468. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  469. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  470. chip->write_buf(mtd, p, data_width);
  471. return 0;
  472. }
  473. /*
  474. * nand_write_page_hwecc - Hardware ECC based page write function
  475. * @mtd: Pointer to the mtd info structure
  476. * @chip: Pointer to the NAND chip info structure
  477. * @buf: Pointer to the data buffer
  478. * @oob_required: must write chip->oob_poi to OOB
  479. *
  480. * This functions writes data and hardware generated ECC values in to the page.
  481. */
  482. static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
  483. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  484. {
  485. int i, eccsteps, eccsize = chip->ecc.size;
  486. u8 *ecc_calc = chip->buffers->ecccalc;
  487. const u8 *p = buf;
  488. u32 *eccpos = chip->ecc.layout->eccpos;
  489. unsigned long data_phase_addr = 0;
  490. unsigned long data_width = 4;
  491. u8 *oob_ptr;
  492. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  493. chip->write_buf(mtd, p, eccsize);
  494. p += eccsize;
  495. }
  496. chip->write_buf(mtd, p, (eccsize - data_width));
  497. p += eccsize - data_width;
  498. /* Set ECC Last bit to 1 */
  499. data_phase_addr = (unsigned long) chip->IO_ADDR_W;
  500. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  501. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  502. chip->write_buf(mtd, p, data_width);
  503. /* Wait for ECC to be calculated and read the error values */
  504. p = buf;
  505. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  506. for (i = 0; i < chip->ecc.total; i++)
  507. chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
  508. /* Clear ECC last bit */
  509. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  510. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  511. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  512. /* Write the spare area with ECC bytes */
  513. oob_ptr = chip->oob_poi;
  514. chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  515. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  516. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  517. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  518. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  519. oob_ptr += (mtd->oobsize - data_width);
  520. chip->write_buf(mtd, oob_ptr, data_width);
  521. return 0;
  522. }
  523. /*
  524. * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
  525. * write function
  526. * @mtd: mtd info structure
  527. * @chip: nand chip info structure
  528. * @buf: data buffer
  529. * @oob_required: must write chip->oob_poi to OOB
  530. */
  531. static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
  532. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  533. {
  534. int i, eccsize = chip->ecc.size;
  535. int eccbytes = chip->ecc.bytes;
  536. int eccsteps = chip->ecc.steps;
  537. u8 *ecc_calc = chip->buffers->ecccalc;
  538. const u8 *p = buf;
  539. u32 *eccpos = chip->ecc.layout->eccpos;
  540. /* Software ecc calculation */
  541. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  542. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  543. for (i = 0; i < chip->ecc.total; i++)
  544. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  545. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  546. }
  547. /*
  548. * nand_read_page_hwecc - Hardware ECC based page read function
  549. * @mtd: Pointer to the mtd info structure
  550. * @chip: Pointer to the NAND chip info structure
  551. * @buf: Pointer to the buffer to store read data
  552. * @oob_required: must write chip->oob_poi to OOB
  553. * @page: page number to read
  554. *
  555. * This functions reads data and checks the data integrity by comparing hardware
  556. * generated ECC values and read ECC values from spare area.
  557. *
  558. * returns: 0 always and updates ECC operation status in to MTD structure
  559. */
  560. static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
  561. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  562. {
  563. int i, stat, eccsteps, eccsize = chip->ecc.size;
  564. int eccbytes = chip->ecc.bytes;
  565. u8 *p = buf;
  566. u8 *ecc_calc = chip->buffers->ecccalc;
  567. u8 *ecc_code = chip->buffers->ecccode;
  568. u32 *eccpos = chip->ecc.layout->eccpos;
  569. unsigned long data_phase_addr = 0;
  570. unsigned long data_width = 4;
  571. u8 *oob_ptr;
  572. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  573. chip->read_buf(mtd, p, eccsize);
  574. p += eccsize;
  575. }
  576. chip->read_buf(mtd, p, (eccsize - data_width));
  577. p += eccsize - data_width;
  578. /* Set ECC Last bit to 1 */
  579. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  580. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  581. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  582. chip->read_buf(mtd, p, data_width);
  583. /* Read the calculated ECC value */
  584. p = buf;
  585. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  586. /* Clear ECC last bit */
  587. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  588. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  589. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  590. /* Read the stored ECC value */
  591. oob_ptr = chip->oob_poi;
  592. chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  593. /* de-assert chip select */
  594. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  595. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  596. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  597. oob_ptr += (mtd->oobsize - data_width);
  598. chip->read_buf(mtd, oob_ptr, data_width);
  599. for (i = 0; i < chip->ecc.total; i++)
  600. ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
  601. eccsteps = chip->ecc.steps;
  602. p = buf;
  603. /* Check ECC error for all blocks and correct if it is correctable */
  604. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  605. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  606. if (stat < 0)
  607. mtd->ecc_stats.failed++;
  608. else
  609. mtd->ecc_stats.corrected += stat;
  610. }
  611. return 0;
  612. }
  613. /*
  614. * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
  615. * read function
  616. * @mtd: mtd info structure
  617. * @chip: nand chip info structure
  618. * @buf: buffer to store read data
  619. * @page: page number to read
  620. */
  621. static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
  622. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  623. {
  624. int i, eccsize = chip->ecc.size;
  625. int eccbytes = chip->ecc.bytes;
  626. int eccsteps = chip->ecc.steps;
  627. u8 *p = buf;
  628. u8 *ecc_calc = chip->buffers->ecccalc;
  629. u8 *ecc_code = chip->buffers->ecccode;
  630. u32 *eccpos = chip->ecc.layout->eccpos;
  631. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  632. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  633. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  634. for (i = 0; i < chip->ecc.total; i++)
  635. ecc_code[i] = chip->oob_poi[eccpos[i]];
  636. eccsteps = chip->ecc.steps;
  637. p = buf;
  638. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  639. int stat;
  640. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  641. if (stat < 0)
  642. mtd->ecc_stats.failed++;
  643. else
  644. mtd->ecc_stats.corrected += stat;
  645. }
  646. return 0;
  647. }
  648. /*
  649. * zynq_nand_select_chip - Select the flash device
  650. * @mtd: Pointer to the mtd_info structure
  651. * @chip: Chip number to be selected
  652. *
  653. * This function is empty as the NAND controller handles chip select line
  654. * internally based on the chip address passed in command and data phase.
  655. */
  656. static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
  657. {
  658. /* Not support multiple chips yet */
  659. }
  660. /*
  661. * zynq_nand_cmd_function - Send command to NAND device
  662. * @mtd: Pointer to the mtd_info structure
  663. * @command: The command to be sent to the flash device
  664. * @column: The column address for this command, -1 if none
  665. * @page_addr: The page address for this command, -1 if none
  666. */
  667. static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  668. int column, int page_addr)
  669. {
  670. struct nand_chip *chip = mtd->priv;
  671. const struct zynq_nand_command_format *curr_cmd = NULL;
  672. u8 addr_cycles = 0;
  673. struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
  674. void *cmd_addr;
  675. unsigned long cmd_data = 0;
  676. unsigned long cmd_phase_addr = 0;
  677. unsigned long data_phase_addr = 0;
  678. u8 end_cmd = 0;
  679. u8 end_cmd_valid = 0;
  680. u32 index;
  681. if (xnand->end_cmd_pending) {
  682. /* Check for end command if this command request is same as the
  683. * pending command then return
  684. */
  685. if (xnand->end_cmd == command) {
  686. xnand->end_cmd = 0;
  687. xnand->end_cmd_pending = 0;
  688. return;
  689. }
  690. }
  691. /* Emulate NAND_CMD_READOOB for large page device */
  692. if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
  693. (command == NAND_CMD_READOOB)) {
  694. column += mtd->writesize;
  695. command = NAND_CMD_READ0;
  696. }
  697. /* Get the command format */
  698. for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
  699. if (command == zynq_nand_commands[index].start_cmd)
  700. break;
  701. if (index == ARRAY_SIZE(zynq_nand_commands)) {
  702. printf("%s: Unsupported start cmd %02x\n", __func__, command);
  703. return;
  704. }
  705. curr_cmd = &zynq_nand_commands[index];
  706. /* Clear interrupt */
  707. writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
  708. /* Get the command phase address */
  709. if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
  710. end_cmd_valid = 1;
  711. if (curr_cmd->end_cmd == NAND_CMD_NONE)
  712. end_cmd = 0x0;
  713. else
  714. end_cmd = curr_cmd->end_cmd;
  715. if (command == NAND_CMD_READ0 ||
  716. command == NAND_CMD_SEQIN) {
  717. addr_cycles = chip->onfi_params.addr_cycles &
  718. ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
  719. addr_cycles += ((chip->onfi_params.addr_cycles &
  720. ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
  721. } else {
  722. addr_cycles = curr_cmd->addr_cycles;
  723. }
  724. cmd_phase_addr = (unsigned long)xnand->nand_base |
  725. (addr_cycles << ADDR_CYCLES_SHIFT) |
  726. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  727. (COMMAND_PHASE) |
  728. (end_cmd << END_CMD_SHIFT) |
  729. (curr_cmd->start_cmd << START_CMD_SHIFT);
  730. cmd_addr = (void __iomem *)cmd_phase_addr;
  731. /* Get the data phase address */
  732. end_cmd_valid = 0;
  733. data_phase_addr = (unsigned long)xnand->nand_base |
  734. (0x0 << CLEAR_CS_SHIFT) |
  735. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  736. (DATA_PHASE) |
  737. (end_cmd << END_CMD_SHIFT) |
  738. (0x0 << ECC_LAST_SHIFT);
  739. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  740. chip->IO_ADDR_W = chip->IO_ADDR_R;
  741. /* Command phase AXI Read & Write */
  742. if (column != -1 && page_addr != -1) {
  743. /* Adjust columns for 16 bit bus width */
  744. if (chip->options & NAND_BUSWIDTH_16)
  745. column >>= 1;
  746. cmd_data = column;
  747. if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
  748. cmd_data |= page_addr << 16;
  749. /* Another address cycle for devices > 128MiB */
  750. if (chip->chipsize > (128 << 20)) {
  751. writel(cmd_data, cmd_addr);
  752. cmd_data = (page_addr >> 16);
  753. }
  754. } else {
  755. cmd_data |= page_addr << 8;
  756. }
  757. } else if (page_addr != -1) { /* Erase */
  758. cmd_data = page_addr;
  759. } else if (column != -1) { /* Change read/write column, read id etc */
  760. /* Adjust columns for 16 bit bus width */
  761. if ((chip->options & NAND_BUSWIDTH_16) &&
  762. ((command == NAND_CMD_READ0) ||
  763. (command == NAND_CMD_SEQIN) ||
  764. (command == NAND_CMD_RNDOUT) ||
  765. (command == NAND_CMD_RNDIN)))
  766. column >>= 1;
  767. cmd_data = column;
  768. }
  769. writel(cmd_data, cmd_addr);
  770. if (curr_cmd->end_cmd_valid) {
  771. xnand->end_cmd = curr_cmd->end_cmd;
  772. xnand->end_cmd_pending = 1;
  773. }
  774. ndelay(100);
  775. if ((command == NAND_CMD_READ0) ||
  776. (command == NAND_CMD_RESET) ||
  777. (command == NAND_CMD_PARAM) ||
  778. (command == NAND_CMD_GET_FEATURES))
  779. /* wait until command is processed */
  780. nand_wait_ready(mtd);
  781. }
  782. /*
  783. * zynq_nand_read_buf - read chip data into buffer
  784. * @mtd: MTD device structure
  785. * @buf: buffer to store date
  786. * @len: number of bytes to read
  787. */
  788. static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  789. {
  790. struct nand_chip *chip = mtd->priv;
  791. /* Make sure that buf is 32 bit aligned */
  792. if (((unsigned long)buf & 0x3) != 0) {
  793. if (((unsigned long)buf & 0x1) != 0) {
  794. if (len) {
  795. *buf = readb(chip->IO_ADDR_R);
  796. buf += 1;
  797. len--;
  798. }
  799. }
  800. if (((unsigned long)buf & 0x3) != 0) {
  801. if (len >= 2) {
  802. *(u16 *)buf = readw(chip->IO_ADDR_R);
  803. buf += 2;
  804. len -= 2;
  805. }
  806. }
  807. }
  808. /* copy aligned data */
  809. while (len >= 4) {
  810. *(u32 *)buf = readl(chip->IO_ADDR_R);
  811. buf += 4;
  812. len -= 4;
  813. }
  814. /* mop up any remaining bytes */
  815. if (len) {
  816. if (len >= 2) {
  817. *(u16 *)buf = readw(chip->IO_ADDR_R);
  818. buf += 2;
  819. len -= 2;
  820. }
  821. if (len)
  822. *buf = readb(chip->IO_ADDR_R);
  823. }
  824. }
  825. /*
  826. * zynq_nand_write_buf - write buffer to chip
  827. * @mtd: MTD device structure
  828. * @buf: data buffer
  829. * @len: number of bytes to write
  830. */
  831. static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  832. {
  833. struct nand_chip *chip = mtd->priv;
  834. const u32 *nand = chip->IO_ADDR_W;
  835. /* Make sure that buf is 32 bit aligned */
  836. if (((unsigned long)buf & 0x3) != 0) {
  837. if (((unsigned long)buf & 0x1) != 0) {
  838. if (len) {
  839. writeb(*buf, nand);
  840. buf += 1;
  841. len--;
  842. }
  843. }
  844. if (((unsigned long)buf & 0x3) != 0) {
  845. if (len >= 2) {
  846. writew(*(u16 *)buf, nand);
  847. buf += 2;
  848. len -= 2;
  849. }
  850. }
  851. }
  852. /* copy aligned data */
  853. while (len >= 4) {
  854. writel(*(u32 *)buf, nand);
  855. buf += 4;
  856. len -= 4;
  857. }
  858. /* mop up any remaining bytes */
  859. if (len) {
  860. if (len >= 2) {
  861. writew(*(u16 *)buf, nand);
  862. buf += 2;
  863. len -= 2;
  864. }
  865. if (len)
  866. writeb(*buf, nand);
  867. }
  868. }
  869. /*
  870. * zynq_nand_device_ready - Check device ready/busy line
  871. * @mtd: Pointer to the mtd_info structure
  872. *
  873. * returns: 0 on busy or 1 on ready state
  874. */
  875. static int zynq_nand_device_ready(struct mtd_info *mtd)
  876. {
  877. u32 csr_val;
  878. csr_val = readl(&zynq_nand_smc_base->csr);
  879. /* Check the raw_int_status1 bit */
  880. if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
  881. /* Clear the interrupt condition */
  882. writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
  883. return 1;
  884. }
  885. return 0;
  886. }
  887. static int zynq_nand_check_is_16bit_bw_flash(void)
  888. {
  889. int is_16bit_bw = NAND_BW_UNKNOWN;
  890. int mio_num_8bit = 0, mio_num_16bit = 0;
  891. mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
  892. if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
  893. is_16bit_bw = NAND_BW_8BIT;
  894. mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
  895. if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
  896. mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
  897. is_16bit_bw = NAND_BW_16BIT;
  898. return is_16bit_bw;
  899. }
  900. static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
  901. {
  902. struct zynq_nand_info *xnand;
  903. struct mtd_info *mtd;
  904. unsigned long ecc_page_size;
  905. u8 maf_id, dev_id, i;
  906. u8 get_feature[4];
  907. u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
  908. unsigned long ecc_cfg;
  909. int ondie_ecc_enabled = 0;
  910. int err = -1;
  911. int is_16bit_bw;
  912. xnand = calloc(1, sizeof(struct zynq_nand_info));
  913. if (!xnand) {
  914. printf("%s: failed to allocate\n", __func__);
  915. goto fail;
  916. }
  917. xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
  918. mtd = nand_to_mtd(nand_chip);
  919. nand_chip->priv = xnand;
  920. mtd->priv = nand_chip;
  921. /* Set address of NAND IO lines */
  922. nand_chip->IO_ADDR_R = xnand->nand_base;
  923. nand_chip->IO_ADDR_W = xnand->nand_base;
  924. /* Set the driver entry points for MTD */
  925. nand_chip->cmdfunc = zynq_nand_cmd_function;
  926. nand_chip->dev_ready = zynq_nand_device_ready;
  927. nand_chip->select_chip = zynq_nand_select_chip;
  928. /* If we don't set this delay driver sets 20us by default */
  929. nand_chip->chip_delay = 30;
  930. /* Buffer read/write routines */
  931. nand_chip->read_buf = zynq_nand_read_buf;
  932. nand_chip->write_buf = zynq_nand_write_buf;
  933. is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
  934. if (is_16bit_bw == NAND_BW_UNKNOWN) {
  935. printf("%s: Unable detect NAND based on MIO settings\n",
  936. __func__);
  937. goto fail;
  938. }
  939. if (is_16bit_bw == NAND_BW_16BIT)
  940. nand_chip->options = NAND_BUSWIDTH_16;
  941. nand_chip->bbt_options = NAND_BBT_USE_FLASH;
  942. /* Initialize the NAND flash interface on NAND controller */
  943. if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
  944. printf("%s: nand flash init failed\n", __func__);
  945. goto fail;
  946. }
  947. /* first scan to find the device and get the page size */
  948. if (nand_scan_ident(mtd, 1, NULL)) {
  949. printf("%s: nand_scan_ident failed\n", __func__);
  950. goto fail;
  951. }
  952. /* Send the command for reading device ID */
  953. nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  954. nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  955. /* Read manufacturer and device IDs */
  956. maf_id = nand_chip->read_byte(mtd);
  957. dev_id = nand_chip->read_byte(mtd);
  958. if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
  959. (dev_id == 0xa1) || (dev_id == 0xb1) ||
  960. (dev_id == 0xaa) || (dev_id == 0xba) ||
  961. (dev_id == 0xda) || (dev_id == 0xca) ||
  962. (dev_id == 0xac) || (dev_id == 0xbc) ||
  963. (dev_id == 0xdc) || (dev_id == 0xcc) ||
  964. (dev_id == 0xa3) || (dev_id == 0xb3) ||
  965. (dev_id == 0xd3) || (dev_id == 0xc3))) {
  966. nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
  967. ONDIE_ECC_FEATURE_ADDR, -1);
  968. for (i = 0; i < 4; i++)
  969. writeb(set_feature[i], nand_chip->IO_ADDR_W);
  970. /* Wait for 1us after writing data with SET_FEATURES command */
  971. ndelay(1000);
  972. nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
  973. ONDIE_ECC_FEATURE_ADDR, -1);
  974. nand_chip->read_buf(mtd, get_feature, 4);
  975. if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
  976. debug("%s: OnDie ECC flash\n", __func__);
  977. ondie_ecc_enabled = 1;
  978. } else {
  979. printf("%s: Unable to detect OnDie ECC\n", __func__);
  980. }
  981. }
  982. if (ondie_ecc_enabled) {
  983. /* Bypass the controller ECC block */
  984. ecc_cfg = readl(&zynq_nand_smc_base->emcr);
  985. ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
  986. writel(ecc_cfg, &zynq_nand_smc_base->emcr);
  987. /* The software ECC routines won't work
  988. * with the SMC controller
  989. */
  990. nand_chip->ecc.mode = NAND_ECC_HW;
  991. nand_chip->ecc.strength = 1;
  992. nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
  993. nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
  994. nand_chip->ecc.write_page = zynq_nand_write_page_raw;
  995. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  996. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  997. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  998. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  999. nand_chip->ecc.size = mtd->writesize;
  1000. nand_chip->ecc.bytes = 0;
  1001. /* NAND with on-die ECC supports subpage reads */
  1002. nand_chip->options |= NAND_SUBPAGE_READ;
  1003. /* On-Die ECC spare bytes offset 8 is used for ECC codes */
  1004. if (ondie_ecc_enabled) {
  1005. nand_chip->ecc.layout = &ondie_nand_oob_64;
  1006. /* Use the BBT pattern descriptors */
  1007. nand_chip->bbt_td = &bbt_main_descr;
  1008. nand_chip->bbt_md = &bbt_mirror_descr;
  1009. }
  1010. } else {
  1011. /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
  1012. nand_chip->ecc.mode = NAND_ECC_HW;
  1013. nand_chip->ecc.strength = 1;
  1014. nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
  1015. nand_chip->ecc.bytes = 3;
  1016. nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
  1017. nand_chip->ecc.correct = zynq_nand_correct_data;
  1018. nand_chip->ecc.hwctl = NULL;
  1019. nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
  1020. nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
  1021. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  1022. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  1023. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  1024. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  1025. switch (mtd->writesize) {
  1026. case 512:
  1027. ecc_page_size = 0x1;
  1028. /* Set the ECC memory config register */
  1029. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1030. &zynq_nand_smc_base->emcr);
  1031. break;
  1032. case 1024:
  1033. ecc_page_size = 0x2;
  1034. /* Set the ECC memory config register */
  1035. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1036. &zynq_nand_smc_base->emcr);
  1037. break;
  1038. case 2048:
  1039. ecc_page_size = 0x3;
  1040. /* Set the ECC memory config register */
  1041. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1042. &zynq_nand_smc_base->emcr);
  1043. break;
  1044. default:
  1045. nand_chip->ecc.mode = NAND_ECC_SOFT;
  1046. nand_chip->ecc.calculate = nand_calculate_ecc;
  1047. nand_chip->ecc.correct = nand_correct_data;
  1048. nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
  1049. nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
  1050. nand_chip->ecc.size = 256;
  1051. break;
  1052. }
  1053. if (mtd->oobsize == 16)
  1054. nand_chip->ecc.layout = &nand_oob_16;
  1055. else if (mtd->oobsize == 64)
  1056. nand_chip->ecc.layout = &nand_oob_64;
  1057. else
  1058. printf("%s: No oob layout found\n", __func__);
  1059. }
  1060. /* Second phase scan */
  1061. if (nand_scan_tail(mtd)) {
  1062. printf("%s: nand_scan_tail failed\n", __func__);
  1063. goto fail;
  1064. }
  1065. if (nand_register(devnum, mtd))
  1066. goto fail;
  1067. return 0;
  1068. fail:
  1069. free(xnand);
  1070. return err;
  1071. }
  1072. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  1073. void board_nand_init(void)
  1074. {
  1075. struct nand_chip *nand = &nand_chip[0];
  1076. if (zynq_nand_init(nand, 0))
  1077. puts("ZYNQ NAND init failed\n");
  1078. }