vf610_nfc.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
  4. *
  5. * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
  6. * Ported to U-Boot by Stefan Agner
  7. * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
  8. * Jason ported to M54418TWR and MVFA5.
  9. * Authors: Stefan Agner <stefan.agner@toradex.com>
  10. * Bill Pringlemeir <bpringlemeir@nbsps.com>
  11. * Shaohui Xie <b21989@freescale.com>
  12. * Jason Jin <Jason.jin@freescale.com>
  13. *
  14. * Based on original driver mpc5121_nfc.c.
  15. *
  16. * Limitations:
  17. * - Untested on MPC5125 and M54418.
  18. * - DMA and pipelining not used.
  19. * - 2K pages or less.
  20. * - HW ECC: Only 2K page with 64+ OOB.
  21. * - HW ECC: Only 24 and 32-bit error correction implemented.
  22. */
  23. #include <common.h>
  24. #include <malloc.h>
  25. #include <linux/mtd/mtd.h>
  26. #include <linux/mtd/rawnand.h>
  27. #include <linux/mtd/partitions.h>
  28. #include <nand.h>
  29. #include <errno.h>
  30. #include <asm/io.h>
  31. /* Register Offsets */
  32. #define NFC_FLASH_CMD1 0x3F00
  33. #define NFC_FLASH_CMD2 0x3F04
  34. #define NFC_COL_ADDR 0x3F08
  35. #define NFC_ROW_ADDR 0x3F0c
  36. #define NFC_ROW_ADDR_INC 0x3F14
  37. #define NFC_FLASH_STATUS1 0x3F18
  38. #define NFC_FLASH_STATUS2 0x3F1c
  39. #define NFC_CACHE_SWAP 0x3F28
  40. #define NFC_SECTOR_SIZE 0x3F2c
  41. #define NFC_FLASH_CONFIG 0x3F30
  42. #define NFC_IRQ_STATUS 0x3F38
  43. /* Addresses for NFC MAIN RAM BUFFER areas */
  44. #define NFC_MAIN_AREA(n) ((n) * 0x1000)
  45. #define PAGE_2K 0x0800
  46. #define OOB_64 0x0040
  47. #define OOB_MAX 0x0100
  48. /*
  49. * NFC_CMD2[CODE] values. See section:
  50. * - 31.4.7 Flash Command Code Description, Vybrid manual
  51. * - 23.8.6 Flash Command Sequencer, MPC5125 manual
  52. *
  53. * Briefly these are bitmasks of controller cycles.
  54. */
  55. #define READ_PAGE_CMD_CODE 0x7EE0
  56. #define READ_ONFI_PARAM_CMD_CODE 0x4860
  57. #define PROGRAM_PAGE_CMD_CODE 0x7FC0
  58. #define ERASE_CMD_CODE 0x4EC0
  59. #define READ_ID_CMD_CODE 0x4804
  60. #define RESET_CMD_CODE 0x4040
  61. #define STATUS_READ_CMD_CODE 0x4068
  62. /* NFC ECC mode define */
  63. #define ECC_BYPASS 0
  64. #define ECC_45_BYTE 6
  65. #define ECC_60_BYTE 7
  66. /*** Register Mask and bit definitions */
  67. /* NFC_FLASH_CMD1 Field */
  68. #define CMD_BYTE2_MASK 0xFF000000
  69. #define CMD_BYTE2_SHIFT 24
  70. /* NFC_FLASH_CM2 Field */
  71. #define CMD_BYTE1_MASK 0xFF000000
  72. #define CMD_BYTE1_SHIFT 24
  73. #define CMD_CODE_MASK 0x00FFFF00
  74. #define CMD_CODE_SHIFT 8
  75. #define BUFNO_MASK 0x00000006
  76. #define BUFNO_SHIFT 1
  77. #define START_BIT (1<<0)
  78. /* NFC_COL_ADDR Field */
  79. #define COL_ADDR_MASK 0x0000FFFF
  80. #define COL_ADDR_SHIFT 0
  81. /* NFC_ROW_ADDR Field */
  82. #define ROW_ADDR_MASK 0x00FFFFFF
  83. #define ROW_ADDR_SHIFT 0
  84. #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
  85. #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
  86. #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
  87. #define ROW_ADDR_CHIP_SEL_SHIFT 24
  88. /* NFC_FLASH_STATUS2 Field */
  89. #define STATUS_BYTE1_MASK 0x000000FF
  90. /* NFC_FLASH_CONFIG Field */
  91. #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
  92. #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
  93. #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
  94. #define CONFIG_DMA_REQ_BIT (1<<20)
  95. #define CONFIG_ECC_MODE_MASK 0x000E0000
  96. #define CONFIG_ECC_MODE_SHIFT 17
  97. #define CONFIG_FAST_FLASH_BIT (1<<16)
  98. #define CONFIG_16BIT (1<<7)
  99. #define CONFIG_BOOT_MODE_BIT (1<<6)
  100. #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
  101. #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
  102. #define CONFIG_PAGE_CNT_MASK 0xF
  103. #define CONFIG_PAGE_CNT_SHIFT 0
  104. /* NFC_IRQ_STATUS Field */
  105. #define IDLE_IRQ_BIT (1<<29)
  106. #define IDLE_EN_BIT (1<<20)
  107. #define CMD_DONE_CLEAR_BIT (1<<18)
  108. #define IDLE_CLEAR_BIT (1<<17)
  109. #define NFC_TIMEOUT (1000)
  110. /*
  111. * ECC status - seems to consume 8 bytes (double word). The documented
  112. * status byte is located in the lowest byte of the second word (which is
  113. * the 4th or 7th byte depending on endianness).
  114. * Calculate an offset to store the ECC status at the end of the buffer.
  115. */
  116. #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
  117. #define ECC_STATUS 0x4
  118. #define ECC_STATUS_MASK 0x80
  119. #define ECC_STATUS_ERR_COUNT 0x3F
  120. enum vf610_nfc_alt_buf {
  121. ALT_BUF_DATA = 0,
  122. ALT_BUF_ID = 1,
  123. ALT_BUF_STAT = 2,
  124. ALT_BUF_ONFI = 3,
  125. };
  126. struct vf610_nfc {
  127. struct nand_chip chip;
  128. void __iomem *regs;
  129. uint buf_offset;
  130. int write_sz;
  131. /* Status and ID are in alternate locations. */
  132. enum vf610_nfc_alt_buf alt_buf;
  133. };
  134. #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
  135. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  136. #define ECC_HW_MODE ECC_45_BYTE
  137. static struct nand_ecclayout vf610_nfc_ecc = {
  138. .eccbytes = 45,
  139. .eccpos = {19, 20, 21, 22, 23,
  140. 24, 25, 26, 27, 28, 29, 30, 31,
  141. 32, 33, 34, 35, 36, 37, 38, 39,
  142. 40, 41, 42, 43, 44, 45, 46, 47,
  143. 48, 49, 50, 51, 52, 53, 54, 55,
  144. 56, 57, 58, 59, 60, 61, 62, 63},
  145. .oobfree = {
  146. {.offset = 2,
  147. .length = 17} }
  148. };
  149. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  150. #define ECC_HW_MODE ECC_60_BYTE
  151. static struct nand_ecclayout vf610_nfc_ecc = {
  152. .eccbytes = 60,
  153. .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
  154. 12, 13, 14, 15, 16, 17, 18, 19,
  155. 20, 21, 22, 23, 24, 25, 26, 27,
  156. 28, 29, 30, 31, 32, 33, 34, 35,
  157. 36, 37, 38, 39, 40, 41, 42, 43,
  158. 44, 45, 46, 47, 48, 49, 50, 51,
  159. 52, 53, 54, 55, 56, 57, 58, 59,
  160. 60, 61, 62, 63 },
  161. .oobfree = {
  162. {.offset = 2,
  163. .length = 2} }
  164. };
  165. #endif
  166. static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
  167. {
  168. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  169. return readl(nfc->regs + reg);
  170. }
  171. static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
  172. {
  173. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  174. writel(val, nfc->regs + reg);
  175. }
  176. static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
  177. {
  178. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
  179. }
  180. static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
  181. {
  182. vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
  183. }
  184. static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
  185. u32 mask, u32 shift, u32 val)
  186. {
  187. vf610_nfc_write(mtd, reg,
  188. (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
  189. }
  190. static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
  191. {
  192. /*
  193. * Use this accessor for the internal SRAM buffers. On the ARM
  194. * Freescale Vybrid SoC it's known that the driver can treat
  195. * the SRAM buffer as if it's memory. Other platform might need
  196. * to treat the buffers differently.
  197. *
  198. * For the time being, use memcpy
  199. */
  200. memcpy(dst, src, n);
  201. }
  202. /* Clear flags for upcoming command */
  203. static inline void vf610_nfc_clear_status(void __iomem *regbase)
  204. {
  205. void __iomem *reg = regbase + NFC_IRQ_STATUS;
  206. u32 tmp = __raw_readl(reg);
  207. tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
  208. __raw_writel(tmp, reg);
  209. }
  210. /* Wait for complete operation */
  211. static void vf610_nfc_done(struct mtd_info *mtd)
  212. {
  213. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  214. uint start;
  215. /*
  216. * Barrier is needed after this write. This write need
  217. * to be done before reading the next register the first
  218. * time.
  219. * vf610_nfc_set implicates such a barrier by using writel
  220. * to write to the register.
  221. */
  222. vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
  223. start = get_timer(0);
  224. while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
  225. if (get_timer(start) > NFC_TIMEOUT) {
  226. printf("Timeout while waiting for IDLE.\n");
  227. return;
  228. }
  229. }
  230. vf610_nfc_clear_status(nfc->regs);
  231. }
  232. static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
  233. {
  234. u32 flash_id;
  235. if (col < 4) {
  236. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
  237. flash_id >>= (3 - col) * 8;
  238. } else {
  239. flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
  240. flash_id >>= 24;
  241. }
  242. return flash_id & 0xff;
  243. }
  244. static u8 vf610_nfc_get_status(struct mtd_info *mtd)
  245. {
  246. return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
  247. }
  248. /* Single command */
  249. static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
  250. u32 cmd_code)
  251. {
  252. void __iomem *reg = regbase + NFC_FLASH_CMD2;
  253. u32 tmp;
  254. vf610_nfc_clear_status(regbase);
  255. tmp = __raw_readl(reg);
  256. tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
  257. tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
  258. tmp |= cmd_code << CMD_CODE_SHIFT;
  259. __raw_writel(tmp, reg);
  260. }
  261. /* Two commands */
  262. static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
  263. u32 cmd_byte2, u32 cmd_code)
  264. {
  265. void __iomem *reg = regbase + NFC_FLASH_CMD1;
  266. u32 tmp;
  267. vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
  268. tmp = __raw_readl(reg);
  269. tmp &= ~CMD_BYTE2_MASK;
  270. tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
  271. __raw_writel(tmp, reg);
  272. }
  273. static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
  274. {
  275. if (column != -1) {
  276. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  277. if (nfc->chip.options & NAND_BUSWIDTH_16)
  278. column = column / 2;
  279. vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
  280. COL_ADDR_SHIFT, column);
  281. }
  282. if (page != -1)
  283. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  284. ROW_ADDR_SHIFT, page);
  285. }
  286. static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
  287. {
  288. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  289. CONFIG_ECC_MODE_MASK,
  290. CONFIG_ECC_MODE_SHIFT, ecc_mode);
  291. }
  292. static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
  293. {
  294. __raw_writel(size, regbase + NFC_SECTOR_SIZE);
  295. }
  296. /* Send command to NAND chip */
  297. static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
  298. int column, int page)
  299. {
  300. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  301. int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
  302. nfc->buf_offset = max(column, 0);
  303. nfc->alt_buf = ALT_BUF_DATA;
  304. switch (command) {
  305. case NAND_CMD_SEQIN:
  306. /* Use valid column/page from preread... */
  307. vf610_nfc_addr_cycle(mtd, column, page);
  308. nfc->buf_offset = 0;
  309. /*
  310. * SEQIN => data => PAGEPROG sequence is done by the controller
  311. * hence we do not need to issue the command here...
  312. */
  313. return;
  314. case NAND_CMD_PAGEPROG:
  315. trfr_sz += nfc->write_sz;
  316. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  317. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  318. vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
  319. command, PROGRAM_PAGE_CMD_CODE);
  320. break;
  321. case NAND_CMD_RESET:
  322. vf610_nfc_transfer_size(nfc->regs, 0);
  323. vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
  324. break;
  325. case NAND_CMD_READOOB:
  326. trfr_sz += mtd->oobsize;
  327. column = mtd->writesize;
  328. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  329. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  330. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  331. vf610_nfc_addr_cycle(mtd, column, page);
  332. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  333. break;
  334. case NAND_CMD_READ0:
  335. trfr_sz += mtd->writesize + mtd->oobsize;
  336. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  337. vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
  338. vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
  339. NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
  340. vf610_nfc_addr_cycle(mtd, column, page);
  341. break;
  342. case NAND_CMD_PARAM:
  343. nfc->alt_buf = ALT_BUF_ONFI;
  344. trfr_sz = 3 * sizeof(struct nand_onfi_params);
  345. vf610_nfc_transfer_size(nfc->regs, trfr_sz);
  346. vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
  347. READ_ONFI_PARAM_CMD_CODE);
  348. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  349. ROW_ADDR_SHIFT, column);
  350. vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
  351. break;
  352. case NAND_CMD_ERASE1:
  353. vf610_nfc_transfer_size(nfc->regs, 0);
  354. vf610_nfc_send_commands(nfc->regs, command,
  355. NAND_CMD_ERASE2, ERASE_CMD_CODE);
  356. vf610_nfc_addr_cycle(mtd, column, page);
  357. break;
  358. case NAND_CMD_READID:
  359. nfc->alt_buf = ALT_BUF_ID;
  360. nfc->buf_offset = 0;
  361. vf610_nfc_transfer_size(nfc->regs, 0);
  362. vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
  363. vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
  364. ROW_ADDR_SHIFT, column);
  365. break;
  366. case NAND_CMD_STATUS:
  367. nfc->alt_buf = ALT_BUF_STAT;
  368. vf610_nfc_transfer_size(nfc->regs, 0);
  369. vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
  370. break;
  371. default:
  372. return;
  373. }
  374. vf610_nfc_done(mtd);
  375. nfc->write_sz = 0;
  376. }
  377. /* Read data from NFC buffers */
  378. static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  379. {
  380. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  381. uint c = nfc->buf_offset;
  382. /* Alternate buffers are only supported through read_byte */
  383. if (nfc->alt_buf)
  384. return;
  385. vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
  386. nfc->buf_offset += len;
  387. }
  388. /* Write data to NFC buffers */
  389. static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  390. int len)
  391. {
  392. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  393. uint c = nfc->buf_offset;
  394. uint l;
  395. l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
  396. vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
  397. nfc->write_sz += l;
  398. nfc->buf_offset += l;
  399. }
  400. /* Read byte from NFC buffers */
  401. static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
  402. {
  403. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  404. u8 tmp;
  405. uint c = nfc->buf_offset;
  406. switch (nfc->alt_buf) {
  407. case ALT_BUF_ID:
  408. tmp = vf610_nfc_get_id(mtd, c);
  409. break;
  410. case ALT_BUF_STAT:
  411. tmp = vf610_nfc_get_status(mtd);
  412. break;
  413. #ifdef __LITTLE_ENDIAN
  414. case ALT_BUF_ONFI:
  415. /* Reverse byte since the controller uses big endianness */
  416. c = nfc->buf_offset ^ 0x3;
  417. /* fall-through */
  418. #endif
  419. default:
  420. tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
  421. break;
  422. }
  423. nfc->buf_offset++;
  424. return tmp;
  425. }
  426. /* Read word from NFC buffers */
  427. static u16 vf610_nfc_read_word(struct mtd_info *mtd)
  428. {
  429. u16 tmp;
  430. vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
  431. return tmp;
  432. }
  433. /* If not provided, upper layers apply a fixed delay. */
  434. static int vf610_nfc_dev_ready(struct mtd_info *mtd)
  435. {
  436. /* NFC handles R/B internally; always ready. */
  437. return 1;
  438. }
  439. /*
  440. * This function supports Vybrid only (MPC5125 would have full RB and four CS)
  441. */
  442. static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
  443. {
  444. #ifdef CONFIG_VF610
  445. u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
  446. tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
  447. if (chip >= 0) {
  448. tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
  449. tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
  450. }
  451. vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
  452. #endif
  453. }
  454. /* Count the number of 0's in buff upto max_bits */
  455. static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
  456. {
  457. uint32_t *buff32 = (uint32_t *)buff;
  458. int k, written_bits = 0;
  459. for (k = 0; k < (size / 4); k++) {
  460. written_bits += hweight32(~buff32[k]);
  461. if (written_bits > max_bits)
  462. break;
  463. }
  464. return written_bits;
  465. }
  466. static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
  467. uint8_t *oob, int page)
  468. {
  469. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  470. u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
  471. u8 ecc_status;
  472. u8 ecc_count;
  473. int flips;
  474. int flips_threshold = nfc->chip.ecc.strength / 2;
  475. ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
  476. ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
  477. if (!(ecc_status & ECC_STATUS_MASK))
  478. return ecc_count;
  479. /* Read OOB without ECC unit enabled */
  480. vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
  481. vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
  482. /*
  483. * On an erased page, bit count (including OOB) should be zero or
  484. * at least less then half of the ECC strength.
  485. */
  486. flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
  487. flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
  488. if (unlikely(flips > flips_threshold))
  489. return -EINVAL;
  490. /* Erased page. */
  491. memset(dat, 0xff, nfc->chip.ecc.size);
  492. memset(oob, 0xff, mtd->oobsize);
  493. return flips;
  494. }
  495. static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  496. uint8_t *buf, int oob_required, int page)
  497. {
  498. int eccsize = chip->ecc.size;
  499. int stat;
  500. vf610_nfc_read_buf(mtd, buf, eccsize);
  501. if (oob_required)
  502. vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  503. stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
  504. if (stat < 0) {
  505. mtd->ecc_stats.failed++;
  506. return 0;
  507. } else {
  508. mtd->ecc_stats.corrected += stat;
  509. return stat;
  510. }
  511. }
  512. /*
  513. * ECC will be calculated automatically
  514. */
  515. static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  516. const uint8_t *buf, int oob_required, int page)
  517. {
  518. struct vf610_nfc *nfc = mtd_to_nfc(mtd);
  519. vf610_nfc_write_buf(mtd, buf, mtd->writesize);
  520. if (oob_required)
  521. vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  522. /* Always write whole page including OOB due to HW ECC */
  523. nfc->write_sz = mtd->writesize + mtd->oobsize;
  524. return 0;
  525. }
  526. struct vf610_nfc_config {
  527. int hardware_ecc;
  528. int width;
  529. int flash_bbt;
  530. };
  531. static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
  532. {
  533. struct mtd_info *mtd;
  534. struct nand_chip *chip;
  535. struct vf610_nfc *nfc;
  536. int err = 0;
  537. struct vf610_nfc_config cfg = {
  538. .hardware_ecc = 1,
  539. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  540. .width = 16,
  541. #else
  542. .width = 8,
  543. #endif
  544. .flash_bbt = 1,
  545. };
  546. nfc = malloc(sizeof(*nfc));
  547. if (!nfc) {
  548. printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
  549. return -ENOMEM;
  550. }
  551. chip = &nfc->chip;
  552. nfc->regs = addr;
  553. mtd = nand_to_mtd(chip);
  554. nand_set_controller_data(chip, nfc);
  555. if (cfg.width == 16)
  556. chip->options |= NAND_BUSWIDTH_16;
  557. chip->dev_ready = vf610_nfc_dev_ready;
  558. chip->cmdfunc = vf610_nfc_command;
  559. chip->read_byte = vf610_nfc_read_byte;
  560. chip->read_word = vf610_nfc_read_word;
  561. chip->read_buf = vf610_nfc_read_buf;
  562. chip->write_buf = vf610_nfc_write_buf;
  563. chip->select_chip = vf610_nfc_select_chip;
  564. chip->options |= NAND_NO_SUBPAGE_WRITE;
  565. chip->ecc.size = PAGE_2K;
  566. /* Set configuration register. */
  567. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  568. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
  569. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
  570. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
  571. vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
  572. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
  573. /* Disable virtual pages, only one elementary transfer unit */
  574. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
  575. CONFIG_PAGE_CNT_SHIFT, 1);
  576. /* first scan to find the device and get the page size */
  577. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
  578. err = -ENXIO;
  579. goto error;
  580. }
  581. if (cfg.width == 16)
  582. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
  583. /* Bad block options. */
  584. if (cfg.flash_bbt)
  585. chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
  586. NAND_BBT_CREATE;
  587. /* Single buffer only, max 256 OOB minus ECC status */
  588. if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
  589. dev_err(nfc->dev, "Unsupported flash page size\n");
  590. err = -ENXIO;
  591. goto error;
  592. }
  593. if (cfg.hardware_ecc) {
  594. if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
  595. dev_err(nfc->dev, "Unsupported flash with hwecc\n");
  596. err = -ENXIO;
  597. goto error;
  598. }
  599. if (chip->ecc.size != mtd->writesize) {
  600. dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
  601. dev_err(nfc->dev, "Step size needs to be page size\n");
  602. err = -ENXIO;
  603. goto error;
  604. }
  605. /* Current HW ECC layouts only use 64 bytes of OOB */
  606. if (mtd->oobsize > 64)
  607. mtd->oobsize = 64;
  608. /* propagate ecc.layout to mtd_info */
  609. mtd->ecclayout = chip->ecc.layout;
  610. chip->ecc.read_page = vf610_nfc_read_page;
  611. chip->ecc.write_page = vf610_nfc_write_page;
  612. chip->ecc.mode = NAND_ECC_HW;
  613. chip->ecc.size = PAGE_2K;
  614. chip->ecc.layout = &vf610_nfc_ecc;
  615. #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
  616. chip->ecc.strength = 24;
  617. chip->ecc.bytes = 45;
  618. #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
  619. chip->ecc.strength = 32;
  620. chip->ecc.bytes = 60;
  621. #endif
  622. /* Set ECC_STATUS offset */
  623. vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
  624. CONFIG_ECC_SRAM_ADDR_MASK,
  625. CONFIG_ECC_SRAM_ADDR_SHIFT,
  626. ECC_SRAM_ADDR >> 3);
  627. /* Enable ECC status in SRAM */
  628. vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
  629. }
  630. /* second phase scan */
  631. err = nand_scan_tail(mtd);
  632. if (err)
  633. return err;
  634. err = nand_register(devnum, mtd);
  635. if (err)
  636. return err;
  637. return 0;
  638. error:
  639. return err;
  640. }
  641. void board_nand_init(void)
  642. {
  643. int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
  644. if (err)
  645. printf("VF610 NAND init failed (err %d)\n", err);
  646. }