tegra_nand.h 7.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
  4. */
  5. /* register offset */
  6. #define COMMAND_0 0x00
  7. #define CMD_GO (1 << 31)
  8. #define CMD_CLE (1 << 30)
  9. #define CMD_ALE (1 << 29)
  10. #define CMD_PIO (1 << 28)
  11. #define CMD_TX (1 << 27)
  12. #define CMD_RX (1 << 26)
  13. #define CMD_SEC_CMD (1 << 25)
  14. #define CMD_AFT_DAT_MASK (1 << 24)
  15. #define CMD_AFT_DAT_DISABLE 0
  16. #define CMD_AFT_DAT_ENABLE (1 << 24)
  17. #define CMD_TRANS_SIZE_SHIFT 20
  18. #define CMD_TRANS_SIZE_PAGE 8
  19. #define CMD_A_VALID (1 << 19)
  20. #define CMD_B_VALID (1 << 18)
  21. #define CMD_RD_STATUS_CHK (1 << 17)
  22. #define CMD_R_BSY_CHK (1 << 16)
  23. #define CMD_CE7 (1 << 15)
  24. #define CMD_CE6 (1 << 14)
  25. #define CMD_CE5 (1 << 13)
  26. #define CMD_CE4 (1 << 12)
  27. #define CMD_CE3 (1 << 11)
  28. #define CMD_CE2 (1 << 10)
  29. #define CMD_CE1 (1 << 9)
  30. #define CMD_CE0 (1 << 8)
  31. #define CMD_CLE_BYTE_SIZE_SHIFT 4
  32. enum {
  33. CMD_CLE_BYTES1 = 0,
  34. CMD_CLE_BYTES2,
  35. CMD_CLE_BYTES3,
  36. CMD_CLE_BYTES4,
  37. };
  38. #define CMD_ALE_BYTE_SIZE_SHIFT 0
  39. enum {
  40. CMD_ALE_BYTES1 = 0,
  41. CMD_ALE_BYTES2,
  42. CMD_ALE_BYTES3,
  43. CMD_ALE_BYTES4,
  44. CMD_ALE_BYTES5,
  45. CMD_ALE_BYTES6,
  46. CMD_ALE_BYTES7,
  47. CMD_ALE_BYTES8
  48. };
  49. #define STATUS_0 0x04
  50. #define STATUS_RBSY0 (1 << 8)
  51. #define ISR_0 0x08
  52. #define ISR_IS_CMD_DONE (1 << 5)
  53. #define ISR_IS_ECC_ERR (1 << 4)
  54. #define IER_0 0x0C
  55. #define CFG_0 0x10
  56. #define CFG_HW_ECC_MASK (1 << 31)
  57. #define CFG_HW_ECC_DISABLE 0
  58. #define CFG_HW_ECC_ENABLE (1 << 31)
  59. #define CFG_HW_ECC_SEL_MASK (1 << 30)
  60. #define CFG_HW_ECC_SEL_HAMMING 0
  61. #define CFG_HW_ECC_SEL_RS (1 << 30)
  62. #define CFG_HW_ECC_CORRECTION_MASK (1 << 29)
  63. #define CFG_HW_ECC_CORRECTION_DISABLE 0
  64. #define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29)
  65. #define CFG_PIPELINE_EN_MASK (1 << 28)
  66. #define CFG_PIPELINE_EN_DISABLE 0
  67. #define CFG_PIPELINE_EN_ENABLE (1 << 28)
  68. #define CFG_ECC_EN_TAG_MASK (1 << 27)
  69. #define CFG_ECC_EN_TAG_DISABLE 0
  70. #define CFG_ECC_EN_TAG_ENABLE (1 << 27)
  71. #define CFG_TVALUE_MASK (3 << 24)
  72. enum {
  73. CFG_TVAL4 = 0 << 24,
  74. CFG_TVAL6 = 1 << 24,
  75. CFG_TVAL8 = 2 << 24
  76. };
  77. #define CFG_SKIP_SPARE_MASK (1 << 23)
  78. #define CFG_SKIP_SPARE_DISABLE 0
  79. #define CFG_SKIP_SPARE_ENABLE (1 << 23)
  80. #define CFG_COM_BSY_MASK (1 << 22)
  81. #define CFG_COM_BSY_DISABLE 0
  82. #define CFG_COM_BSY_ENABLE (1 << 22)
  83. #define CFG_BUS_WIDTH_MASK (1 << 21)
  84. #define CFG_BUS_WIDTH_8BIT 0
  85. #define CFG_BUS_WIDTH_16BIT (1 << 21)
  86. #define CFG_LPDDR1_MODE_MASK (1 << 20)
  87. #define CFG_LPDDR1_MODE_DISABLE 0
  88. #define CFG_LPDDR1_MODE_ENABLE (1 << 20)
  89. #define CFG_EDO_MODE_MASK (1 << 19)
  90. #define CFG_EDO_MODE_DISABLE 0
  91. #define CFG_EDO_MODE_ENABLE (1 << 19)
  92. #define CFG_PAGE_SIZE_SEL_MASK (7 << 16)
  93. enum {
  94. CFG_PAGE_SIZE_256 = 0 << 16,
  95. CFG_PAGE_SIZE_512 = 1 << 16,
  96. CFG_PAGE_SIZE_1024 = 2 << 16,
  97. CFG_PAGE_SIZE_2048 = 3 << 16,
  98. CFG_PAGE_SIZE_4096 = 4 << 16
  99. };
  100. #define CFG_SKIP_SPARE_SEL_MASK (3 << 14)
  101. enum {
  102. CFG_SKIP_SPARE_SEL_4 = 0 << 14,
  103. CFG_SKIP_SPARE_SEL_8 = 1 << 14,
  104. CFG_SKIP_SPARE_SEL_12 = 2 << 14,
  105. CFG_SKIP_SPARE_SEL_16 = 3 << 14
  106. };
  107. #define CFG_TAG_BYTE_SIZE_MASK 0x1FF
  108. #define TIMING_0 0x14
  109. #define TIMING_TRP_RESP_CNT_SHIFT 28
  110. #define TIMING_TRP_RESP_CNT_MASK (0xf << TIMING_TRP_RESP_CNT_SHIFT)
  111. #define TIMING_TWB_CNT_SHIFT 24
  112. #define TIMING_TWB_CNT_MASK (0xf << TIMING_TWB_CNT_SHIFT)
  113. #define TIMING_TCR_TAR_TRR_CNT_SHIFT 20
  114. #define TIMING_TCR_TAR_TRR_CNT_MASK (0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT)
  115. #define TIMING_TWHR_CNT_SHIFT 16
  116. #define TIMING_TWHR_CNT_MASK (0xf << TIMING_TWHR_CNT_SHIFT)
  117. #define TIMING_TCS_CNT_SHIFT 14
  118. #define TIMING_TCS_CNT_MASK (3 << TIMING_TCS_CNT_SHIFT)
  119. #define TIMING_TWH_CNT_SHIFT 12
  120. #define TIMING_TWH_CNT_MASK (3 << TIMING_TWH_CNT_SHIFT)
  121. #define TIMING_TWP_CNT_SHIFT 8
  122. #define TIMING_TWP_CNT_MASK (0xf << TIMING_TWP_CNT_SHIFT)
  123. #define TIMING_TRH_CNT_SHIFT 4
  124. #define TIMING_TRH_CNT_MASK (3 << TIMING_TRH_CNT_SHIFT)
  125. #define TIMING_TRP_CNT_SHIFT 0
  126. #define TIMING_TRP_CNT_MASK (0xf << TIMING_TRP_CNT_SHIFT)
  127. #define RESP_0 0x18
  128. #define TIMING2_0 0x1C
  129. #define TIMING2_TADL_CNT_SHIFT 0
  130. #define TIMING2_TADL_CNT_MASK (0xf << TIMING2_TADL_CNT_SHIFT)
  131. #define CMD_REG1_0 0x20
  132. #define CMD_REG2_0 0x24
  133. #define ADDR_REG1_0 0x28
  134. #define ADDR_REG2_0 0x2C
  135. #define DMA_MST_CTRL_0 0x30
  136. #define DMA_MST_CTRL_GO_MASK (1 << 31)
  137. #define DMA_MST_CTRL_GO_DISABLE 0
  138. #define DMA_MST_CTRL_GO_ENABLE (1 << 31)
  139. #define DMA_MST_CTRL_DIR_MASK (1 << 30)
  140. #define DMA_MST_CTRL_DIR_READ 0
  141. #define DMA_MST_CTRL_DIR_WRITE (1 << 30)
  142. #define DMA_MST_CTRL_PERF_EN_MASK (1 << 29)
  143. #define DMA_MST_CTRL_PERF_EN_DISABLE 0
  144. #define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29)
  145. #define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27)
  146. #define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0
  147. #define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27)
  148. #define DMA_MST_CTRL_BURST_SIZE_SHIFT 24
  149. #define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT)
  150. enum {
  151. DMA_MST_CTRL_BURST_1WORDS = 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
  152. DMA_MST_CTRL_BURST_4WORDS = 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
  153. DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
  154. DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT
  155. };
  156. #define DMA_MST_CTRL_IS_DMA_DONE (1 << 20)
  157. #define DMA_MST_CTRL_EN_A_MASK (1 << 2)
  158. #define DMA_MST_CTRL_EN_A_DISABLE 0
  159. #define DMA_MST_CTRL_EN_A_ENABLE (1 << 2)
  160. #define DMA_MST_CTRL_EN_B_MASK (1 << 1)
  161. #define DMA_MST_CTRL_EN_B_DISABLE 0
  162. #define DMA_MST_CTRL_EN_B_ENABLE (1 << 1)
  163. #define DMA_CFG_A_0 0x34
  164. #define DMA_CFG_B_0 0x38
  165. #define FIFO_CTRL_0 0x3C
  166. #define DATA_BLOCK_PTR_0 0x40
  167. #define TAG_PTR_0 0x44
  168. #define ECC_PTR_0 0x48
  169. #define DEC_STATUS_0 0x4C
  170. #define DEC_STATUS_A_ECC_FAIL (1 << 1)
  171. #define DEC_STATUS_B_ECC_FAIL (1 << 0)
  172. #define BCH_CONFIG_0 0xCC
  173. #define BCH_CONFIG_BCH_TVALUE_SHIFT 4
  174. #define BCH_CONFIG_BCH_TVALUE_MASK (3 << BCH_CONFIG_BCH_TVALUE_SHIFT)
  175. enum {
  176. BCH_CONFIG_BCH_TVAL4 = 0 << BCH_CONFIG_BCH_TVALUE_SHIFT,
  177. BCH_CONFIG_BCH_TVAL8 = 1 << BCH_CONFIG_BCH_TVALUE_SHIFT,
  178. BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT,
  179. BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT
  180. };
  181. #define BCH_CONFIG_BCH_ECC_MASK (1 << 0)
  182. #define BCH_CONFIG_BCH_ECC_DISABLE 0
  183. #define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0)
  184. #define BCH_DEC_RESULT_0 0xD0
  185. #define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8)
  186. #define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF
  187. #define BCH_DEC_STATUS_BUF_0 0xD4
  188. #define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000
  189. #define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000
  190. #define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14)
  191. #define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13)
  192. #define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8)
  193. #define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF
  194. #define LP_OPTIONS 0
  195. struct nand_ctlr {
  196. u32 command; /* offset 00h */
  197. u32 status; /* offset 04h */
  198. u32 isr; /* offset 08h */
  199. u32 ier; /* offset 0Ch */
  200. u32 config; /* offset 10h */
  201. u32 timing; /* offset 14h */
  202. u32 resp; /* offset 18h */
  203. u32 timing2; /* offset 1Ch */
  204. u32 cmd_reg1; /* offset 20h */
  205. u32 cmd_reg2; /* offset 24h */
  206. u32 addr_reg1; /* offset 28h */
  207. u32 addr_reg2; /* offset 2Ch */
  208. u32 dma_mst_ctrl; /* offset 30h */
  209. u32 dma_cfg_a; /* offset 34h */
  210. u32 dma_cfg_b; /* offset 38h */
  211. u32 fifo_ctrl; /* offset 3Ch */
  212. u32 data_block_ptr; /* offset 40h */
  213. u32 tag_ptr; /* offset 44h */
  214. u32 resv1; /* offset 48h */
  215. u32 dec_status; /* offset 4Ch */
  216. u32 hwstatus_cmd; /* offset 50h */
  217. u32 hwstatus_mask; /* offset 54h */
  218. u32 resv2[29];
  219. u32 bch_config; /* offset CCh */
  220. u32 bch_dec_result; /* offset D0h */
  221. u32 bch_dec_status_buf;
  222. /* offset D4h */
  223. };