sunxi_nand.c 47 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
  4. * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com>
  5. *
  6. * Derived from:
  7. * https://github.com/yuq/sunxi-nfc-mtd
  8. * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
  9. *
  10. * https://github.com/hno/Allwinner-Info
  11. * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  12. *
  13. * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  14. * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. */
  26. #include <common.h>
  27. #include <fdtdec.h>
  28. #include <memalign.h>
  29. #include <nand.h>
  30. #include <linux/kernel.h>
  31. #include <linux/mtd/mtd.h>
  32. #include <linux/mtd/rawnand.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/io.h>
  35. #include <asm/gpio.h>
  36. #include <asm/arch/clock.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define NFC_REG_CTL 0x0000
  39. #define NFC_REG_ST 0x0004
  40. #define NFC_REG_INT 0x0008
  41. #define NFC_REG_TIMING_CTL 0x000C
  42. #define NFC_REG_TIMING_CFG 0x0010
  43. #define NFC_REG_ADDR_LOW 0x0014
  44. #define NFC_REG_ADDR_HIGH 0x0018
  45. #define NFC_REG_SECTOR_NUM 0x001C
  46. #define NFC_REG_CNT 0x0020
  47. #define NFC_REG_CMD 0x0024
  48. #define NFC_REG_RCMD_SET 0x0028
  49. #define NFC_REG_WCMD_SET 0x002C
  50. #define NFC_REG_IO_DATA 0x0030
  51. #define NFC_REG_ECC_CTL 0x0034
  52. #define NFC_REG_ECC_ST 0x0038
  53. #define NFC_REG_DEBUG 0x003C
  54. #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
  55. #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
  56. #define NFC_REG_SPARE_AREA 0x00A0
  57. #define NFC_REG_PAT_ID 0x00A4
  58. #define NFC_RAM0_BASE 0x0400
  59. #define NFC_RAM1_BASE 0x0800
  60. /* define bit use in NFC_CTL */
  61. #define NFC_EN BIT(0)
  62. #define NFC_RESET BIT(1)
  63. #define NFC_BUS_WIDTH_MSK BIT(2)
  64. #define NFC_BUS_WIDTH_8 (0 << 2)
  65. #define NFC_BUS_WIDTH_16 (1 << 2)
  66. #define NFC_RB_SEL_MSK BIT(3)
  67. #define NFC_RB_SEL(x) ((x) << 3)
  68. #define NFC_CE_SEL_MSK (0x7 << 24)
  69. #define NFC_CE_SEL(x) ((x) << 24)
  70. #define NFC_CE_CTL BIT(6)
  71. #define NFC_PAGE_SHIFT_MSK (0xf << 8)
  72. #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
  73. #define NFC_SAM BIT(12)
  74. #define NFC_RAM_METHOD BIT(14)
  75. #define NFC_DEBUG_CTL BIT(31)
  76. /* define bit use in NFC_ST */
  77. #define NFC_RB_B2R BIT(0)
  78. #define NFC_CMD_INT_FLAG BIT(1)
  79. #define NFC_DMA_INT_FLAG BIT(2)
  80. #define NFC_CMD_FIFO_STATUS BIT(3)
  81. #define NFC_STA BIT(4)
  82. #define NFC_NATCH_INT_FLAG BIT(5)
  83. #define NFC_RB_STATE(x) BIT(x + 8)
  84. /* define bit use in NFC_INT */
  85. #define NFC_B2R_INT_ENABLE BIT(0)
  86. #define NFC_CMD_INT_ENABLE BIT(1)
  87. #define NFC_DMA_INT_ENABLE BIT(2)
  88. #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
  89. NFC_CMD_INT_ENABLE | \
  90. NFC_DMA_INT_ENABLE)
  91. /* define bit use in NFC_TIMING_CTL */
  92. #define NFC_TIMING_CTL_EDO BIT(8)
  93. /* define NFC_TIMING_CFG register layout */
  94. #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
  95. (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
  96. (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
  97. (((tCAD) & 0x7) << 8))
  98. /* define bit use in NFC_CMD */
  99. #define NFC_CMD_LOW_BYTE_MSK 0xff
  100. #define NFC_CMD_HIGH_BYTE_MSK (0xff << 8)
  101. #define NFC_CMD(x) (x)
  102. #define NFC_ADR_NUM_MSK (0x7 << 16)
  103. #define NFC_ADR_NUM(x) (((x) - 1) << 16)
  104. #define NFC_SEND_ADR BIT(19)
  105. #define NFC_ACCESS_DIR BIT(20)
  106. #define NFC_DATA_TRANS BIT(21)
  107. #define NFC_SEND_CMD1 BIT(22)
  108. #define NFC_WAIT_FLAG BIT(23)
  109. #define NFC_SEND_CMD2 BIT(24)
  110. #define NFC_SEQ BIT(25)
  111. #define NFC_DATA_SWAP_METHOD BIT(26)
  112. #define NFC_ROW_AUTO_INC BIT(27)
  113. #define NFC_SEND_CMD3 BIT(28)
  114. #define NFC_SEND_CMD4 BIT(29)
  115. #define NFC_CMD_TYPE_MSK (0x3 << 30)
  116. #define NFC_NORMAL_OP (0 << 30)
  117. #define NFC_ECC_OP (1 << 30)
  118. #define NFC_PAGE_OP (2 << 30)
  119. /* define bit use in NFC_RCMD_SET */
  120. #define NFC_READ_CMD_MSK 0xff
  121. #define NFC_RND_READ_CMD0_MSK (0xff << 8)
  122. #define NFC_RND_READ_CMD1_MSK (0xff << 16)
  123. /* define bit use in NFC_WCMD_SET */
  124. #define NFC_PROGRAM_CMD_MSK 0xff
  125. #define NFC_RND_WRITE_CMD_MSK (0xff << 8)
  126. #define NFC_READ_CMD0_MSK (0xff << 16)
  127. #define NFC_READ_CMD1_MSK (0xff << 24)
  128. /* define bit use in NFC_ECC_CTL */
  129. #define NFC_ECC_EN BIT(0)
  130. #define NFC_ECC_PIPELINE BIT(3)
  131. #define NFC_ECC_EXCEPTION BIT(4)
  132. #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
  133. #define NFC_ECC_BLOCK_512 (1 << 5)
  134. #define NFC_RANDOM_EN BIT(9)
  135. #define NFC_RANDOM_DIRECTION BIT(10)
  136. #define NFC_ECC_MODE_MSK (0xf << 12)
  137. #define NFC_ECC_MODE(x) ((x) << 12)
  138. #define NFC_RANDOM_SEED_MSK (0x7fff << 16)
  139. #define NFC_RANDOM_SEED(x) ((x) << 16)
  140. /* define bit use in NFC_ECC_ST */
  141. #define NFC_ECC_ERR(x) BIT(x)
  142. #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
  143. #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
  144. #define NFC_DEFAULT_TIMEOUT_MS 1000
  145. #define NFC_SRAM_SIZE 1024
  146. #define NFC_MAX_CS 7
  147. /*
  148. * Ready/Busy detection type: describes the Ready/Busy detection modes
  149. *
  150. * @RB_NONE: no external detection available, rely on STATUS command
  151. * and software timeouts
  152. * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
  153. * pin of the NAND flash chip must be connected to one of the
  154. * native NAND R/B pins (those which can be muxed to the NAND
  155. * Controller)
  156. * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
  157. * pin of the NAND flash chip must be connected to a GPIO capable
  158. * pin.
  159. */
  160. enum sunxi_nand_rb_type {
  161. RB_NONE,
  162. RB_NATIVE,
  163. RB_GPIO,
  164. };
  165. /*
  166. * Ready/Busy structure: stores information related to Ready/Busy detection
  167. *
  168. * @type: the Ready/Busy detection mode
  169. * @info: information related to the R/B detection mode. Either a gpio
  170. * id or a native R/B id (those supported by the NAND controller).
  171. */
  172. struct sunxi_nand_rb {
  173. enum sunxi_nand_rb_type type;
  174. union {
  175. struct gpio_desc gpio;
  176. int nativeid;
  177. } info;
  178. };
  179. /*
  180. * Chip Select structure: stores information related to NAND Chip Select
  181. *
  182. * @cs: the NAND CS id used to communicate with a NAND Chip
  183. * @rb: the Ready/Busy description
  184. */
  185. struct sunxi_nand_chip_sel {
  186. u8 cs;
  187. struct sunxi_nand_rb rb;
  188. };
  189. /*
  190. * sunxi HW ECC infos: stores information related to HW ECC support
  191. *
  192. * @mode: the sunxi ECC mode field deduced from ECC requirements
  193. * @layout: the OOB layout depending on the ECC requirements and the
  194. * selected ECC mode
  195. */
  196. struct sunxi_nand_hw_ecc {
  197. int mode;
  198. struct nand_ecclayout layout;
  199. };
  200. /*
  201. * NAND chip structure: stores NAND chip device related information
  202. *
  203. * @node: used to store NAND chips into a list
  204. * @nand: base NAND chip structure
  205. * @mtd: base MTD structure
  206. * @clk_rate: clk_rate required for this NAND chip
  207. * @timing_cfg TIMING_CFG register value for this NAND chip
  208. * @selected: current active CS
  209. * @nsels: number of CS lines required by the NAND chip
  210. * @sels: array of CS lines descriptions
  211. */
  212. struct sunxi_nand_chip {
  213. struct list_head node;
  214. struct nand_chip nand;
  215. unsigned long clk_rate;
  216. u32 timing_cfg;
  217. u32 timing_ctl;
  218. int selected;
  219. int addr_cycles;
  220. u32 addr[2];
  221. int cmd_cycles;
  222. u8 cmd[2];
  223. int nsels;
  224. struct sunxi_nand_chip_sel sels[0];
  225. };
  226. static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
  227. {
  228. return container_of(nand, struct sunxi_nand_chip, nand);
  229. }
  230. /*
  231. * NAND Controller structure: stores sunxi NAND controller information
  232. *
  233. * @controller: base controller structure
  234. * @dev: parent device (used to print error messages)
  235. * @regs: NAND controller registers
  236. * @ahb_clk: NAND Controller AHB clock
  237. * @mod_clk: NAND Controller mod clock
  238. * @assigned_cs: bitmask describing already assigned CS lines
  239. * @clk_rate: NAND controller current clock rate
  240. * @chips: a list containing all the NAND chips attached to
  241. * this NAND controller
  242. * @complete: a completion object used to wait for NAND
  243. * controller events
  244. */
  245. struct sunxi_nfc {
  246. struct nand_hw_control controller;
  247. struct device *dev;
  248. void __iomem *regs;
  249. struct clk *ahb_clk;
  250. struct clk *mod_clk;
  251. unsigned long assigned_cs;
  252. unsigned long clk_rate;
  253. struct list_head chips;
  254. };
  255. static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
  256. {
  257. return container_of(ctrl, struct sunxi_nfc, controller);
  258. }
  259. static void sunxi_nfc_set_clk_rate(unsigned long hz)
  260. {
  261. struct sunxi_ccm_reg *const ccm =
  262. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  263. int div_m, div_n;
  264. div_m = (clock_get_pll6() + hz - 1) / hz;
  265. for (div_n = 0; div_n < 3 && div_m > 16; div_n++) {
  266. if (div_m % 2)
  267. div_m++;
  268. div_m >>= 1;
  269. }
  270. if (div_m > 16)
  271. div_m = 16;
  272. /* config mod clock */
  273. writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 |
  274. CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m),
  275. &ccm->nand0_clk_cfg);
  276. /* gate on nand clock */
  277. setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
  278. #ifdef CONFIG_MACH_SUN9I
  279. setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
  280. #else
  281. setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
  282. #endif
  283. }
  284. static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
  285. unsigned int timeout_ms)
  286. {
  287. unsigned int timeout_ticks;
  288. u32 time_start, status;
  289. int ret = -ETIMEDOUT;
  290. if (!timeout_ms)
  291. timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
  292. timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000;
  293. time_start = get_timer(0);
  294. do {
  295. status = readl(nfc->regs + NFC_REG_ST);
  296. if ((status & flags) == flags) {
  297. ret = 0;
  298. break;
  299. }
  300. udelay(1);
  301. } while (get_timer(time_start) < timeout_ticks);
  302. writel(status & flags, nfc->regs + NFC_REG_ST);
  303. return ret;
  304. }
  305. static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
  306. {
  307. unsigned long timeout = (CONFIG_SYS_HZ *
  308. NFC_DEFAULT_TIMEOUT_MS) / 1000;
  309. u32 time_start;
  310. time_start = get_timer(0);
  311. do {
  312. if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
  313. return 0;
  314. } while (get_timer(time_start) < timeout);
  315. dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
  316. return -ETIMEDOUT;
  317. }
  318. static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
  319. {
  320. unsigned long timeout = (CONFIG_SYS_HZ *
  321. NFC_DEFAULT_TIMEOUT_MS) / 1000;
  322. u32 time_start;
  323. writel(0, nfc->regs + NFC_REG_ECC_CTL);
  324. writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
  325. time_start = get_timer(0);
  326. do {
  327. if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
  328. return 0;
  329. } while (get_timer(time_start) < timeout);
  330. dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
  331. return -ETIMEDOUT;
  332. }
  333. static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
  334. {
  335. struct nand_chip *nand = mtd_to_nand(mtd);
  336. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  337. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  338. struct sunxi_nand_rb *rb;
  339. unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
  340. int ret;
  341. if (sunxi_nand->selected < 0)
  342. return 0;
  343. rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
  344. switch (rb->type) {
  345. case RB_NATIVE:
  346. ret = !!(readl(nfc->regs + NFC_REG_ST) &
  347. NFC_RB_STATE(rb->info.nativeid));
  348. if (ret)
  349. break;
  350. sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
  351. ret = !!(readl(nfc->regs + NFC_REG_ST) &
  352. NFC_RB_STATE(rb->info.nativeid));
  353. break;
  354. case RB_GPIO:
  355. ret = dm_gpio_get_value(&rb->info.gpio);
  356. break;
  357. case RB_NONE:
  358. default:
  359. ret = 0;
  360. dev_err(nfc->dev, "cannot check R/B NAND status!\n");
  361. break;
  362. }
  363. return ret;
  364. }
  365. static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
  366. {
  367. struct nand_chip *nand = mtd_to_nand(mtd);
  368. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  369. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  370. struct sunxi_nand_chip_sel *sel;
  371. u32 ctl;
  372. if (chip > 0 && chip >= sunxi_nand->nsels)
  373. return;
  374. if (chip == sunxi_nand->selected)
  375. return;
  376. ctl = readl(nfc->regs + NFC_REG_CTL) &
  377. ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
  378. if (chip >= 0) {
  379. sel = &sunxi_nand->sels[chip];
  380. ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
  381. NFC_PAGE_SHIFT(nand->page_shift - 10);
  382. if (sel->rb.type == RB_NONE) {
  383. nand->dev_ready = NULL;
  384. } else {
  385. nand->dev_ready = sunxi_nfc_dev_ready;
  386. if (sel->rb.type == RB_NATIVE)
  387. ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
  388. }
  389. writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
  390. if (nfc->clk_rate != sunxi_nand->clk_rate) {
  391. sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate);
  392. nfc->clk_rate = sunxi_nand->clk_rate;
  393. }
  394. }
  395. writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
  396. writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
  397. writel(ctl, nfc->regs + NFC_REG_CTL);
  398. sunxi_nand->selected = chip;
  399. }
  400. static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  401. {
  402. struct nand_chip *nand = mtd_to_nand(mtd);
  403. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  404. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  405. int ret;
  406. int cnt;
  407. int offs = 0;
  408. u32 tmp;
  409. while (len > offs) {
  410. cnt = min(len - offs, NFC_SRAM_SIZE);
  411. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  412. if (ret)
  413. break;
  414. writel(cnt, nfc->regs + NFC_REG_CNT);
  415. tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
  416. writel(tmp, nfc->regs + NFC_REG_CMD);
  417. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  418. if (ret)
  419. break;
  420. if (buf)
  421. memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
  422. cnt);
  423. offs += cnt;
  424. }
  425. }
  426. static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  427. int len)
  428. {
  429. struct nand_chip *nand = mtd_to_nand(mtd);
  430. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  431. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  432. int ret;
  433. int cnt;
  434. int offs = 0;
  435. u32 tmp;
  436. while (len > offs) {
  437. cnt = min(len - offs, NFC_SRAM_SIZE);
  438. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  439. if (ret)
  440. break;
  441. writel(cnt, nfc->regs + NFC_REG_CNT);
  442. memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
  443. tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
  444. NFC_ACCESS_DIR;
  445. writel(tmp, nfc->regs + NFC_REG_CMD);
  446. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  447. if (ret)
  448. break;
  449. offs += cnt;
  450. }
  451. }
  452. static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
  453. {
  454. uint8_t ret;
  455. sunxi_nfc_read_buf(mtd, &ret, 1);
  456. return ret;
  457. }
  458. static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
  459. unsigned int ctrl)
  460. {
  461. struct nand_chip *nand = mtd_to_nand(mtd);
  462. struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
  463. struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
  464. int ret;
  465. u32 tmp;
  466. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  467. if (ret)
  468. return;
  469. if (ctrl & NAND_CTRL_CHANGE) {
  470. tmp = readl(nfc->regs + NFC_REG_CTL);
  471. if (ctrl & NAND_NCE)
  472. tmp |= NFC_CE_CTL;
  473. else
  474. tmp &= ~NFC_CE_CTL;
  475. writel(tmp, nfc->regs + NFC_REG_CTL);
  476. }
  477. if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
  478. !(ctrl & (NAND_CLE | NAND_ALE))) {
  479. u32 cmd = 0;
  480. if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
  481. return;
  482. if (sunxi_nand->cmd_cycles--)
  483. cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
  484. if (sunxi_nand->cmd_cycles--) {
  485. cmd |= NFC_SEND_CMD2;
  486. writel(sunxi_nand->cmd[1],
  487. nfc->regs + NFC_REG_RCMD_SET);
  488. }
  489. sunxi_nand->cmd_cycles = 0;
  490. if (sunxi_nand->addr_cycles) {
  491. cmd |= NFC_SEND_ADR |
  492. NFC_ADR_NUM(sunxi_nand->addr_cycles);
  493. writel(sunxi_nand->addr[0],
  494. nfc->regs + NFC_REG_ADDR_LOW);
  495. }
  496. if (sunxi_nand->addr_cycles > 4)
  497. writel(sunxi_nand->addr[1],
  498. nfc->regs + NFC_REG_ADDR_HIGH);
  499. writel(cmd, nfc->regs + NFC_REG_CMD);
  500. sunxi_nand->addr[0] = 0;
  501. sunxi_nand->addr[1] = 0;
  502. sunxi_nand->addr_cycles = 0;
  503. sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  504. }
  505. if (ctrl & NAND_CLE) {
  506. sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
  507. } else if (ctrl & NAND_ALE) {
  508. sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
  509. dat << ((sunxi_nand->addr_cycles % 4) * 8);
  510. sunxi_nand->addr_cycles++;
  511. }
  512. }
  513. /* These seed values have been extracted from Allwinner's BSP */
  514. static const u16 sunxi_nfc_randomizer_page_seeds[] = {
  515. 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
  516. 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
  517. 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
  518. 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
  519. 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
  520. 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
  521. 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
  522. 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
  523. 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
  524. 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
  525. 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
  526. 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
  527. 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
  528. 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
  529. 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
  530. 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
  531. };
  532. /*
  533. * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds
  534. * have been generated using
  535. * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what
  536. * the randomizer engine does internally before de/scrambling OOB data.
  537. *
  538. * Those tables are statically defined to avoid calculating randomizer state
  539. * at runtime.
  540. */
  541. static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = {
  542. 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64,
  543. 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409,
  544. 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617,
  545. 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d,
  546. 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91,
  547. 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d,
  548. 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab,
  549. 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8,
  550. 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8,
  551. 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b,
  552. 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5,
  553. 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a,
  554. 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891,
  555. 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36,
  556. 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd,
  557. 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0,
  558. };
  559. static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = {
  560. 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6,
  561. 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982,
  562. 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9,
  563. 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07,
  564. 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e,
  565. 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2,
  566. 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c,
  567. 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f,
  568. 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc,
  569. 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e,
  570. 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8,
  571. 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68,
  572. 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d,
  573. 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179,
  574. 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601,
  575. 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd,
  576. };
  577. static u16 sunxi_nfc_randomizer_step(u16 state, int count)
  578. {
  579. state &= 0x7fff;
  580. /*
  581. * This loop is just a simple implementation of a Fibonacci LFSR using
  582. * the x16 + x15 + 1 polynomial.
  583. */
  584. while (count--)
  585. state = ((state >> 1) |
  586. (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff;
  587. return state;
  588. }
  589. static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
  590. {
  591. const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
  592. int mod = mtd->erasesize / mtd->writesize;
  593. if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds))
  594. mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds);
  595. if (ecc) {
  596. if (mtd->ecc_step_size == 512)
  597. seeds = sunxi_nfc_randomizer_ecc512_seeds;
  598. else
  599. seeds = sunxi_nfc_randomizer_ecc1024_seeds;
  600. }
  601. return seeds[page % mod];
  602. }
  603. static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
  604. int page, bool ecc)
  605. {
  606. struct nand_chip *nand = mtd_to_nand(mtd);
  607. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  608. u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  609. u16 state;
  610. if (!(nand->options & NAND_NEED_SCRAMBLING))
  611. return;
  612. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  613. state = sunxi_nfc_randomizer_state(mtd, page, ecc);
  614. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
  615. writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
  616. }
  617. static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
  618. {
  619. struct nand_chip *nand = mtd_to_nand(mtd);
  620. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  621. if (!(nand->options & NAND_NEED_SCRAMBLING))
  622. return;
  623. writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN,
  624. nfc->regs + NFC_REG_ECC_CTL);
  625. }
  626. static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
  627. {
  628. struct nand_chip *nand = mtd_to_nand(mtd);
  629. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  630. if (!(nand->options & NAND_NEED_SCRAMBLING))
  631. return;
  632. writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN,
  633. nfc->regs + NFC_REG_ECC_CTL);
  634. }
  635. static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
  636. {
  637. u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
  638. bbm[0] ^= state;
  639. bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
  640. }
  641. static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
  642. const uint8_t *buf, int len,
  643. bool ecc, int page)
  644. {
  645. sunxi_nfc_randomizer_config(mtd, page, ecc);
  646. sunxi_nfc_randomizer_enable(mtd);
  647. sunxi_nfc_write_buf(mtd, buf, len);
  648. sunxi_nfc_randomizer_disable(mtd);
  649. }
  650. static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
  651. int len, bool ecc, int page)
  652. {
  653. sunxi_nfc_randomizer_config(mtd, page, ecc);
  654. sunxi_nfc_randomizer_enable(mtd);
  655. sunxi_nfc_read_buf(mtd, buf, len);
  656. sunxi_nfc_randomizer_disable(mtd);
  657. }
  658. static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
  659. {
  660. struct nand_chip *nand = mtd_to_nand(mtd);
  661. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  662. struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
  663. u32 ecc_ctl;
  664. ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
  665. ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
  666. NFC_ECC_BLOCK_SIZE_MSK);
  667. ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
  668. if (nand->ecc.size == 512)
  669. ecc_ctl |= NFC_ECC_BLOCK_512;
  670. writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
  671. }
  672. static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
  673. {
  674. struct nand_chip *nand = mtd_to_nand(mtd);
  675. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  676. writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
  677. nfc->regs + NFC_REG_ECC_CTL);
  678. }
  679. static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf)
  680. {
  681. buf[0] = user_data;
  682. buf[1] = user_data >> 8;
  683. buf[2] = user_data >> 16;
  684. buf[3] = user_data >> 24;
  685. }
  686. static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
  687. u8 *data, int data_off,
  688. u8 *oob, int oob_off,
  689. int *cur_off,
  690. unsigned int *max_bitflips,
  691. bool bbm, int page)
  692. {
  693. struct nand_chip *nand = mtd_to_nand(mtd);
  694. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  695. struct nand_ecc_ctrl *ecc = &nand->ecc;
  696. int raw_mode = 0;
  697. u32 status;
  698. int ret;
  699. if (*cur_off != data_off)
  700. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
  701. sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
  702. if (data_off + ecc->size != oob_off)
  703. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  704. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  705. if (ret)
  706. return ret;
  707. sunxi_nfc_randomizer_enable(mtd);
  708. writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
  709. nfc->regs + NFC_REG_CMD);
  710. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  711. sunxi_nfc_randomizer_disable(mtd);
  712. if (ret)
  713. return ret;
  714. *cur_off = oob_off + ecc->bytes + 4;
  715. status = readl(nfc->regs + NFC_REG_ECC_ST);
  716. if (status & NFC_ECC_PAT_FOUND(0)) {
  717. u8 pattern = 0xff;
  718. if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1)))
  719. pattern = 0x0;
  720. memset(data, pattern, ecc->size);
  721. memset(oob, pattern, ecc->bytes + 4);
  722. return 1;
  723. }
  724. ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
  725. memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
  726. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  727. sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page);
  728. if (status & NFC_ECC_ERR(0)) {
  729. /*
  730. * Re-read the data with the randomizer disabled to identify
  731. * bitflips in erased pages.
  732. */
  733. if (nand->options & NAND_NEED_SCRAMBLING) {
  734. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
  735. nand->read_buf(mtd, data, ecc->size);
  736. nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
  737. nand->read_buf(mtd, oob, ecc->bytes + 4);
  738. }
  739. ret = nand_check_erased_ecc_chunk(data, ecc->size,
  740. oob, ecc->bytes + 4,
  741. NULL, 0, ecc->strength);
  742. if (ret >= 0)
  743. raw_mode = 1;
  744. } else {
  745. /*
  746. * The engine protects 4 bytes of OOB data per chunk.
  747. * Retrieve the corrected OOB bytes.
  748. */
  749. sunxi_nfc_user_data_to_buf(readl(nfc->regs +
  750. NFC_REG_USER_DATA(0)),
  751. oob);
  752. /* De-randomize the Bad Block Marker. */
  753. if (bbm && nand->options & NAND_NEED_SCRAMBLING)
  754. sunxi_nfc_randomize_bbm(mtd, page, oob);
  755. }
  756. if (ret < 0) {
  757. mtd->ecc_stats.failed++;
  758. } else {
  759. mtd->ecc_stats.corrected += ret;
  760. *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
  761. }
  762. return raw_mode;
  763. }
  764. static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
  765. u8 *oob, int *cur_off,
  766. bool randomize, int page)
  767. {
  768. struct nand_chip *nand = mtd_to_nand(mtd);
  769. struct nand_ecc_ctrl *ecc = &nand->ecc;
  770. int offset = ((ecc->bytes + 4) * ecc->steps);
  771. int len = mtd->oobsize - offset;
  772. if (len <= 0)
  773. return;
  774. if (*cur_off != offset)
  775. nand->cmdfunc(mtd, NAND_CMD_RNDOUT,
  776. offset + mtd->writesize, -1);
  777. if (!randomize)
  778. sunxi_nfc_read_buf(mtd, oob + offset, len);
  779. else
  780. sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
  781. false, page);
  782. *cur_off = mtd->oobsize + mtd->writesize;
  783. }
  784. static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
  785. {
  786. return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
  787. }
  788. static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
  789. const u8 *data, int data_off,
  790. const u8 *oob, int oob_off,
  791. int *cur_off, bool bbm,
  792. int page)
  793. {
  794. struct nand_chip *nand = mtd_to_nand(mtd);
  795. struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
  796. struct nand_ecc_ctrl *ecc = &nand->ecc;
  797. int ret;
  798. if (data_off != *cur_off)
  799. nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
  800. sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
  801. /* Fill OOB data in */
  802. if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) {
  803. u8 user_data[4];
  804. memcpy(user_data, oob, 4);
  805. sunxi_nfc_randomize_bbm(mtd, page, user_data);
  806. writel(sunxi_nfc_buf_to_user_data(user_data),
  807. nfc->regs + NFC_REG_USER_DATA(0));
  808. } else {
  809. writel(sunxi_nfc_buf_to_user_data(oob),
  810. nfc->regs + NFC_REG_USER_DATA(0));
  811. }
  812. if (data_off + ecc->size != oob_off)
  813. nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
  814. ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
  815. if (ret)
  816. return ret;
  817. sunxi_nfc_randomizer_enable(mtd);
  818. writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
  819. NFC_ACCESS_DIR | NFC_ECC_OP,
  820. nfc->regs + NFC_REG_CMD);
  821. ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
  822. sunxi_nfc_randomizer_disable(mtd);
  823. if (ret)
  824. return ret;
  825. *cur_off = oob_off + ecc->bytes + 4;
  826. return 0;
  827. }
  828. static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
  829. u8 *oob, int *cur_off,
  830. int page)
  831. {
  832. struct nand_chip *nand = mtd_to_nand(mtd);
  833. struct nand_ecc_ctrl *ecc = &nand->ecc;
  834. int offset = ((ecc->bytes + 4) * ecc->steps);
  835. int len = mtd->oobsize - offset;
  836. if (len <= 0)
  837. return;
  838. if (*cur_off != offset)
  839. nand->cmdfunc(mtd, NAND_CMD_RNDIN,
  840. offset + mtd->writesize, -1);
  841. sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
  842. *cur_off = mtd->oobsize + mtd->writesize;
  843. }
  844. static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
  845. struct nand_chip *chip, uint8_t *buf,
  846. int oob_required, int page)
  847. {
  848. struct nand_ecc_ctrl *ecc = &chip->ecc;
  849. unsigned int max_bitflips = 0;
  850. int ret, i, cur_off = 0;
  851. bool raw_mode = false;
  852. sunxi_nfc_hw_ecc_enable(mtd);
  853. for (i = 0; i < ecc->steps; i++) {
  854. int data_off = i * ecc->size;
  855. int oob_off = i * (ecc->bytes + 4);
  856. u8 *data = buf + data_off;
  857. u8 *oob = chip->oob_poi + oob_off;
  858. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
  859. oob_off + mtd->writesize,
  860. &cur_off, &max_bitflips,
  861. !i, page);
  862. if (ret < 0)
  863. return ret;
  864. else if (ret)
  865. raw_mode = true;
  866. }
  867. if (oob_required)
  868. sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
  869. !raw_mode, page);
  870. sunxi_nfc_hw_ecc_disable(mtd);
  871. return max_bitflips;
  872. }
  873. static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd,
  874. struct nand_chip *chip,
  875. uint32_t data_offs, uint32_t readlen,
  876. uint8_t *bufpoi, int page)
  877. {
  878. struct nand_ecc_ctrl *ecc = &chip->ecc;
  879. int ret, i, cur_off = 0;
  880. unsigned int max_bitflips = 0;
  881. sunxi_nfc_hw_ecc_enable(mtd);
  882. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  883. for (i = data_offs / ecc->size;
  884. i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
  885. int data_off = i * ecc->size;
  886. int oob_off = i * (ecc->bytes + 4);
  887. u8 *data = bufpoi + data_off;
  888. u8 *oob = chip->oob_poi + oob_off;
  889. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
  890. oob, oob_off + mtd->writesize,
  891. &cur_off, &max_bitflips, !i, page);
  892. if (ret < 0)
  893. return ret;
  894. }
  895. sunxi_nfc_hw_ecc_disable(mtd);
  896. return max_bitflips;
  897. }
  898. static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
  899. struct nand_chip *chip,
  900. const uint8_t *buf, int oob_required,
  901. int page)
  902. {
  903. struct nand_ecc_ctrl *ecc = &chip->ecc;
  904. int ret, i, cur_off = 0;
  905. sunxi_nfc_hw_ecc_enable(mtd);
  906. for (i = 0; i < ecc->steps; i++) {
  907. int data_off = i * ecc->size;
  908. int oob_off = i * (ecc->bytes + 4);
  909. const u8 *data = buf + data_off;
  910. const u8 *oob = chip->oob_poi + oob_off;
  911. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
  912. oob_off + mtd->writesize,
  913. &cur_off, !i, page);
  914. if (ret)
  915. return ret;
  916. }
  917. if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
  918. sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
  919. &cur_off, page);
  920. sunxi_nfc_hw_ecc_disable(mtd);
  921. return 0;
  922. }
  923. static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd,
  924. struct nand_chip *chip,
  925. u32 data_offs, u32 data_len,
  926. const u8 *buf, int oob_required,
  927. int page)
  928. {
  929. struct nand_ecc_ctrl *ecc = &chip->ecc;
  930. int ret, i, cur_off = 0;
  931. sunxi_nfc_hw_ecc_enable(mtd);
  932. for (i = data_offs / ecc->size;
  933. i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
  934. int data_off = i * ecc->size;
  935. int oob_off = i * (ecc->bytes + 4);
  936. const u8 *data = buf + data_off;
  937. const u8 *oob = chip->oob_poi + oob_off;
  938. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
  939. oob_off + mtd->writesize,
  940. &cur_off, !i, page);
  941. if (ret)
  942. return ret;
  943. }
  944. sunxi_nfc_hw_ecc_disable(mtd);
  945. return 0;
  946. }
  947. static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
  948. struct nand_chip *chip,
  949. uint8_t *buf, int oob_required,
  950. int page)
  951. {
  952. struct nand_ecc_ctrl *ecc = &chip->ecc;
  953. unsigned int max_bitflips = 0;
  954. int ret, i, cur_off = 0;
  955. bool raw_mode = false;
  956. sunxi_nfc_hw_ecc_enable(mtd);
  957. for (i = 0; i < ecc->steps; i++) {
  958. int data_off = i * (ecc->size + ecc->bytes + 4);
  959. int oob_off = data_off + ecc->size;
  960. u8 *data = buf + (i * ecc->size);
  961. u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
  962. ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
  963. oob_off, &cur_off,
  964. &max_bitflips, !i, page);
  965. if (ret < 0)
  966. return ret;
  967. else if (ret)
  968. raw_mode = true;
  969. }
  970. if (oob_required)
  971. sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
  972. !raw_mode, page);
  973. sunxi_nfc_hw_ecc_disable(mtd);
  974. return max_bitflips;
  975. }
  976. static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
  977. struct nand_chip *chip,
  978. const uint8_t *buf,
  979. int oob_required, int page)
  980. {
  981. struct nand_ecc_ctrl *ecc = &chip->ecc;
  982. int ret, i, cur_off = 0;
  983. sunxi_nfc_hw_ecc_enable(mtd);
  984. for (i = 0; i < ecc->steps; i++) {
  985. int data_off = i * (ecc->size + ecc->bytes + 4);
  986. int oob_off = data_off + ecc->size;
  987. const u8 *data = buf + (i * ecc->size);
  988. const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4));
  989. ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off,
  990. oob, oob_off, &cur_off,
  991. false, page);
  992. if (ret)
  993. return ret;
  994. }
  995. if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
  996. sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
  997. &cur_off, page);
  998. sunxi_nfc_hw_ecc_disable(mtd);
  999. return 0;
  1000. }
  1001. static const s32 tWB_lut[] = {6, 12, 16, 20};
  1002. static const s32 tRHW_lut[] = {4, 8, 12, 20};
  1003. static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
  1004. u32 clk_period)
  1005. {
  1006. u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
  1007. int i;
  1008. for (i = 0; i < lut_size; i++) {
  1009. if (clk_cycles <= lut[i])
  1010. return i;
  1011. }
  1012. /* Doesn't fit */
  1013. return -EINVAL;
  1014. }
  1015. #define sunxi_nand_lookup_timing(l, p, c) \
  1016. _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
  1017. static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
  1018. const struct nand_sdr_timings *timings)
  1019. {
  1020. u32 min_clk_period = 0;
  1021. s32 tWB, tADL, tWHR, tRHW, tCAD;
  1022. /* T1 <=> tCLS */
  1023. if (timings->tCLS_min > min_clk_period)
  1024. min_clk_period = timings->tCLS_min;
  1025. /* T2 <=> tCLH */
  1026. if (timings->tCLH_min > min_clk_period)
  1027. min_clk_period = timings->tCLH_min;
  1028. /* T3 <=> tCS */
  1029. if (timings->tCS_min > min_clk_period)
  1030. min_clk_period = timings->tCS_min;
  1031. /* T4 <=> tCH */
  1032. if (timings->tCH_min > min_clk_period)
  1033. min_clk_period = timings->tCH_min;
  1034. /* T5 <=> tWP */
  1035. if (timings->tWP_min > min_clk_period)
  1036. min_clk_period = timings->tWP_min;
  1037. /* T6 <=> tWH */
  1038. if (timings->tWH_min > min_clk_period)
  1039. min_clk_period = timings->tWH_min;
  1040. /* T7 <=> tALS */
  1041. if (timings->tALS_min > min_clk_period)
  1042. min_clk_period = timings->tALS_min;
  1043. /* T8 <=> tDS */
  1044. if (timings->tDS_min > min_clk_period)
  1045. min_clk_period = timings->tDS_min;
  1046. /* T9 <=> tDH */
  1047. if (timings->tDH_min > min_clk_period)
  1048. min_clk_period = timings->tDH_min;
  1049. /* T10 <=> tRR */
  1050. if (timings->tRR_min > (min_clk_period * 3))
  1051. min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
  1052. /* T11 <=> tALH */
  1053. if (timings->tALH_min > min_clk_period)
  1054. min_clk_period = timings->tALH_min;
  1055. /* T12 <=> tRP */
  1056. if (timings->tRP_min > min_clk_period)
  1057. min_clk_period = timings->tRP_min;
  1058. /* T13 <=> tREH */
  1059. if (timings->tREH_min > min_clk_period)
  1060. min_clk_period = timings->tREH_min;
  1061. /* T14 <=> tRC */
  1062. if (timings->tRC_min > (min_clk_period * 2))
  1063. min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
  1064. /* T15 <=> tWC */
  1065. if (timings->tWC_min > (min_clk_period * 2))
  1066. min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
  1067. /* T16 - T19 + tCAD */
  1068. tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
  1069. min_clk_period);
  1070. if (tWB < 0) {
  1071. dev_err(nfc->dev, "unsupported tWB\n");
  1072. return tWB;
  1073. }
  1074. tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
  1075. if (tADL > 3) {
  1076. dev_err(nfc->dev, "unsupported tADL\n");
  1077. return -EINVAL;
  1078. }
  1079. tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
  1080. if (tWHR > 3) {
  1081. dev_err(nfc->dev, "unsupported tWHR\n");
  1082. return -EINVAL;
  1083. }
  1084. tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
  1085. min_clk_period);
  1086. if (tRHW < 0) {
  1087. dev_err(nfc->dev, "unsupported tRHW\n");
  1088. return tRHW;
  1089. }
  1090. /*
  1091. * TODO: according to ONFI specs this value only applies for DDR NAND,
  1092. * but Allwinner seems to set this to 0x7. Mimic them for now.
  1093. */
  1094. tCAD = 0x7;
  1095. /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
  1096. chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
  1097. /*
  1098. * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
  1099. * output cycle timings shall be used if the host drives tRC less than
  1100. * 30 ns.
  1101. */
  1102. chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
  1103. /* Convert min_clk_period from picoseconds to nanoseconds */
  1104. min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
  1105. /*
  1106. * Convert min_clk_period into a clk frequency, then get the
  1107. * appropriate rate for the NAND controller IP given this formula
  1108. * (specified in the datasheet):
  1109. * nand clk_rate = min_clk_rate
  1110. */
  1111. chip->clk_rate = 1000000000L / min_clk_period;
  1112. return 0;
  1113. }
  1114. static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip)
  1115. {
  1116. struct mtd_info *mtd = nand_to_mtd(&chip->nand);
  1117. const struct nand_sdr_timings *timings;
  1118. int ret;
  1119. int mode;
  1120. mode = onfi_get_async_timing_mode(&chip->nand);
  1121. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  1122. mode = chip->nand.onfi_timing_mode_default;
  1123. } else {
  1124. uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
  1125. int i;
  1126. mode = fls(mode) - 1;
  1127. if (mode < 0)
  1128. mode = 0;
  1129. feature[0] = mode;
  1130. for (i = 0; i < chip->nsels; i++) {
  1131. chip->nand.select_chip(mtd, i);
  1132. ret = chip->nand.onfi_set_features(mtd,
  1133. &chip->nand,
  1134. ONFI_FEATURE_ADDR_TIMING_MODE,
  1135. feature);
  1136. chip->nand.select_chip(mtd, -1);
  1137. if (ret && ret != -ENOTSUPP)
  1138. return ret;
  1139. }
  1140. }
  1141. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  1142. if (IS_ERR(timings))
  1143. return PTR_ERR(timings);
  1144. return sunxi_nand_chip_set_timings(chip, timings);
  1145. }
  1146. static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
  1147. struct nand_ecc_ctrl *ecc)
  1148. {
  1149. static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
  1150. struct sunxi_nand_hw_ecc *data;
  1151. struct nand_ecclayout *layout;
  1152. int nsectors;
  1153. int ret;
  1154. int i;
  1155. data = kzalloc(sizeof(*data), GFP_KERNEL);
  1156. if (!data)
  1157. return -ENOMEM;
  1158. if (ecc->size != 512 && ecc->size != 1024)
  1159. return -EINVAL;
  1160. /* Prefer 1k ECC chunk over 512 ones */
  1161. if (ecc->size == 512 && mtd->writesize > 512) {
  1162. ecc->size = 1024;
  1163. ecc->strength *= 2;
  1164. }
  1165. /* Add ECC info retrieval from DT */
  1166. for (i = 0; i < ARRAY_SIZE(strengths); i++) {
  1167. if (ecc->strength <= strengths[i]) {
  1168. /*
  1169. * Update ecc->strength value with the actual strength
  1170. * that will be used by the ECC engine.
  1171. */
  1172. ecc->strength = strengths[i];
  1173. break;
  1174. }
  1175. }
  1176. if (i >= ARRAY_SIZE(strengths)) {
  1177. dev_err(nfc->dev, "unsupported strength\n");
  1178. ret = -ENOTSUPP;
  1179. goto err;
  1180. }
  1181. data->mode = i;
  1182. /* HW ECC always request ECC bytes for 1024 bytes blocks */
  1183. ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
  1184. /* HW ECC always work with even numbers of ECC bytes */
  1185. ecc->bytes = ALIGN(ecc->bytes, 2);
  1186. layout = &data->layout;
  1187. nsectors = mtd->writesize / ecc->size;
  1188. if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
  1189. ret = -EINVAL;
  1190. goto err;
  1191. }
  1192. layout->eccbytes = (ecc->bytes * nsectors);
  1193. ecc->layout = layout;
  1194. ecc->priv = data;
  1195. return 0;
  1196. err:
  1197. kfree(data);
  1198. return ret;
  1199. }
  1200. #ifndef __UBOOT__
  1201. static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
  1202. {
  1203. kfree(ecc->priv);
  1204. }
  1205. #endif /* __UBOOT__ */
  1206. static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
  1207. struct nand_ecc_ctrl *ecc)
  1208. {
  1209. struct nand_ecclayout *layout;
  1210. int nsectors;
  1211. int i, j;
  1212. int ret;
  1213. ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
  1214. if (ret)
  1215. return ret;
  1216. ecc->read_page = sunxi_nfc_hw_ecc_read_page;
  1217. ecc->write_page = sunxi_nfc_hw_ecc_write_page;
  1218. ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage;
  1219. ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage;
  1220. layout = ecc->layout;
  1221. nsectors = mtd->writesize / ecc->size;
  1222. for (i = 0; i < nsectors; i++) {
  1223. if (i) {
  1224. layout->oobfree[i].offset =
  1225. layout->oobfree[i - 1].offset +
  1226. layout->oobfree[i - 1].length +
  1227. ecc->bytes;
  1228. layout->oobfree[i].length = 4;
  1229. } else {
  1230. /*
  1231. * The first 2 bytes are used for BB markers, hence we
  1232. * only have 2 bytes available in the first user data
  1233. * section.
  1234. */
  1235. layout->oobfree[i].length = 2;
  1236. layout->oobfree[i].offset = 2;
  1237. }
  1238. for (j = 0; j < ecc->bytes; j++)
  1239. layout->eccpos[(ecc->bytes * i) + j] =
  1240. layout->oobfree[i].offset +
  1241. layout->oobfree[i].length + j;
  1242. }
  1243. if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
  1244. layout->oobfree[nsectors].offset =
  1245. layout->oobfree[nsectors - 1].offset +
  1246. layout->oobfree[nsectors - 1].length +
  1247. ecc->bytes;
  1248. layout->oobfree[nsectors].length = mtd->oobsize -
  1249. ((ecc->bytes + 4) * nsectors);
  1250. }
  1251. return 0;
  1252. }
  1253. static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
  1254. struct nand_ecc_ctrl *ecc)
  1255. {
  1256. struct nand_ecclayout *layout;
  1257. int nsectors;
  1258. int i;
  1259. int ret;
  1260. ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc);
  1261. if (ret)
  1262. return ret;
  1263. ecc->prepad = 4;
  1264. ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
  1265. ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
  1266. layout = ecc->layout;
  1267. nsectors = mtd->writesize / ecc->size;
  1268. for (i = 0; i < (ecc->bytes * nsectors); i++)
  1269. layout->eccpos[i] = i;
  1270. layout->oobfree[0].length = mtd->oobsize - i;
  1271. layout->oobfree[0].offset = i;
  1272. return 0;
  1273. }
  1274. #ifndef __UBOOT__
  1275. static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
  1276. {
  1277. switch (ecc->mode) {
  1278. case NAND_ECC_HW:
  1279. case NAND_ECC_HW_SYNDROME:
  1280. sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
  1281. break;
  1282. case NAND_ECC_NONE:
  1283. kfree(ecc->layout);
  1284. default:
  1285. break;
  1286. }
  1287. }
  1288. #endif /* __UBOOT__ */
  1289. static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
  1290. {
  1291. struct nand_chip *nand = mtd_to_nand(mtd);
  1292. int ret;
  1293. if (!ecc->size) {
  1294. ecc->size = nand->ecc_step_ds;
  1295. ecc->strength = nand->ecc_strength_ds;
  1296. }
  1297. if (!ecc->size || !ecc->strength)
  1298. return -EINVAL;
  1299. switch (ecc->mode) {
  1300. case NAND_ECC_SOFT_BCH:
  1301. break;
  1302. case NAND_ECC_HW:
  1303. ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc);
  1304. if (ret)
  1305. return ret;
  1306. break;
  1307. case NAND_ECC_HW_SYNDROME:
  1308. ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc);
  1309. if (ret)
  1310. return ret;
  1311. break;
  1312. case NAND_ECC_NONE:
  1313. ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
  1314. if (!ecc->layout)
  1315. return -ENOMEM;
  1316. ecc->layout->oobfree[0].length = mtd->oobsize;
  1317. case NAND_ECC_SOFT:
  1318. break;
  1319. default:
  1320. return -EINVAL;
  1321. }
  1322. return 0;
  1323. }
  1324. static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum)
  1325. {
  1326. const struct nand_sdr_timings *timings;
  1327. const void *blob = gd->fdt_blob;
  1328. struct sunxi_nand_chip *chip;
  1329. struct mtd_info *mtd;
  1330. struct nand_chip *nand;
  1331. int nsels;
  1332. int ret;
  1333. int i;
  1334. u32 cs[8], rb[8];
  1335. if (!fdt_getprop(blob, node, "reg", &nsels))
  1336. return -EINVAL;
  1337. nsels /= sizeof(u32);
  1338. if (!nsels || nsels > 8) {
  1339. dev_err(dev, "invalid reg property size\n");
  1340. return -EINVAL;
  1341. }
  1342. chip = kzalloc(sizeof(*chip) +
  1343. (nsels * sizeof(struct sunxi_nand_chip_sel)),
  1344. GFP_KERNEL);
  1345. if (!chip) {
  1346. dev_err(dev, "could not allocate chip\n");
  1347. return -ENOMEM;
  1348. }
  1349. chip->nsels = nsels;
  1350. chip->selected = -1;
  1351. for (i = 0; i < nsels; i++) {
  1352. cs[i] = -1;
  1353. rb[i] = -1;
  1354. }
  1355. ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels);
  1356. if (ret) {
  1357. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  1358. return ret;
  1359. }
  1360. ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb,
  1361. nsels);
  1362. if (ret) {
  1363. dev_err(dev, "could not retrieve reg property: %d\n", ret);
  1364. return ret;
  1365. }
  1366. for (i = 0; i < nsels; i++) {
  1367. int tmp = cs[i];
  1368. if (tmp > NFC_MAX_CS) {
  1369. dev_err(dev,
  1370. "invalid reg value: %u (max CS = 7)\n",
  1371. tmp);
  1372. return -EINVAL;
  1373. }
  1374. if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
  1375. dev_err(dev, "CS %d already assigned\n", tmp);
  1376. return -EINVAL;
  1377. }
  1378. chip->sels[i].cs = tmp;
  1379. tmp = rb[i];
  1380. if (tmp >= 0 && tmp < 2) {
  1381. chip->sels[i].rb.type = RB_NATIVE;
  1382. chip->sels[i].rb.info.nativeid = tmp;
  1383. } else {
  1384. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  1385. "rb-gpios", i,
  1386. &chip->sels[i].rb.info.gpio,
  1387. GPIOD_IS_IN);
  1388. if (ret)
  1389. chip->sels[i].rb.type = RB_GPIO;
  1390. else
  1391. chip->sels[i].rb.type = RB_NONE;
  1392. }
  1393. }
  1394. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1395. if (IS_ERR(timings)) {
  1396. ret = PTR_ERR(timings);
  1397. dev_err(dev,
  1398. "could not retrieve timings for ONFI mode 0: %d\n",
  1399. ret);
  1400. return ret;
  1401. }
  1402. ret = sunxi_nand_chip_set_timings(chip, timings);
  1403. if (ret) {
  1404. dev_err(dev, "could not configure chip timings: %d\n", ret);
  1405. return ret;
  1406. }
  1407. nand = &chip->nand;
  1408. /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
  1409. nand->chip_delay = 200;
  1410. nand->controller = &nfc->controller;
  1411. /*
  1412. * Set the ECC mode to the default value in case nothing is specified
  1413. * in the DT.
  1414. */
  1415. nand->ecc.mode = NAND_ECC_HW;
  1416. nand->flash_node = node;
  1417. nand->select_chip = sunxi_nfc_select_chip;
  1418. nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
  1419. nand->read_buf = sunxi_nfc_read_buf;
  1420. nand->write_buf = sunxi_nfc_write_buf;
  1421. nand->read_byte = sunxi_nfc_read_byte;
  1422. mtd = nand_to_mtd(nand);
  1423. ret = nand_scan_ident(mtd, nsels, NULL);
  1424. if (ret)
  1425. return ret;
  1426. if (nand->bbt_options & NAND_BBT_USE_FLASH)
  1427. nand->bbt_options |= NAND_BBT_NO_OOB;
  1428. if (nand->options & NAND_NEED_SCRAMBLING)
  1429. nand->options |= NAND_NO_SUBPAGE_WRITE;
  1430. nand->options |= NAND_SUBPAGE_READ;
  1431. ret = sunxi_nand_chip_init_timings(chip);
  1432. if (ret) {
  1433. dev_err(dev, "could not configure chip timings: %d\n", ret);
  1434. return ret;
  1435. }
  1436. ret = sunxi_nand_ecc_init(mtd, &nand->ecc);
  1437. if (ret) {
  1438. dev_err(dev, "ECC init failed: %d\n", ret);
  1439. return ret;
  1440. }
  1441. ret = nand_scan_tail(mtd);
  1442. if (ret) {
  1443. dev_err(dev, "nand_scan_tail failed: %d\n", ret);
  1444. return ret;
  1445. }
  1446. ret = nand_register(devnum, mtd);
  1447. if (ret) {
  1448. dev_err(dev, "failed to register mtd device: %d\n", ret);
  1449. return ret;
  1450. }
  1451. list_add_tail(&chip->node, &nfc->chips);
  1452. return 0;
  1453. }
  1454. static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc)
  1455. {
  1456. const void *blob = gd->fdt_blob;
  1457. int nand_node;
  1458. int ret, i = 0;
  1459. for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
  1460. nand_node = fdt_next_subnode(blob, nand_node))
  1461. i++;
  1462. if (i > 8) {
  1463. dev_err(dev, "too many NAND chips: %d (max = 8)\n", i);
  1464. return -EINVAL;
  1465. }
  1466. i = 0;
  1467. for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
  1468. nand_node = fdt_next_subnode(blob, nand_node)) {
  1469. ret = sunxi_nand_chip_init(nand_node, nfc, i++);
  1470. if (ret)
  1471. return ret;
  1472. }
  1473. return 0;
  1474. }
  1475. #ifndef __UBOOT__
  1476. static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
  1477. {
  1478. struct sunxi_nand_chip *chip;
  1479. while (!list_empty(&nfc->chips)) {
  1480. chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
  1481. node);
  1482. nand_release(&chip->mtd);
  1483. sunxi_nand_ecc_cleanup(&chip->nand.ecc);
  1484. list_del(&chip->node);
  1485. kfree(chip);
  1486. }
  1487. }
  1488. #endif /* __UBOOT__ */
  1489. void sunxi_nand_init(void)
  1490. {
  1491. const void *blob = gd->fdt_blob;
  1492. struct sunxi_nfc *nfc;
  1493. fdt_addr_t regs;
  1494. int node;
  1495. int ret;
  1496. nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
  1497. if (!nfc)
  1498. return;
  1499. spin_lock_init(&nfc->controller.lock);
  1500. init_waitqueue_head(&nfc->controller.wq);
  1501. INIT_LIST_HEAD(&nfc->chips);
  1502. node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND);
  1503. if (node < 0) {
  1504. pr_err("unable to find nfc node in device tree\n");
  1505. goto err;
  1506. }
  1507. if (!fdtdec_get_is_enabled(blob, node)) {
  1508. pr_err("nfc disabled in device tree\n");
  1509. goto err;
  1510. }
  1511. regs = fdtdec_get_addr(blob, node, "reg");
  1512. if (regs == FDT_ADDR_T_NONE) {
  1513. pr_err("unable to find nfc address in device tree\n");
  1514. goto err;
  1515. }
  1516. nfc->regs = (void *)regs;
  1517. ret = sunxi_nfc_rst(nfc);
  1518. if (ret)
  1519. goto err;
  1520. ret = sunxi_nand_chips_init(node, nfc);
  1521. if (ret) {
  1522. dev_err(dev, "failed to init nand chips\n");
  1523. goto err;
  1524. }
  1525. return;
  1526. err:
  1527. kfree(nfc);
  1528. }
  1529. MODULE_LICENSE("GPL v2");
  1530. MODULE_AUTHOR("Boris BREZILLON");
  1531. MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");