omap_gpmc.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
  4. * Rohit Choraria <rohitkc@ti.com>
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <linux/errno.h>
  9. #include <asm/arch/mem.h>
  10. #include <linux/mtd/omap_gpmc.h>
  11. #include <linux/mtd/nand_ecc.h>
  12. #include <linux/bch.h>
  13. #include <linux/compiler.h>
  14. #include <nand.h>
  15. #include <linux/mtd/omap_elm.h>
  16. #define BADBLOCK_MARKER_LENGTH 2
  17. #define SECTOR_BYTES 512
  18. #define ECCCLEAR (0x1 << 8)
  19. #define ECCRESULTREG1 (0x1 << 0)
  20. /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  21. #define BCH4_BIT_PAD 4
  22. #ifdef CONFIG_BCH
  23. static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  24. 0x97, 0x79, 0xe5, 0x24, 0xb5};
  25. #endif
  26. static uint8_t cs_next;
  27. static __maybe_unused struct nand_ecclayout omap_ecclayout;
  28. #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
  29. static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
  30. { CONFIG_NAND_OMAP_GPMC_WSCFG };
  31. #else
  32. /* wscfg is preset to zero since its a static variable */
  33. static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
  34. #endif
  35. /*
  36. * Driver configurations
  37. */
  38. struct omap_nand_info {
  39. struct bch_control *control;
  40. enum omap_ecc ecc_scheme;
  41. uint8_t cs;
  42. uint8_t ws; /* wait status pin (0,1) */
  43. };
  44. /* We are wasting a bit of memory but al least we are safe */
  45. static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  46. /*
  47. * omap_nand_hwcontrol - Set the address pointers corretly for the
  48. * following address/data/command operation
  49. */
  50. static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  51. uint32_t ctrl)
  52. {
  53. register struct nand_chip *this = mtd_to_nand(mtd);
  54. struct omap_nand_info *info = nand_get_controller_data(this);
  55. int cs = info->cs;
  56. /*
  57. * Point the IO_ADDR to DATA and ADDRESS registers instead
  58. * of chip address
  59. */
  60. switch (ctrl) {
  61. case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  62. this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  63. break;
  64. case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  65. this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  66. break;
  67. case NAND_CTRL_CHANGE | NAND_NCE:
  68. this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  69. break;
  70. }
  71. if (cmd != NAND_CMD_NONE)
  72. writeb(cmd, this->IO_ADDR_W);
  73. }
  74. /* Check wait pin as dev ready indicator */
  75. static int omap_dev_ready(struct mtd_info *mtd)
  76. {
  77. register struct nand_chip *this = mtd_to_nand(mtd);
  78. struct omap_nand_info *info = nand_get_controller_data(this);
  79. return gpmc_cfg->status & (1 << (8 + info->ws));
  80. }
  81. /*
  82. * gen_true_ecc - This function will generate true ECC value, which
  83. * can be used when correcting data read from NAND flash memory core
  84. *
  85. * @ecc_buf: buffer to store ecc code
  86. *
  87. * @return: re-formatted ECC value
  88. */
  89. static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  90. {
  91. return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  92. ((ecc_buf[2] & 0x0F) << 8);
  93. }
  94. /*
  95. * omap_correct_data - Compares the ecc read from nand spare area with ECC
  96. * registers values and corrects one bit error if it has occurred
  97. * Further details can be had from OMAP TRM and the following selected links:
  98. * http://en.wikipedia.org/wiki/Hamming_code
  99. * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
  100. *
  101. * @mtd: MTD device structure
  102. * @dat: page data
  103. * @read_ecc: ecc read from nand flash
  104. * @calc_ecc: ecc read from ECC registers
  105. *
  106. * @return 0 if data is OK or corrected, else returns -1
  107. */
  108. static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
  109. uint8_t *read_ecc, uint8_t *calc_ecc)
  110. {
  111. uint32_t orig_ecc, new_ecc, res, hm;
  112. uint16_t parity_bits, byte;
  113. uint8_t bit;
  114. /* Regenerate the orginal ECC */
  115. orig_ecc = gen_true_ecc(read_ecc);
  116. new_ecc = gen_true_ecc(calc_ecc);
  117. /* Get the XOR of real ecc */
  118. res = orig_ecc ^ new_ecc;
  119. if (res) {
  120. /* Get the hamming width */
  121. hm = hweight32(res);
  122. /* Single bit errors can be corrected! */
  123. if (hm == 12) {
  124. /* Correctable data! */
  125. parity_bits = res >> 16;
  126. bit = (parity_bits & 0x7);
  127. byte = (parity_bits >> 3) & 0x1FF;
  128. /* Flip the bit to correct */
  129. dat[byte] ^= (0x1 << bit);
  130. } else if (hm == 1) {
  131. printf("Error: Ecc is wrong\n");
  132. /* ECC itself is corrupted */
  133. return 2;
  134. } else {
  135. /*
  136. * hm distance != parity pairs OR one, could mean 2 bit
  137. * error OR potentially be on a blank page..
  138. * orig_ecc: contains spare area data from nand flash.
  139. * new_ecc: generated ecc while reading data area.
  140. * Note: if the ecc = 0, all data bits from which it was
  141. * generated are 0xFF.
  142. * The 3 byte(24 bits) ecc is generated per 512byte
  143. * chunk of a page. If orig_ecc(from spare area)
  144. * is 0xFF && new_ecc(computed now from data area)=0x0,
  145. * this means that data area is 0xFF and spare area is
  146. * 0xFF. A sure sign of a erased page!
  147. */
  148. if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
  149. return 0;
  150. printf("Error: Bad compare! failed\n");
  151. /* detected 2 bit error */
  152. return -EBADMSG;
  153. }
  154. }
  155. return 0;
  156. }
  157. /*
  158. * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
  159. * @mtd: MTD device structure
  160. * @mode: Read/Write mode
  161. */
  162. __maybe_unused
  163. static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
  164. {
  165. struct nand_chip *nand = mtd_to_nand(mtd);
  166. struct omap_nand_info *info = nand_get_controller_data(nand);
  167. unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
  168. unsigned int ecc_algo = 0;
  169. unsigned int bch_type = 0;
  170. unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
  171. u32 ecc_size_config_val = 0;
  172. u32 ecc_config_val = 0;
  173. int cs = info->cs;
  174. /* configure GPMC for specific ecc-scheme */
  175. switch (info->ecc_scheme) {
  176. case OMAP_ECC_HAM1_CODE_SW:
  177. return;
  178. case OMAP_ECC_HAM1_CODE_HW:
  179. ecc_algo = 0x0;
  180. bch_type = 0x0;
  181. bch_wrapmode = 0x00;
  182. eccsize0 = 0xFF;
  183. eccsize1 = 0xFF;
  184. break;
  185. case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
  186. case OMAP_ECC_BCH8_CODE_HW:
  187. ecc_algo = 0x1;
  188. bch_type = 0x1;
  189. if (mode == NAND_ECC_WRITE) {
  190. bch_wrapmode = 0x01;
  191. eccsize0 = 0; /* extra bits in nibbles per sector */
  192. eccsize1 = 28; /* OOB bits in nibbles per sector */
  193. } else {
  194. bch_wrapmode = 0x01;
  195. eccsize0 = 26; /* ECC bits in nibbles per sector */
  196. eccsize1 = 2; /* non-ECC bits in nibbles per sector */
  197. }
  198. break;
  199. case OMAP_ECC_BCH16_CODE_HW:
  200. ecc_algo = 0x1;
  201. bch_type = 0x2;
  202. if (mode == NAND_ECC_WRITE) {
  203. bch_wrapmode = 0x01;
  204. eccsize0 = 0; /* extra bits in nibbles per sector */
  205. eccsize1 = 52; /* OOB bits in nibbles per sector */
  206. } else {
  207. bch_wrapmode = 0x01;
  208. eccsize0 = 52; /* ECC bits in nibbles per sector */
  209. eccsize1 = 0; /* non-ECC bits in nibbles per sector */
  210. }
  211. break;
  212. default:
  213. return;
  214. }
  215. /* Clear ecc and enable bits */
  216. writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
  217. /* Configure ecc size for BCH */
  218. ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
  219. writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
  220. /* Configure device details for BCH engine */
  221. ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */
  222. (bch_type << 12) | /* BCH4/BCH8/BCH16 */
  223. (bch_wrapmode << 8) | /* wrap mode */
  224. (dev_width << 7) | /* bus width */
  225. (0x0 << 4) | /* number of sectors */
  226. (cs << 1) | /* ECC CS */
  227. (0x1)); /* enable ECC */
  228. writel(ecc_config_val, &gpmc_cfg->ecc_config);
  229. }
  230. /*
  231. * omap_calculate_ecc - Read ECC result
  232. * @mtd: MTD structure
  233. * @dat: unused
  234. * @ecc_code: ecc_code buffer
  235. * Using noninverted ECC can be considered ugly since writing a blank
  236. * page ie. padding will clear the ECC bytes. This is no problem as
  237. * long nobody is trying to write data on the seemingly unused page.
  238. * Reading an erased page will produce an ECC mismatch between
  239. * generated and read ECC bytes that has to be dealt with separately.
  240. * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
  241. * is used, the result of read will be 0x0 while the ECC offsets of the
  242. * spare area will be 0xFF which will result in an ECC mismatch.
  243. */
  244. static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
  245. uint8_t *ecc_code)
  246. {
  247. struct nand_chip *chip = mtd_to_nand(mtd);
  248. struct omap_nand_info *info = nand_get_controller_data(chip);
  249. const uint32_t *ptr;
  250. uint32_t val = 0;
  251. int8_t i = 0, j;
  252. switch (info->ecc_scheme) {
  253. case OMAP_ECC_HAM1_CODE_HW:
  254. val = readl(&gpmc_cfg->ecc1_result);
  255. ecc_code[0] = val & 0xFF;
  256. ecc_code[1] = (val >> 16) & 0xFF;
  257. ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
  258. break;
  259. #ifdef CONFIG_BCH
  260. case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
  261. #endif
  262. case OMAP_ECC_BCH8_CODE_HW:
  263. ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
  264. val = readl(ptr);
  265. ecc_code[i++] = (val >> 0) & 0xFF;
  266. ptr--;
  267. for (j = 0; j < 3; j++) {
  268. val = readl(ptr);
  269. ecc_code[i++] = (val >> 24) & 0xFF;
  270. ecc_code[i++] = (val >> 16) & 0xFF;
  271. ecc_code[i++] = (val >> 8) & 0xFF;
  272. ecc_code[i++] = (val >> 0) & 0xFF;
  273. ptr--;
  274. }
  275. break;
  276. case OMAP_ECC_BCH16_CODE_HW:
  277. val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
  278. ecc_code[i++] = (val >> 8) & 0xFF;
  279. ecc_code[i++] = (val >> 0) & 0xFF;
  280. val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
  281. ecc_code[i++] = (val >> 24) & 0xFF;
  282. ecc_code[i++] = (val >> 16) & 0xFF;
  283. ecc_code[i++] = (val >> 8) & 0xFF;
  284. ecc_code[i++] = (val >> 0) & 0xFF;
  285. val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
  286. ecc_code[i++] = (val >> 24) & 0xFF;
  287. ecc_code[i++] = (val >> 16) & 0xFF;
  288. ecc_code[i++] = (val >> 8) & 0xFF;
  289. ecc_code[i++] = (val >> 0) & 0xFF;
  290. for (j = 3; j >= 0; j--) {
  291. val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
  292. );
  293. ecc_code[i++] = (val >> 24) & 0xFF;
  294. ecc_code[i++] = (val >> 16) & 0xFF;
  295. ecc_code[i++] = (val >> 8) & 0xFF;
  296. ecc_code[i++] = (val >> 0) & 0xFF;
  297. }
  298. break;
  299. default:
  300. return -EINVAL;
  301. }
  302. /* ECC scheme specific syndrome customizations */
  303. switch (info->ecc_scheme) {
  304. case OMAP_ECC_HAM1_CODE_HW:
  305. break;
  306. #ifdef CONFIG_BCH
  307. case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
  308. for (i = 0; i < chip->ecc.bytes; i++)
  309. *(ecc_code + i) = *(ecc_code + i) ^
  310. bch8_polynomial[i];
  311. break;
  312. #endif
  313. case OMAP_ECC_BCH8_CODE_HW:
  314. ecc_code[chip->ecc.bytes - 1] = 0x00;
  315. break;
  316. case OMAP_ECC_BCH16_CODE_HW:
  317. break;
  318. default:
  319. return -EINVAL;
  320. }
  321. return 0;
  322. }
  323. #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
  324. #define PREFETCH_CONFIG1_CS_SHIFT 24
  325. #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
  326. #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
  327. #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
  328. #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
  329. #define ENABLE_PREFETCH (1 << 7)
  330. /**
  331. * omap_prefetch_enable - configures and starts prefetch transfer
  332. * @fifo_th: fifo threshold to be used for read/ write
  333. * @count: number of bytes to be transferred
  334. * @is_write: prefetch read(0) or write post(1) mode
  335. * @cs: chip select to use
  336. */
  337. static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
  338. {
  339. uint32_t val;
  340. if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
  341. return -EINVAL;
  342. if (readl(&gpmc_cfg->prefetch_control))
  343. return -EBUSY;
  344. /* Set the amount of bytes to be prefetched */
  345. writel(count, &gpmc_cfg->prefetch_config2);
  346. val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
  347. PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
  348. writel(val, &gpmc_cfg->prefetch_config1);
  349. /* Start the prefetch engine */
  350. writel(1, &gpmc_cfg->prefetch_control);
  351. return 0;
  352. }
  353. /**
  354. * omap_prefetch_reset - disables and stops the prefetch engine
  355. */
  356. static void omap_prefetch_reset(void)
  357. {
  358. writel(0, &gpmc_cfg->prefetch_control);
  359. writel(0, &gpmc_cfg->prefetch_config1);
  360. }
  361. static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
  362. {
  363. int ret;
  364. uint32_t cnt;
  365. struct omap_nand_info *info = nand_get_controller_data(chip);
  366. ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
  367. if (ret < 0)
  368. return ret;
  369. do {
  370. int i;
  371. cnt = readl(&gpmc_cfg->prefetch_status);
  372. cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
  373. for (i = 0; i < cnt / 4; i++) {
  374. *buf++ = readl(CONFIG_SYS_NAND_BASE);
  375. len -= 4;
  376. }
  377. } while (len);
  378. omap_prefetch_reset();
  379. return 0;
  380. }
  381. static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
  382. {
  383. struct nand_chip *chip = mtd_to_nand(mtd);
  384. if (chip->options & NAND_BUSWIDTH_16)
  385. nand_read_buf16(mtd, buf, len);
  386. else
  387. nand_read_buf(mtd, buf, len);
  388. }
  389. static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
  390. {
  391. int ret;
  392. uint32_t head, tail;
  393. struct nand_chip *chip = mtd_to_nand(mtd);
  394. /*
  395. * If the destination buffer is unaligned, start with reading
  396. * the overlap byte-wise.
  397. */
  398. head = ((uint32_t) buf) % 4;
  399. if (head) {
  400. omap_nand_read(mtd, buf, head);
  401. buf += head;
  402. len -= head;
  403. }
  404. /*
  405. * Only transfer multiples of 4 bytes in a pre-fetched fashion.
  406. * If there's a residue, care for it byte-wise afterwards.
  407. */
  408. tail = len % 4;
  409. ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
  410. if (ret < 0) {
  411. /* fallback in case the prefetch engine is busy */
  412. omap_nand_read(mtd, buf, len);
  413. } else if (tail) {
  414. buf += len - tail;
  415. omap_nand_read(mtd, buf, tail);
  416. }
  417. }
  418. #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
  419. #ifdef CONFIG_NAND_OMAP_ELM
  420. /*
  421. * omap_reverse_list - re-orders list elements in reverse order [internal]
  422. * @list: pointer to start of list
  423. * @length: length of list
  424. */
  425. static void omap_reverse_list(u8 *list, unsigned int length)
  426. {
  427. unsigned int i, j;
  428. unsigned int half_length = length / 2;
  429. u8 tmp;
  430. for (i = 0, j = length - 1; i < half_length; i++, j--) {
  431. tmp = list[i];
  432. list[i] = list[j];
  433. list[j] = tmp;
  434. }
  435. }
  436. /*
  437. * omap_correct_data_bch - Compares the ecc read from nand spare area
  438. * with ECC registers values and corrects one bit error if it has occurred
  439. *
  440. * @mtd: MTD device structure
  441. * @dat: page data
  442. * @read_ecc: ecc read from nand flash (ignored)
  443. * @calc_ecc: ecc read from ECC registers
  444. *
  445. * @return 0 if data is OK or corrected, else returns -1
  446. */
  447. static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
  448. uint8_t *read_ecc, uint8_t *calc_ecc)
  449. {
  450. struct nand_chip *chip = mtd_to_nand(mtd);
  451. struct omap_nand_info *info = nand_get_controller_data(chip);
  452. struct nand_ecc_ctrl *ecc = &chip->ecc;
  453. uint32_t error_count = 0, error_max;
  454. uint32_t error_loc[ELM_MAX_ERROR_COUNT];
  455. enum bch_level bch_type;
  456. uint32_t i, ecc_flag = 0;
  457. uint8_t count;
  458. uint32_t byte_pos, bit_pos;
  459. int err = 0;
  460. /* check calculated ecc */
  461. for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
  462. if (calc_ecc[i] != 0x00)
  463. ecc_flag = 1;
  464. }
  465. if (!ecc_flag)
  466. return 0;
  467. /* check for whether its a erased-page */
  468. ecc_flag = 0;
  469. for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
  470. if (read_ecc[i] != 0xff)
  471. ecc_flag = 1;
  472. }
  473. if (!ecc_flag)
  474. return 0;
  475. /*
  476. * while reading ECC result we read it in big endian.
  477. * Hence while loading to ELM we have rotate to get the right endian.
  478. */
  479. switch (info->ecc_scheme) {
  480. case OMAP_ECC_BCH8_CODE_HW:
  481. bch_type = BCH_8_BIT;
  482. omap_reverse_list(calc_ecc, ecc->bytes - 1);
  483. break;
  484. case OMAP_ECC_BCH16_CODE_HW:
  485. bch_type = BCH_16_BIT;
  486. omap_reverse_list(calc_ecc, ecc->bytes);
  487. break;
  488. default:
  489. return -EINVAL;
  490. }
  491. /* use elm module to check for errors */
  492. elm_config(bch_type);
  493. err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
  494. if (err)
  495. return err;
  496. /* correct bch error */
  497. for (count = 0; count < error_count; count++) {
  498. switch (info->ecc_scheme) {
  499. case OMAP_ECC_BCH8_CODE_HW:
  500. /* 14th byte in ECC is reserved to match ROM layout */
  501. error_max = SECTOR_BYTES + (ecc->bytes - 1);
  502. break;
  503. case OMAP_ECC_BCH16_CODE_HW:
  504. error_max = SECTOR_BYTES + ecc->bytes;
  505. break;
  506. default:
  507. return -EINVAL;
  508. }
  509. byte_pos = error_max - (error_loc[count] / 8) - 1;
  510. bit_pos = error_loc[count] % 8;
  511. if (byte_pos < SECTOR_BYTES) {
  512. dat[byte_pos] ^= 1 << bit_pos;
  513. debug("nand: bit-flip corrected @data=%d\n", byte_pos);
  514. } else if (byte_pos < error_max) {
  515. read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
  516. debug("nand: bit-flip corrected @oob=%d\n", byte_pos -
  517. SECTOR_BYTES);
  518. } else {
  519. err = -EBADMSG;
  520. printf("nand: error: invalid bit-flip location\n");
  521. }
  522. }
  523. return (err) ? err : error_count;
  524. }
  525. /**
  526. * omap_read_page_bch - hardware ecc based page read function
  527. * @mtd: mtd info structure
  528. * @chip: nand chip info structure
  529. * @buf: buffer to store read data
  530. * @oob_required: caller expects OOB data read to chip->oob_poi
  531. * @page: page number to read
  532. *
  533. */
  534. static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
  535. uint8_t *buf, int oob_required, int page)
  536. {
  537. int i, eccsize = chip->ecc.size;
  538. int eccbytes = chip->ecc.bytes;
  539. int eccsteps = chip->ecc.steps;
  540. uint8_t *p = buf;
  541. uint8_t *ecc_calc = chip->buffers->ecccalc;
  542. uint8_t *ecc_code = chip->buffers->ecccode;
  543. uint32_t *eccpos = chip->ecc.layout->eccpos;
  544. uint8_t *oob = chip->oob_poi;
  545. uint32_t data_pos;
  546. uint32_t oob_pos;
  547. data_pos = 0;
  548. /* oob area start */
  549. oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
  550. oob += chip->ecc.layout->eccpos[0];
  551. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
  552. oob += eccbytes) {
  553. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  554. /* read data */
  555. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
  556. chip->read_buf(mtd, p, eccsize);
  557. /* read respective ecc from oob area */
  558. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
  559. chip->read_buf(mtd, oob, eccbytes);
  560. /* read syndrome */
  561. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  562. data_pos += eccsize;
  563. oob_pos += eccbytes;
  564. }
  565. for (i = 0; i < chip->ecc.total; i++)
  566. ecc_code[i] = chip->oob_poi[eccpos[i]];
  567. eccsteps = chip->ecc.steps;
  568. p = buf;
  569. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  570. int stat;
  571. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  572. if (stat < 0)
  573. mtd->ecc_stats.failed++;
  574. else
  575. mtd->ecc_stats.corrected += stat;
  576. }
  577. return 0;
  578. }
  579. #endif /* CONFIG_NAND_OMAP_ELM */
  580. /*
  581. * OMAP3 BCH8 support (with BCH library)
  582. */
  583. #ifdef CONFIG_BCH
  584. /**
  585. * omap_correct_data_bch_sw - Decode received data and correct errors
  586. * @mtd: MTD device structure
  587. * @data: page data
  588. * @read_ecc: ecc read from nand flash
  589. * @calc_ecc: ecc read from HW ECC registers
  590. */
  591. static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
  592. u_char *read_ecc, u_char *calc_ecc)
  593. {
  594. int i, count;
  595. /* cannot correct more than 8 errors */
  596. unsigned int errloc[8];
  597. struct nand_chip *chip = mtd_to_nand(mtd);
  598. struct omap_nand_info *info = nand_get_controller_data(chip);
  599. count = decode_bch(info->control, NULL, SECTOR_BYTES,
  600. read_ecc, calc_ecc, NULL, errloc);
  601. if (count > 0) {
  602. /* correct errors */
  603. for (i = 0; i < count; i++) {
  604. /* correct data only, not ecc bytes */
  605. if (errloc[i] < SECTOR_BYTES << 3)
  606. data[errloc[i] >> 3] ^= 1 << (errloc[i] & 7);
  607. debug("corrected bitflip %u\n", errloc[i]);
  608. #ifdef DEBUG
  609. puts("read_ecc: ");
  610. /*
  611. * BCH8 have 13 bytes of ECC; BCH4 needs adoption
  612. * here!
  613. */
  614. for (i = 0; i < 13; i++)
  615. printf("%02x ", read_ecc[i]);
  616. puts("\n");
  617. puts("calc_ecc: ");
  618. for (i = 0; i < 13; i++)
  619. printf("%02x ", calc_ecc[i]);
  620. puts("\n");
  621. #endif
  622. }
  623. } else if (count < 0) {
  624. puts("ecc unrecoverable error\n");
  625. }
  626. return count;
  627. }
  628. /**
  629. * omap_free_bch - Release BCH ecc resources
  630. * @mtd: MTD device structure
  631. */
  632. static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
  633. {
  634. struct nand_chip *chip = mtd_to_nand(mtd);
  635. struct omap_nand_info *info = nand_get_controller_data(chip);
  636. if (info->control) {
  637. free_bch(info->control);
  638. info->control = NULL;
  639. }
  640. }
  641. #endif /* CONFIG_BCH */
  642. /**
  643. * omap_select_ecc_scheme - configures driver for particular ecc-scheme
  644. * @nand: NAND chip device structure
  645. * @ecc_scheme: ecc scheme to configure
  646. * @pagesize: number of main-area bytes per page of NAND device
  647. * @oobsize: number of OOB/spare bytes per page of NAND device
  648. */
  649. static int omap_select_ecc_scheme(struct nand_chip *nand,
  650. enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
  651. struct omap_nand_info *info = nand_get_controller_data(nand);
  652. struct nand_ecclayout *ecclayout = &omap_ecclayout;
  653. int eccsteps = pagesize / SECTOR_BYTES;
  654. int i;
  655. switch (ecc_scheme) {
  656. case OMAP_ECC_HAM1_CODE_SW:
  657. debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
  658. /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
  659. * initialized in nand_scan_tail(), so just set ecc.mode */
  660. info->control = NULL;
  661. nand->ecc.mode = NAND_ECC_SOFT;
  662. nand->ecc.layout = NULL;
  663. nand->ecc.size = 0;
  664. break;
  665. case OMAP_ECC_HAM1_CODE_HW:
  666. debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
  667. /* check ecc-scheme requirements before updating ecc info */
  668. if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
  669. printf("nand: error: insufficient OOB: require=%d\n", (
  670. (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
  671. return -EINVAL;
  672. }
  673. info->control = NULL;
  674. /* populate ecc specific fields */
  675. memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
  676. nand->ecc.mode = NAND_ECC_HW;
  677. nand->ecc.strength = 1;
  678. nand->ecc.size = SECTOR_BYTES;
  679. nand->ecc.bytes = 3;
  680. nand->ecc.hwctl = omap_enable_hwecc;
  681. nand->ecc.correct = omap_correct_data;
  682. nand->ecc.calculate = omap_calculate_ecc;
  683. /* define ecc-layout */
  684. ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
  685. for (i = 0; i < ecclayout->eccbytes; i++) {
  686. if (nand->options & NAND_BUSWIDTH_16)
  687. ecclayout->eccpos[i] = i + 2;
  688. else
  689. ecclayout->eccpos[i] = i + 1;
  690. }
  691. ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
  692. ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
  693. BADBLOCK_MARKER_LENGTH;
  694. break;
  695. case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
  696. #ifdef CONFIG_BCH
  697. debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
  698. /* check ecc-scheme requirements before updating ecc info */
  699. if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
  700. printf("nand: error: insufficient OOB: require=%d\n", (
  701. (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
  702. return -EINVAL;
  703. }
  704. /* check if BCH S/W library can be used for error detection */
  705. info->control = init_bch(13, 8, 0x201b);
  706. if (!info->control) {
  707. printf("nand: error: could not init_bch()\n");
  708. return -ENODEV;
  709. }
  710. /* populate ecc specific fields */
  711. memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
  712. nand->ecc.mode = NAND_ECC_HW;
  713. nand->ecc.strength = 8;
  714. nand->ecc.size = SECTOR_BYTES;
  715. nand->ecc.bytes = 13;
  716. nand->ecc.hwctl = omap_enable_hwecc;
  717. nand->ecc.correct = omap_correct_data_bch_sw;
  718. nand->ecc.calculate = omap_calculate_ecc;
  719. /* define ecc-layout */
  720. ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
  721. ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
  722. for (i = 1; i < ecclayout->eccbytes; i++) {
  723. if (i % nand->ecc.bytes)
  724. ecclayout->eccpos[i] =
  725. ecclayout->eccpos[i - 1] + 1;
  726. else
  727. ecclayout->eccpos[i] =
  728. ecclayout->eccpos[i - 1] + 2;
  729. }
  730. ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
  731. ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
  732. BADBLOCK_MARKER_LENGTH;
  733. break;
  734. #else
  735. printf("nand: error: CONFIG_BCH required for ECC\n");
  736. return -EINVAL;
  737. #endif
  738. case OMAP_ECC_BCH8_CODE_HW:
  739. #ifdef CONFIG_NAND_OMAP_ELM
  740. debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
  741. /* check ecc-scheme requirements before updating ecc info */
  742. if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
  743. printf("nand: error: insufficient OOB: require=%d\n", (
  744. (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
  745. return -EINVAL;
  746. }
  747. /* intialize ELM for ECC error detection */
  748. elm_init();
  749. info->control = NULL;
  750. /* populate ecc specific fields */
  751. memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
  752. nand->ecc.mode = NAND_ECC_HW;
  753. nand->ecc.strength = 8;
  754. nand->ecc.size = SECTOR_BYTES;
  755. nand->ecc.bytes = 14;
  756. nand->ecc.hwctl = omap_enable_hwecc;
  757. nand->ecc.correct = omap_correct_data_bch;
  758. nand->ecc.calculate = omap_calculate_ecc;
  759. nand->ecc.read_page = omap_read_page_bch;
  760. /* define ecc-layout */
  761. ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
  762. for (i = 0; i < ecclayout->eccbytes; i++)
  763. ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
  764. ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
  765. ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
  766. BADBLOCK_MARKER_LENGTH;
  767. break;
  768. #else
  769. printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
  770. return -EINVAL;
  771. #endif
  772. case OMAP_ECC_BCH16_CODE_HW:
  773. #ifdef CONFIG_NAND_OMAP_ELM
  774. debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
  775. /* check ecc-scheme requirements before updating ecc info */
  776. if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
  777. printf("nand: error: insufficient OOB: require=%d\n", (
  778. (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
  779. return -EINVAL;
  780. }
  781. /* intialize ELM for ECC error detection */
  782. elm_init();
  783. /* populate ecc specific fields */
  784. nand->ecc.mode = NAND_ECC_HW;
  785. nand->ecc.size = SECTOR_BYTES;
  786. nand->ecc.bytes = 26;
  787. nand->ecc.strength = 16;
  788. nand->ecc.hwctl = omap_enable_hwecc;
  789. nand->ecc.correct = omap_correct_data_bch;
  790. nand->ecc.calculate = omap_calculate_ecc;
  791. nand->ecc.read_page = omap_read_page_bch;
  792. /* define ecc-layout */
  793. ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
  794. for (i = 0; i < ecclayout->eccbytes; i++)
  795. ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
  796. ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
  797. ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
  798. BADBLOCK_MARKER_LENGTH;
  799. break;
  800. #else
  801. printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
  802. return -EINVAL;
  803. #endif
  804. default:
  805. debug("nand: error: ecc scheme not enabled or supported\n");
  806. return -EINVAL;
  807. }
  808. /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
  809. if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
  810. nand->ecc.layout = ecclayout;
  811. info->ecc_scheme = ecc_scheme;
  812. return 0;
  813. }
  814. #ifndef CONFIG_SPL_BUILD
  815. /*
  816. * omap_nand_switch_ecc - switch the ECC operation between different engines
  817. * (h/w and s/w) and different algorithms (hamming and BCHx)
  818. *
  819. * @hardware - true if one of the HW engines should be used
  820. * @eccstrength - the number of bits that could be corrected
  821. * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
  822. */
  823. int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
  824. {
  825. struct nand_chip *nand;
  826. struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
  827. int err = 0;
  828. if (!mtd) {
  829. printf("nand: error: no NAND devices found\n");
  830. return -ENODEV;
  831. }
  832. nand = mtd_to_nand(mtd);
  833. nand->options |= NAND_OWN_BUFFERS;
  834. nand->options &= ~NAND_SUBPAGE_READ;
  835. /* Setup the ecc configurations again */
  836. if (hardware) {
  837. if (eccstrength == 1) {
  838. err = omap_select_ecc_scheme(nand,
  839. OMAP_ECC_HAM1_CODE_HW,
  840. mtd->writesize, mtd->oobsize);
  841. } else if (eccstrength == 8) {
  842. err = omap_select_ecc_scheme(nand,
  843. OMAP_ECC_BCH8_CODE_HW,
  844. mtd->writesize, mtd->oobsize);
  845. } else if (eccstrength == 16) {
  846. err = omap_select_ecc_scheme(nand,
  847. OMAP_ECC_BCH16_CODE_HW,
  848. mtd->writesize, mtd->oobsize);
  849. } else {
  850. printf("nand: error: unsupported ECC scheme\n");
  851. return -EINVAL;
  852. }
  853. } else {
  854. if (eccstrength == 1) {
  855. err = omap_select_ecc_scheme(nand,
  856. OMAP_ECC_HAM1_CODE_SW,
  857. mtd->writesize, mtd->oobsize);
  858. } else if (eccstrength == 8) {
  859. err = omap_select_ecc_scheme(nand,
  860. OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
  861. mtd->writesize, mtd->oobsize);
  862. } else {
  863. printf("nand: error: unsupported ECC scheme\n");
  864. return -EINVAL;
  865. }
  866. }
  867. /* Update NAND handling after ECC mode switch */
  868. if (!err)
  869. err = nand_scan_tail(mtd);
  870. return err;
  871. }
  872. #endif /* CONFIG_SPL_BUILD */
  873. /*
  874. * Board-specific NAND initialization. The following members of the
  875. * argument are board-specific:
  876. * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
  877. * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
  878. * - cmd_ctrl: hardwarespecific function for accesing control-lines
  879. * - waitfunc: hardwarespecific function for accesing device ready/busy line
  880. * - ecc.hwctl: function to enable (reset) hardware ecc generator
  881. * - ecc.mode: mode of ecc, see defines
  882. * - chip_delay: chip dependent delay for transfering data from array to
  883. * read regs (tR)
  884. * - options: various chip options. They can partly be set to inform
  885. * nand_scan about special functionality. See the defines for further
  886. * explanation
  887. */
  888. int board_nand_init(struct nand_chip *nand)
  889. {
  890. int32_t gpmc_config = 0;
  891. int cs = cs_next++;
  892. int err = 0;
  893. /*
  894. * xloader/Uboot's gpmc configuration would have configured GPMC for
  895. * nand type of memory. The following logic scans and latches on to the
  896. * first CS with NAND type memory.
  897. * TBD: need to make this logic generic to handle multiple CS NAND
  898. * devices.
  899. */
  900. while (cs < GPMC_MAX_CS) {
  901. /* Check if NAND type is set */
  902. if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
  903. /* Found it!! */
  904. break;
  905. }
  906. cs++;
  907. }
  908. if (cs >= GPMC_MAX_CS) {
  909. printf("nand: error: Unable to find NAND settings in "
  910. "GPMC Configuration - quitting\n");
  911. return -ENODEV;
  912. }
  913. gpmc_config = readl(&gpmc_cfg->config);
  914. /* Disable Write protect */
  915. gpmc_config |= 0x10;
  916. writel(gpmc_config, &gpmc_cfg->config);
  917. nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  918. nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  919. omap_nand_info[cs].control = NULL;
  920. omap_nand_info[cs].cs = cs;
  921. omap_nand_info[cs].ws = wscfg[cs];
  922. nand_set_controller_data(nand, &omap_nand_info[cs]);
  923. nand->cmd_ctrl = omap_nand_hwcontrol;
  924. nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
  925. nand->chip_delay = 100;
  926. nand->ecc.layout = &omap_ecclayout;
  927. /* configure driver and controller based on NAND device bus-width */
  928. gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
  929. #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  930. nand->options |= NAND_BUSWIDTH_16;
  931. writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
  932. #else
  933. nand->options &= ~NAND_BUSWIDTH_16;
  934. writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
  935. #endif
  936. /* select ECC scheme */
  937. #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
  938. err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
  939. CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
  940. #else
  941. /* pagesize and oobsize are not required to configure sw ecc-scheme */
  942. err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
  943. 0, 0);
  944. #endif
  945. if (err)
  946. return err;
  947. #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
  948. nand->read_buf = omap_nand_read_prefetch;
  949. #else
  950. if (nand->options & NAND_BUSWIDTH_16)
  951. nand->read_buf = nand_read_buf16;
  952. else
  953. nand->read_buf = nand_read_buf;
  954. #endif
  955. nand->dev_ready = omap_dev_ready;
  956. return 0;
  957. }