nand_spl_simple.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006-2008
  4. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  5. */
  6. #include <common.h>
  7. #include <nand.h>
  8. #include <asm/io.h>
  9. #include <linux/mtd/nand_ecc.h>
  10. static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  11. static struct mtd_info *mtd;
  12. static struct nand_chip nand_chip;
  13. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  14. CONFIG_SYS_NAND_ECCSIZE)
  15. #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  16. #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  17. /*
  18. * NAND command for small page NAND devices (512)
  19. */
  20. static int nand_command(int block, int page, uint32_t offs,
  21. u8 cmd)
  22. {
  23. struct nand_chip *this = mtd_to_nand(mtd);
  24. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  25. while (!this->dev_ready(mtd))
  26. ;
  27. /* Begin command latch cycle */
  28. this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  29. /* Set ALE and clear CLE to start address cycle */
  30. /* Column address */
  31. this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  32. this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
  33. this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
  34. NAND_CTRL_ALE); /* A[24:17] */
  35. #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  36. /* One more address cycle for devices > 32MiB */
  37. this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
  38. NAND_CTRL_ALE); /* A[28:25] */
  39. #endif
  40. /* Latch in address */
  41. this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  42. /*
  43. * Wait a while for the data to be ready
  44. */
  45. while (!this->dev_ready(mtd))
  46. ;
  47. return 0;
  48. }
  49. #else
  50. /*
  51. * NAND command for large page NAND devices (2k)
  52. */
  53. static int nand_command(int block, int page, uint32_t offs,
  54. u8 cmd)
  55. {
  56. struct nand_chip *this = mtd_to_nand(mtd);
  57. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  58. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  59. unsigned int ctrl) = this->cmd_ctrl;
  60. while (!this->dev_ready(mtd))
  61. ;
  62. /* Emulate NAND_CMD_READOOB */
  63. if (cmd == NAND_CMD_READOOB) {
  64. offs += CONFIG_SYS_NAND_PAGE_SIZE;
  65. cmd = NAND_CMD_READ0;
  66. }
  67. /* Shift the offset from byte addressing to word addressing. */
  68. if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
  69. offs >>= 1;
  70. /* Begin command latch cycle */
  71. hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  72. /* Set ALE and clear CLE to start address cycle */
  73. /* Column address */
  74. hwctrl(mtd, offs & 0xff,
  75. NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  76. hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  77. /* Row address */
  78. hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  79. hwctrl(mtd, ((page_addr >> 8) & 0xff),
  80. NAND_CTRL_ALE); /* A[27:20] */
  81. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  82. /* One more address cycle for devices > 128MiB */
  83. hwctrl(mtd, (page_addr >> 16) & 0x0f,
  84. NAND_CTRL_ALE); /* A[31:28] */
  85. #endif
  86. /* Latch in address */
  87. hwctrl(mtd, NAND_CMD_READSTART,
  88. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  89. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  90. /*
  91. * Wait a while for the data to be ready
  92. */
  93. while (!this->dev_ready(mtd))
  94. ;
  95. return 0;
  96. }
  97. #endif
  98. static int nand_is_bad_block(int block)
  99. {
  100. struct nand_chip *this = mtd_to_nand(mtd);
  101. u_char bb_data[2];
  102. nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
  103. NAND_CMD_READOOB);
  104. /*
  105. * Read one byte (or two if it's a 16 bit chip).
  106. */
  107. if (this->options & NAND_BUSWIDTH_16) {
  108. this->read_buf(mtd, bb_data, 2);
  109. if (bb_data[0] != 0xff || bb_data[1] != 0xff)
  110. return 1;
  111. } else {
  112. this->read_buf(mtd, bb_data, 1);
  113. if (bb_data[0] != 0xff)
  114. return 1;
  115. }
  116. return 0;
  117. }
  118. #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
  119. static int nand_read_page(int block, int page, uchar *dst)
  120. {
  121. struct nand_chip *this = mtd_to_nand(mtd);
  122. u_char ecc_calc[ECCTOTAL];
  123. u_char ecc_code[ECCTOTAL];
  124. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  125. int i;
  126. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  127. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  128. int eccsteps = ECCSTEPS;
  129. uint8_t *p = dst;
  130. nand_command(block, page, 0, NAND_CMD_READOOB);
  131. this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  132. nand_command(block, page, 0, NAND_CMD_READ0);
  133. /* Pick the ECC bytes out of the oob data */
  134. for (i = 0; i < ECCTOTAL; i++)
  135. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  136. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  137. this->ecc.hwctl(mtd, NAND_ECC_READ);
  138. this->read_buf(mtd, p, eccsize);
  139. this->ecc.calculate(mtd, p, &ecc_calc[i]);
  140. this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  141. }
  142. return 0;
  143. }
  144. #else
  145. static int nand_read_page(int block, int page, void *dst)
  146. {
  147. struct nand_chip *this = mtd_to_nand(mtd);
  148. u_char ecc_calc[ECCTOTAL];
  149. u_char ecc_code[ECCTOTAL];
  150. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  151. int i;
  152. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  153. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  154. int eccsteps = ECCSTEPS;
  155. uint8_t *p = dst;
  156. nand_command(block, page, 0, NAND_CMD_READ0);
  157. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  158. if (this->ecc.mode != NAND_ECC_SOFT)
  159. this->ecc.hwctl(mtd, NAND_ECC_READ);
  160. this->read_buf(mtd, p, eccsize);
  161. this->ecc.calculate(mtd, p, &ecc_calc[i]);
  162. }
  163. this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  164. /* Pick the ECC bytes out of the oob data */
  165. for (i = 0; i < ECCTOTAL; i++)
  166. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  167. eccsteps = ECCSTEPS;
  168. p = dst;
  169. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  170. /* No chance to do something with the possible error message
  171. * from correct_data(). We just hope that all possible errors
  172. * are corrected by this routine.
  173. */
  174. this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  175. }
  176. return 0;
  177. }
  178. #endif
  179. /* nand_init() - initialize data to make nand usable by SPL */
  180. void nand_init(void)
  181. {
  182. /*
  183. * Init board specific nand support
  184. */
  185. mtd = nand_to_mtd(&nand_chip);
  186. nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
  187. (void __iomem *)CONFIG_SYS_NAND_BASE;
  188. board_nand_init(&nand_chip);
  189. #ifdef CONFIG_SPL_NAND_SOFTECC
  190. if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
  191. nand_chip.ecc.calculate = nand_calculate_ecc;
  192. nand_chip.ecc.correct = nand_correct_data;
  193. }
  194. #endif
  195. if (nand_chip.select_chip)
  196. nand_chip.select_chip(mtd, 0);
  197. }
  198. /* Unselect after operation */
  199. void nand_deselect(void)
  200. {
  201. if (nand_chip.select_chip)
  202. nand_chip.select_chip(mtd, -1);
  203. }
  204. #include "nand_spl_loaders.c"