mxs_nand.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 NAND flash driver
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Freescale GPMI NFC NAND Flash Driver
  10. *
  11. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  12. * Copyright (C) 2008 Embedded Alley Solutions, Inc.
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <linux/mtd/rawnand.h>
  17. #include <linux/sizes.h>
  18. #include <linux/types.h>
  19. #include <malloc.h>
  20. #include <linux/errno.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/imx-regs.h>
  24. #include <asm/mach-imx/regs-bch.h>
  25. #include <asm/mach-imx/regs-gpmi.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include "mxs_nand.h"
  28. #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
  29. #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
  30. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
  31. #else
  32. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
  33. #endif
  34. #define MXS_NAND_METADATA_SIZE 10
  35. #define MXS_NAND_BITS_PER_ECC_LEVEL 13
  36. #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
  37. #define MXS_NAND_COMMAND_BUFFER_SIZE 32
  38. #else
  39. #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
  40. #endif
  41. #define MXS_NAND_BCH_TIMEOUT 10000
  42. struct nand_ecclayout fake_ecc_layout;
  43. /*
  44. * Cache management functions
  45. */
  46. #ifndef CONFIG_SYS_DCACHE_OFF
  47. static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
  48. {
  49. uint32_t addr = (uint32_t)info->data_buf;
  50. flush_dcache_range(addr, addr + info->data_buf_size);
  51. }
  52. static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
  53. {
  54. uint32_t addr = (uint32_t)info->data_buf;
  55. invalidate_dcache_range(addr, addr + info->data_buf_size);
  56. }
  57. static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
  58. {
  59. uint32_t addr = (uint32_t)info->cmd_buf;
  60. flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
  61. }
  62. #else
  63. static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
  64. static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
  65. static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
  66. #endif
  67. static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
  68. {
  69. struct mxs_dma_desc *desc;
  70. if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
  71. printf("MXS NAND: Too many DMA descriptors requested\n");
  72. return NULL;
  73. }
  74. desc = info->desc[info->desc_index];
  75. info->desc_index++;
  76. return desc;
  77. }
  78. static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
  79. {
  80. int i;
  81. struct mxs_dma_desc *desc;
  82. for (i = 0; i < info->desc_index; i++) {
  83. desc = info->desc[i];
  84. memset(desc, 0, sizeof(struct mxs_dma_desc));
  85. desc->address = (dma_addr_t)desc;
  86. }
  87. info->desc_index = 0;
  88. }
  89. static uint32_t mxs_nand_aux_status_offset(void)
  90. {
  91. return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
  92. }
  93. static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo,
  94. uint32_t page_data_size)
  95. {
  96. uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8;
  97. uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len;
  98. uint32_t chunk_total_size_in_bits;
  99. uint32_t block_mark_chunk_number;
  100. uint32_t block_mark_chunk_bit_offset;
  101. uint32_t block_mark_bit_offset;
  102. chunk_total_size_in_bits =
  103. chunk_data_size_in_bits + chunk_ecc_size_in_bits;
  104. /* Compute the bit offset of the block mark within the physical page. */
  105. block_mark_bit_offset = page_data_size * 8;
  106. /* Subtract the metadata bits. */
  107. block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
  108. /*
  109. * Compute the chunk number (starting at zero) in which the block mark
  110. * appears.
  111. */
  112. block_mark_chunk_number =
  113. block_mark_bit_offset / chunk_total_size_in_bits;
  114. /*
  115. * Compute the bit offset of the block mark within its chunk, and
  116. * validate it.
  117. */
  118. block_mark_chunk_bit_offset = block_mark_bit_offset -
  119. (block_mark_chunk_number * chunk_total_size_in_bits);
  120. if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
  121. return -EINVAL;
  122. /*
  123. * Now that we know the chunk number in which the block mark appears,
  124. * we can subtract all the ECC bits that appear before it.
  125. */
  126. block_mark_bit_offset -=
  127. block_mark_chunk_number * chunk_ecc_size_in_bits;
  128. geo->block_mark_byte_offset = block_mark_bit_offset >> 3;
  129. geo->block_mark_bit_offset = block_mark_bit_offset & 0x7;
  130. return 0;
  131. }
  132. static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo,
  133. struct mtd_info *mtd,
  134. unsigned int ecc_strength,
  135. unsigned int ecc_step)
  136. {
  137. struct nand_chip *chip = mtd_to_nand(mtd);
  138. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  139. switch (ecc_step) {
  140. case SZ_512:
  141. geo->gf_len = 13;
  142. break;
  143. case SZ_1K:
  144. geo->gf_len = 14;
  145. break;
  146. default:
  147. return -EINVAL;
  148. }
  149. geo->ecc_chunk_size = ecc_step;
  150. geo->ecc_strength = round_up(ecc_strength, 2);
  151. /* Keep the C >= O */
  152. if (geo->ecc_chunk_size < mtd->oobsize)
  153. return -EINVAL;
  154. if (geo->ecc_strength > nand_info->max_ecc_strength_supported)
  155. return -EINVAL;
  156. geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
  157. return 0;
  158. }
  159. static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo,
  160. struct mtd_info *mtd)
  161. {
  162. struct nand_chip *chip = mtd_to_nand(mtd);
  163. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  164. /* The default for the length of Galois Field. */
  165. geo->gf_len = 13;
  166. /* The default for chunk size. */
  167. geo->ecc_chunk_size = 512;
  168. if (geo->ecc_chunk_size < mtd->oobsize) {
  169. geo->gf_len = 14;
  170. geo->ecc_chunk_size *= 2;
  171. }
  172. if (mtd->oobsize > geo->ecc_chunk_size) {
  173. printf("Not support the NAND chips whose oob size is larger then %d bytes!\n",
  174. geo->ecc_chunk_size);
  175. return -EINVAL;
  176. }
  177. geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
  178. /*
  179. * Determine the ECC layout with the formula:
  180. * ECC bits per chunk = (total page spare data bits) /
  181. * (bits per ECC level) / (chunks per page)
  182. * where:
  183. * total page spare data bits =
  184. * (page oob size - meta data size) * (bits per byte)
  185. */
  186. geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
  187. / (geo->gf_len * geo->ecc_chunk_count);
  188. geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
  189. nand_info->max_ecc_strength_supported);
  190. return 0;
  191. }
  192. /*
  193. * Wait for BCH complete IRQ and clear the IRQ
  194. */
  195. static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
  196. {
  197. int timeout = MXS_NAND_BCH_TIMEOUT;
  198. int ret;
  199. ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
  200. BCH_CTRL_COMPLETE_IRQ, timeout);
  201. writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
  202. return ret;
  203. }
  204. /*
  205. * This is the function that we install in the cmd_ctrl function pointer of the
  206. * owning struct nand_chip. The only functions in the reference implementation
  207. * that use these functions pointers are cmdfunc and select_chip.
  208. *
  209. * In this driver, we implement our own select_chip, so this function will only
  210. * be called by the reference implementation's cmdfunc. For this reason, we can
  211. * ignore the chip enable bit and concentrate only on sending bytes to the NAND
  212. * Flash.
  213. */
  214. static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
  215. {
  216. struct nand_chip *nand = mtd_to_nand(mtd);
  217. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  218. struct mxs_dma_desc *d;
  219. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  220. int ret;
  221. /*
  222. * If this condition is true, something is _VERY_ wrong in MTD
  223. * subsystem!
  224. */
  225. if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
  226. printf("MXS NAND: Command queue too long\n");
  227. return;
  228. }
  229. /*
  230. * Every operation begins with a command byte and a series of zero or
  231. * more address bytes. These are distinguished by either the Address
  232. * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
  233. * asserted. When MTD is ready to execute the command, it will
  234. * deasert both latch enables.
  235. *
  236. * Rather than run a separate DMA operation for every single byte, we
  237. * queue them up and run a single DMA operation for the entire series
  238. * of command and data bytes.
  239. */
  240. if (ctrl & (NAND_ALE | NAND_CLE)) {
  241. if (data != NAND_CMD_NONE)
  242. nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
  243. return;
  244. }
  245. /*
  246. * If control arrives here, MTD has deasserted both the ALE and CLE,
  247. * which means it's ready to run an operation. Check if we have any
  248. * bytes to send.
  249. */
  250. if (nand_info->cmd_queue_len == 0)
  251. return;
  252. /* Compile the DMA descriptor -- a descriptor that sends command. */
  253. d = mxs_nand_get_dma_desc(nand_info);
  254. d->cmd.data =
  255. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  256. MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
  257. MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  258. (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
  259. d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
  260. d->cmd.pio_words[0] =
  261. GPMI_CTRL0_COMMAND_MODE_WRITE |
  262. GPMI_CTRL0_WORD_LENGTH |
  263. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  264. GPMI_CTRL0_ADDRESS_NAND_CLE |
  265. GPMI_CTRL0_ADDRESS_INCREMENT |
  266. nand_info->cmd_queue_len;
  267. mxs_dma_desc_append(channel, d);
  268. /* Flush caches */
  269. mxs_nand_flush_cmd_buf(nand_info);
  270. /* Execute the DMA chain. */
  271. ret = mxs_dma_go(channel);
  272. if (ret)
  273. printf("MXS NAND: Error sending command\n");
  274. mxs_nand_return_dma_descs(nand_info);
  275. /* Reset the command queue. */
  276. nand_info->cmd_queue_len = 0;
  277. }
  278. /*
  279. * Test if the NAND flash is ready.
  280. */
  281. static int mxs_nand_device_ready(struct mtd_info *mtd)
  282. {
  283. struct nand_chip *chip = mtd_to_nand(mtd);
  284. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  285. uint32_t tmp;
  286. tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
  287. tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
  288. return tmp & 1;
  289. }
  290. /*
  291. * Select the NAND chip.
  292. */
  293. static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
  294. {
  295. struct nand_chip *nand = mtd_to_nand(mtd);
  296. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  297. nand_info->cur_chip = chip;
  298. }
  299. /*
  300. * Handle block mark swapping.
  301. *
  302. * Note that, when this function is called, it doesn't know whether it's
  303. * swapping the block mark, or swapping it *back* -- but it doesn't matter
  304. * because the the operation is the same.
  305. */
  306. static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
  307. uint8_t *data_buf, uint8_t *oob_buf)
  308. {
  309. uint32_t bit_offset = geo->block_mark_bit_offset;
  310. uint32_t buf_offset = geo->block_mark_byte_offset;
  311. uint32_t src;
  312. uint32_t dst;
  313. /*
  314. * Get the byte from the data area that overlays the block mark. Since
  315. * the ECC engine applies its own view to the bits in the page, the
  316. * physical block mark won't (in general) appear on a byte boundary in
  317. * the data.
  318. */
  319. src = data_buf[buf_offset] >> bit_offset;
  320. src |= data_buf[buf_offset + 1] << (8 - bit_offset);
  321. dst = oob_buf[0];
  322. oob_buf[0] = src;
  323. data_buf[buf_offset] &= ~(0xff << bit_offset);
  324. data_buf[buf_offset + 1] &= 0xff << bit_offset;
  325. data_buf[buf_offset] |= dst << bit_offset;
  326. data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
  327. }
  328. /*
  329. * Read data from NAND.
  330. */
  331. static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
  332. {
  333. struct nand_chip *nand = mtd_to_nand(mtd);
  334. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  335. struct mxs_dma_desc *d;
  336. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  337. int ret;
  338. if (length > NAND_MAX_PAGESIZE) {
  339. printf("MXS NAND: DMA buffer too big\n");
  340. return;
  341. }
  342. if (!buf) {
  343. printf("MXS NAND: DMA buffer is NULL\n");
  344. return;
  345. }
  346. /* Compile the DMA descriptor - a descriptor that reads data. */
  347. d = mxs_nand_get_dma_desc(nand_info);
  348. d->cmd.data =
  349. MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
  350. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  351. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  352. (length << MXS_DMA_DESC_BYTES_OFFSET);
  353. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  354. d->cmd.pio_words[0] =
  355. GPMI_CTRL0_COMMAND_MODE_READ |
  356. GPMI_CTRL0_WORD_LENGTH |
  357. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  358. GPMI_CTRL0_ADDRESS_NAND_DATA |
  359. length;
  360. mxs_dma_desc_append(channel, d);
  361. /*
  362. * A DMA descriptor that waits for the command to end and the chip to
  363. * become ready.
  364. *
  365. * I think we actually should *not* be waiting for the chip to become
  366. * ready because, after all, we don't care. I think the original code
  367. * did that and no one has re-thought it yet.
  368. */
  369. d = mxs_nand_get_dma_desc(nand_info);
  370. d->cmd.data =
  371. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  372. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
  373. MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  374. d->cmd.address = 0;
  375. d->cmd.pio_words[0] =
  376. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  377. GPMI_CTRL0_WORD_LENGTH |
  378. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  379. GPMI_CTRL0_ADDRESS_NAND_DATA;
  380. mxs_dma_desc_append(channel, d);
  381. /* Invalidate caches */
  382. mxs_nand_inval_data_buf(nand_info);
  383. /* Execute the DMA chain. */
  384. ret = mxs_dma_go(channel);
  385. if (ret) {
  386. printf("MXS NAND: DMA read error\n");
  387. goto rtn;
  388. }
  389. /* Invalidate caches */
  390. mxs_nand_inval_data_buf(nand_info);
  391. memcpy(buf, nand_info->data_buf, length);
  392. rtn:
  393. mxs_nand_return_dma_descs(nand_info);
  394. }
  395. /*
  396. * Write data to NAND.
  397. */
  398. static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  399. int length)
  400. {
  401. struct nand_chip *nand = mtd_to_nand(mtd);
  402. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  403. struct mxs_dma_desc *d;
  404. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  405. int ret;
  406. if (length > NAND_MAX_PAGESIZE) {
  407. printf("MXS NAND: DMA buffer too big\n");
  408. return;
  409. }
  410. if (!buf) {
  411. printf("MXS NAND: DMA buffer is NULL\n");
  412. return;
  413. }
  414. memcpy(nand_info->data_buf, buf, length);
  415. /* Compile the DMA descriptor - a descriptor that writes data. */
  416. d = mxs_nand_get_dma_desc(nand_info);
  417. d->cmd.data =
  418. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  419. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  420. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  421. (length << MXS_DMA_DESC_BYTES_OFFSET);
  422. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  423. d->cmd.pio_words[0] =
  424. GPMI_CTRL0_COMMAND_MODE_WRITE |
  425. GPMI_CTRL0_WORD_LENGTH |
  426. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  427. GPMI_CTRL0_ADDRESS_NAND_DATA |
  428. length;
  429. mxs_dma_desc_append(channel, d);
  430. /* Flush caches */
  431. mxs_nand_flush_data_buf(nand_info);
  432. /* Execute the DMA chain. */
  433. ret = mxs_dma_go(channel);
  434. if (ret)
  435. printf("MXS NAND: DMA write error\n");
  436. mxs_nand_return_dma_descs(nand_info);
  437. }
  438. /*
  439. * Read a single byte from NAND.
  440. */
  441. static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
  442. {
  443. uint8_t buf;
  444. mxs_nand_read_buf(mtd, &buf, 1);
  445. return buf;
  446. }
  447. /*
  448. * Read a page from NAND.
  449. */
  450. static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
  451. uint8_t *buf, int oob_required,
  452. int page)
  453. {
  454. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  455. struct bch_geometry *geo = &nand_info->bch_geometry;
  456. struct mxs_dma_desc *d;
  457. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  458. uint32_t corrected = 0, failed = 0;
  459. uint8_t *status;
  460. int i, ret;
  461. /* Compile the DMA descriptor - wait for ready. */
  462. d = mxs_nand_get_dma_desc(nand_info);
  463. d->cmd.data =
  464. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  465. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  466. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  467. d->cmd.address = 0;
  468. d->cmd.pio_words[0] =
  469. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  470. GPMI_CTRL0_WORD_LENGTH |
  471. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  472. GPMI_CTRL0_ADDRESS_NAND_DATA;
  473. mxs_dma_desc_append(channel, d);
  474. /* Compile the DMA descriptor - enable the BCH block and read. */
  475. d = mxs_nand_get_dma_desc(nand_info);
  476. d->cmd.data =
  477. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  478. MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  479. d->cmd.address = 0;
  480. d->cmd.pio_words[0] =
  481. GPMI_CTRL0_COMMAND_MODE_READ |
  482. GPMI_CTRL0_WORD_LENGTH |
  483. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  484. GPMI_CTRL0_ADDRESS_NAND_DATA |
  485. (mtd->writesize + mtd->oobsize);
  486. d->cmd.pio_words[1] = 0;
  487. d->cmd.pio_words[2] =
  488. GPMI_ECCCTRL_ENABLE_ECC |
  489. GPMI_ECCCTRL_ECC_CMD_DECODE |
  490. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  491. d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
  492. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  493. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  494. mxs_dma_desc_append(channel, d);
  495. /* Compile the DMA descriptor - disable the BCH block. */
  496. d = mxs_nand_get_dma_desc(nand_info);
  497. d->cmd.data =
  498. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  499. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  500. (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  501. d->cmd.address = 0;
  502. d->cmd.pio_words[0] =
  503. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  504. GPMI_CTRL0_WORD_LENGTH |
  505. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  506. GPMI_CTRL0_ADDRESS_NAND_DATA |
  507. (mtd->writesize + mtd->oobsize);
  508. d->cmd.pio_words[1] = 0;
  509. d->cmd.pio_words[2] = 0;
  510. mxs_dma_desc_append(channel, d);
  511. /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
  512. d = mxs_nand_get_dma_desc(nand_info);
  513. d->cmd.data =
  514. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  515. MXS_DMA_DESC_DEC_SEM;
  516. d->cmd.address = 0;
  517. mxs_dma_desc_append(channel, d);
  518. /* Invalidate caches */
  519. mxs_nand_inval_data_buf(nand_info);
  520. /* Execute the DMA chain. */
  521. ret = mxs_dma_go(channel);
  522. if (ret) {
  523. printf("MXS NAND: DMA read error\n");
  524. goto rtn;
  525. }
  526. ret = mxs_nand_wait_for_bch_complete(nand_info);
  527. if (ret) {
  528. printf("MXS NAND: BCH read timeout\n");
  529. goto rtn;
  530. }
  531. /* Invalidate caches */
  532. mxs_nand_inval_data_buf(nand_info);
  533. /* Read DMA completed, now do the mark swapping. */
  534. mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
  535. /* Loop over status bytes, accumulating ECC status. */
  536. status = nand_info->oob_buf + mxs_nand_aux_status_offset();
  537. for (i = 0; i < geo->ecc_chunk_count; i++) {
  538. if (status[i] == 0x00)
  539. continue;
  540. if (status[i] == 0xff)
  541. continue;
  542. if (status[i] == 0xfe) {
  543. failed++;
  544. continue;
  545. }
  546. corrected += status[i];
  547. }
  548. /* Propagate ECC status to the owning MTD. */
  549. mtd->ecc_stats.failed += failed;
  550. mtd->ecc_stats.corrected += corrected;
  551. /*
  552. * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
  553. * details about our policy for delivering the OOB.
  554. *
  555. * We fill the caller's buffer with set bits, and then copy the block
  556. * mark to the caller's buffer. Note that, if block mark swapping was
  557. * necessary, it has already been done, so we can rely on the first
  558. * byte of the auxiliary buffer to contain the block mark.
  559. */
  560. memset(nand->oob_poi, 0xff, mtd->oobsize);
  561. nand->oob_poi[0] = nand_info->oob_buf[0];
  562. memcpy(buf, nand_info->data_buf, mtd->writesize);
  563. rtn:
  564. mxs_nand_return_dma_descs(nand_info);
  565. return ret;
  566. }
  567. /*
  568. * Write a page to NAND.
  569. */
  570. static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
  571. struct nand_chip *nand, const uint8_t *buf,
  572. int oob_required, int page)
  573. {
  574. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  575. struct bch_geometry *geo = &nand_info->bch_geometry;
  576. struct mxs_dma_desc *d;
  577. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  578. int ret;
  579. memcpy(nand_info->data_buf, buf, mtd->writesize);
  580. memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
  581. /* Handle block mark swapping. */
  582. mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
  583. /* Compile the DMA descriptor - write data. */
  584. d = mxs_nand_get_dma_desc(nand_info);
  585. d->cmd.data =
  586. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  587. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  588. (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  589. d->cmd.address = 0;
  590. d->cmd.pio_words[0] =
  591. GPMI_CTRL0_COMMAND_MODE_WRITE |
  592. GPMI_CTRL0_WORD_LENGTH |
  593. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  594. GPMI_CTRL0_ADDRESS_NAND_DATA;
  595. d->cmd.pio_words[1] = 0;
  596. d->cmd.pio_words[2] =
  597. GPMI_ECCCTRL_ENABLE_ECC |
  598. GPMI_ECCCTRL_ECC_CMD_ENCODE |
  599. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  600. d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
  601. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  602. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  603. mxs_dma_desc_append(channel, d);
  604. /* Flush caches */
  605. mxs_nand_flush_data_buf(nand_info);
  606. /* Execute the DMA chain. */
  607. ret = mxs_dma_go(channel);
  608. if (ret) {
  609. printf("MXS NAND: DMA write error\n");
  610. goto rtn;
  611. }
  612. ret = mxs_nand_wait_for_bch_complete(nand_info);
  613. if (ret) {
  614. printf("MXS NAND: BCH write timeout\n");
  615. goto rtn;
  616. }
  617. rtn:
  618. mxs_nand_return_dma_descs(nand_info);
  619. return 0;
  620. }
  621. /*
  622. * Read OOB from NAND.
  623. *
  624. * This function is a veneer that replaces the function originally installed by
  625. * the NAND Flash MTD code.
  626. */
  627. static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
  628. struct mtd_oob_ops *ops)
  629. {
  630. struct nand_chip *chip = mtd_to_nand(mtd);
  631. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  632. int ret;
  633. if (ops->mode == MTD_OPS_RAW)
  634. nand_info->raw_oob_mode = 1;
  635. else
  636. nand_info->raw_oob_mode = 0;
  637. ret = nand_info->hooked_read_oob(mtd, from, ops);
  638. nand_info->raw_oob_mode = 0;
  639. return ret;
  640. }
  641. /*
  642. * Write OOB to NAND.
  643. *
  644. * This function is a veneer that replaces the function originally installed by
  645. * the NAND Flash MTD code.
  646. */
  647. static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
  648. struct mtd_oob_ops *ops)
  649. {
  650. struct nand_chip *chip = mtd_to_nand(mtd);
  651. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  652. int ret;
  653. if (ops->mode == MTD_OPS_RAW)
  654. nand_info->raw_oob_mode = 1;
  655. else
  656. nand_info->raw_oob_mode = 0;
  657. ret = nand_info->hooked_write_oob(mtd, to, ops);
  658. nand_info->raw_oob_mode = 0;
  659. return ret;
  660. }
  661. /*
  662. * Mark a block bad in NAND.
  663. *
  664. * This function is a veneer that replaces the function originally installed by
  665. * the NAND Flash MTD code.
  666. */
  667. static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
  668. {
  669. struct nand_chip *chip = mtd_to_nand(mtd);
  670. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  671. int ret;
  672. nand_info->marking_block_bad = 1;
  673. ret = nand_info->hooked_block_markbad(mtd, ofs);
  674. nand_info->marking_block_bad = 0;
  675. return ret;
  676. }
  677. /*
  678. * There are several places in this driver where we have to handle the OOB and
  679. * block marks. This is the function where things are the most complicated, so
  680. * this is where we try to explain it all. All the other places refer back to
  681. * here.
  682. *
  683. * These are the rules, in order of decreasing importance:
  684. *
  685. * 1) Nothing the caller does can be allowed to imperil the block mark, so all
  686. * write operations take measures to protect it.
  687. *
  688. * 2) In read operations, the first byte of the OOB we return must reflect the
  689. * true state of the block mark, no matter where that block mark appears in
  690. * the physical page.
  691. *
  692. * 3) ECC-based read operations return an OOB full of set bits (since we never
  693. * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
  694. * return).
  695. *
  696. * 4) "Raw" read operations return a direct view of the physical bytes in the
  697. * page, using the conventional definition of which bytes are data and which
  698. * are OOB. This gives the caller a way to see the actual, physical bytes
  699. * in the page, without the distortions applied by our ECC engine.
  700. *
  701. * What we do for this specific read operation depends on whether we're doing
  702. * "raw" read, or an ECC-based read.
  703. *
  704. * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
  705. * easy. When reading a page, for example, the NAND Flash MTD code calls our
  706. * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
  707. * ECC-based or raw view of the page is implicit in which function it calls
  708. * (there is a similar pair of ECC-based/raw functions for writing).
  709. *
  710. * Since MTD assumes the OOB is not covered by ECC, there is no pair of
  711. * ECC-based/raw functions for reading or or writing the OOB. The fact that the
  712. * caller wants an ECC-based or raw view of the page is not propagated down to
  713. * this driver.
  714. *
  715. * Since our OOB *is* covered by ECC, we need this information. So, we hook the
  716. * ecc.read_oob and ecc.write_oob function pointers in the owning
  717. * struct mtd_info with our own functions. These hook functions set the
  718. * raw_oob_mode field so that, when control finally arrives here, we'll know
  719. * what to do.
  720. */
  721. static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
  722. int page)
  723. {
  724. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  725. /*
  726. * First, fill in the OOB buffer. If we're doing a raw read, we need to
  727. * get the bytes from the physical page. If we're not doing a raw read,
  728. * we need to fill the buffer with set bits.
  729. */
  730. if (nand_info->raw_oob_mode) {
  731. /*
  732. * If control arrives here, we're doing a "raw" read. Send the
  733. * command to read the conventional OOB and read it.
  734. */
  735. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  736. nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
  737. } else {
  738. /*
  739. * If control arrives here, we're not doing a "raw" read. Fill
  740. * the OOB buffer with set bits and correct the block mark.
  741. */
  742. memset(nand->oob_poi, 0xff, mtd->oobsize);
  743. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  744. mxs_nand_read_buf(mtd, nand->oob_poi, 1);
  745. }
  746. return 0;
  747. }
  748. /*
  749. * Write OOB data to NAND.
  750. */
  751. static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
  752. int page)
  753. {
  754. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  755. uint8_t block_mark = 0;
  756. /*
  757. * There are fundamental incompatibilities between the i.MX GPMI NFC and
  758. * the NAND Flash MTD model that make it essentially impossible to write
  759. * the out-of-band bytes.
  760. *
  761. * We permit *ONE* exception. If the *intent* of writing the OOB is to
  762. * mark a block bad, we can do that.
  763. */
  764. if (!nand_info->marking_block_bad) {
  765. printf("NXS NAND: Writing OOB isn't supported\n");
  766. return -EIO;
  767. }
  768. /* Write the block mark. */
  769. nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  770. nand->write_buf(mtd, &block_mark, 1);
  771. nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  772. /* Check if it worked. */
  773. if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
  774. return -EIO;
  775. return 0;
  776. }
  777. /*
  778. * Claims all blocks are good.
  779. *
  780. * In principle, this function is *only* called when the NAND Flash MTD system
  781. * isn't allowed to keep an in-memory bad block table, so it is forced to ask
  782. * the driver for bad block information.
  783. *
  784. * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
  785. * this function is *only* called when we take it away.
  786. *
  787. * Thus, this function is only called when we want *all* blocks to look good,
  788. * so it *always* return success.
  789. */
  790. static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  791. {
  792. return 0;
  793. }
  794. static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo)
  795. {
  796. struct nand_chip *chip = mtd_to_nand(mtd);
  797. struct nand_chip *nand = mtd_to_nand(mtd);
  798. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  799. if (chip->ecc.strength > 0 && chip->ecc.size > 0)
  800. return mxs_nand_calc_ecc_layout_by_info(geo, mtd,
  801. chip->ecc.strength, chip->ecc.size);
  802. if (nand_info->use_minimum_ecc ||
  803. mxs_nand_calc_ecc_layout(geo, mtd)) {
  804. if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
  805. return -EINVAL;
  806. return mxs_nand_calc_ecc_layout_by_info(geo, mtd,
  807. chip->ecc_strength_ds, chip->ecc_step_ds);
  808. }
  809. return 0;
  810. }
  811. /*
  812. * At this point, the physical NAND Flash chips have been identified and
  813. * counted, so we know the physical geometry. This enables us to make some
  814. * important configuration decisions.
  815. *
  816. * The return value of this function propagates directly back to this driver's
  817. * board_nand_init(). Anything other than zero will cause this driver to
  818. * tear everything down and declare failure.
  819. */
  820. int mxs_nand_setup_ecc(struct mtd_info *mtd)
  821. {
  822. struct nand_chip *nand = mtd_to_nand(mtd);
  823. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  824. struct bch_geometry *geo = &nand_info->bch_geometry;
  825. struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
  826. uint32_t tmp;
  827. int ret;
  828. ret = mxs_nand_set_geometry(mtd, geo);
  829. if (ret)
  830. return ret;
  831. mxs_nand_calc_mark_offset(geo, mtd->writesize);
  832. /* Configure BCH and set NFC geometry */
  833. mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  834. /* Configure layout 0 */
  835. tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
  836. tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
  837. tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
  838. tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  839. tmp |= (geo->gf_len == 14 ? 1 : 0) <<
  840. BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
  841. writel(tmp, &bch_regs->hw_bch_flash0layout0);
  842. tmp = (mtd->writesize + mtd->oobsize)
  843. << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
  844. tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
  845. tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  846. tmp |= (geo->gf_len == 14 ? 1 : 0) <<
  847. BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
  848. writel(tmp, &bch_regs->hw_bch_flash0layout1);
  849. /* Set *all* chip selects to use layout 0 */
  850. writel(0, &bch_regs->hw_bch_layoutselect);
  851. /* Enable BCH complete interrupt */
  852. writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
  853. /* Hook some operations at the MTD level. */
  854. if (mtd->_read_oob != mxs_nand_hook_read_oob) {
  855. nand_info->hooked_read_oob = mtd->_read_oob;
  856. mtd->_read_oob = mxs_nand_hook_read_oob;
  857. }
  858. if (mtd->_write_oob != mxs_nand_hook_write_oob) {
  859. nand_info->hooked_write_oob = mtd->_write_oob;
  860. mtd->_write_oob = mxs_nand_hook_write_oob;
  861. }
  862. if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
  863. nand_info->hooked_block_markbad = mtd->_block_markbad;
  864. mtd->_block_markbad = mxs_nand_hook_block_markbad;
  865. }
  866. return 0;
  867. }
  868. /*
  869. * Allocate DMA buffers
  870. */
  871. int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
  872. {
  873. uint8_t *buf;
  874. const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
  875. nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
  876. /* DMA buffers */
  877. buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
  878. if (!buf) {
  879. printf("MXS NAND: Error allocating DMA buffers\n");
  880. return -ENOMEM;
  881. }
  882. memset(buf, 0, nand_info->data_buf_size);
  883. nand_info->data_buf = buf;
  884. nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
  885. /* Command buffers */
  886. nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
  887. MXS_NAND_COMMAND_BUFFER_SIZE);
  888. if (!nand_info->cmd_buf) {
  889. free(buf);
  890. printf("MXS NAND: Error allocating command buffers\n");
  891. return -ENOMEM;
  892. }
  893. memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
  894. nand_info->cmd_queue_len = 0;
  895. return 0;
  896. }
  897. /*
  898. * Initializes the NFC hardware.
  899. */
  900. int mxs_nand_init_dma(struct mxs_nand_info *info)
  901. {
  902. int i = 0, j, ret = 0;
  903. info->desc = malloc(sizeof(struct mxs_dma_desc *) *
  904. MXS_NAND_DMA_DESCRIPTOR_COUNT);
  905. if (!info->desc) {
  906. ret = -ENOMEM;
  907. goto err1;
  908. }
  909. /* Allocate the DMA descriptors. */
  910. for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
  911. info->desc[i] = mxs_dma_desc_alloc();
  912. if (!info->desc[i]) {
  913. ret = -ENOMEM;
  914. goto err2;
  915. }
  916. }
  917. /* Init the DMA controller. */
  918. mxs_dma_init();
  919. for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
  920. j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
  921. ret = mxs_dma_init_channel(j);
  922. if (ret)
  923. goto err3;
  924. }
  925. /* Reset the GPMI block. */
  926. mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
  927. mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
  928. /*
  929. * Choose NAND mode, set IRQ polarity, disable write protection and
  930. * select BCH ECC.
  931. */
  932. clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
  933. GPMI_CTRL1_GPMI_MODE,
  934. GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
  935. GPMI_CTRL1_BCH_MODE);
  936. return 0;
  937. err3:
  938. for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
  939. mxs_dma_release(j);
  940. err2:
  941. for (--i; i >= 0; i--)
  942. mxs_dma_desc_free(info->desc[i]);
  943. free(info->desc);
  944. err1:
  945. if (ret == -ENOMEM)
  946. printf("MXS NAND: Unable to allocate DMA descriptors\n");
  947. return ret;
  948. }
  949. int mxs_nand_init_spl(struct nand_chip *nand)
  950. {
  951. struct mxs_nand_info *nand_info;
  952. int err;
  953. nand_info = malloc(sizeof(struct mxs_nand_info));
  954. if (!nand_info) {
  955. printf("MXS NAND: Failed to allocate private data\n");
  956. return -ENOMEM;
  957. }
  958. memset(nand_info, 0, sizeof(struct mxs_nand_info));
  959. nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  960. nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  961. err = mxs_nand_alloc_buffers(nand_info);
  962. if (err)
  963. return err;
  964. err = mxs_nand_init_dma(nand_info);
  965. if (err)
  966. return err;
  967. nand_set_controller_data(nand, nand_info);
  968. nand->options |= NAND_NO_SUBPAGE_WRITE;
  969. nand->cmd_ctrl = mxs_nand_cmd_ctrl;
  970. nand->dev_ready = mxs_nand_device_ready;
  971. nand->select_chip = mxs_nand_select_chip;
  972. nand->read_byte = mxs_nand_read_byte;
  973. nand->read_buf = mxs_nand_read_buf;
  974. nand->ecc.read_page = mxs_nand_ecc_read_page;
  975. nand->ecc.mode = NAND_ECC_HW;
  976. nand->ecc.bytes = 9;
  977. nand->ecc.size = 512;
  978. nand->ecc.strength = 8;
  979. return 0;
  980. }
  981. int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info)
  982. {
  983. struct mtd_info *mtd;
  984. struct nand_chip *nand;
  985. int err;
  986. nand = &nand_info->chip;
  987. mtd = nand_to_mtd(nand);
  988. err = mxs_nand_alloc_buffers(nand_info);
  989. if (err)
  990. return err;
  991. err = mxs_nand_init_dma(nand_info);
  992. if (err)
  993. goto err_free_buffers;
  994. memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
  995. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  996. nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
  997. #endif
  998. nand_set_controller_data(nand, nand_info);
  999. nand->options |= NAND_NO_SUBPAGE_WRITE;
  1000. if (nand_info->dev)
  1001. nand->flash_node = dev_of_offset(nand_info->dev);
  1002. nand->cmd_ctrl = mxs_nand_cmd_ctrl;
  1003. nand->dev_ready = mxs_nand_device_ready;
  1004. nand->select_chip = mxs_nand_select_chip;
  1005. nand->block_bad = mxs_nand_block_bad;
  1006. nand->read_byte = mxs_nand_read_byte;
  1007. nand->read_buf = mxs_nand_read_buf;
  1008. nand->write_buf = mxs_nand_write_buf;
  1009. /* first scan to find the device and get the page size */
  1010. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
  1011. goto err_free_buffers;
  1012. if (mxs_nand_setup_ecc(mtd))
  1013. goto err_free_buffers;
  1014. nand->ecc.read_page = mxs_nand_ecc_read_page;
  1015. nand->ecc.write_page = mxs_nand_ecc_write_page;
  1016. nand->ecc.read_oob = mxs_nand_ecc_read_oob;
  1017. nand->ecc.write_oob = mxs_nand_ecc_write_oob;
  1018. nand->ecc.layout = &fake_ecc_layout;
  1019. nand->ecc.mode = NAND_ECC_HW;
  1020. nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size;
  1021. nand->ecc.strength = nand_info->bch_geometry.ecc_strength;
  1022. /* second phase scan */
  1023. err = nand_scan_tail(mtd);
  1024. if (err)
  1025. goto err_free_buffers;
  1026. err = nand_register(0, mtd);
  1027. if (err)
  1028. goto err_free_buffers;
  1029. return 0;
  1030. err_free_buffers:
  1031. free(nand_info->data_buf);
  1032. free(nand_info->cmd_buf);
  1033. return err;
  1034. }
  1035. #ifndef CONFIG_NAND_MXS_DT
  1036. void board_nand_init(void)
  1037. {
  1038. struct mxs_nand_info *nand_info;
  1039. nand_info = malloc(sizeof(struct mxs_nand_info));
  1040. if (!nand_info) {
  1041. printf("MXS NAND: Failed to allocate private data\n");
  1042. return;
  1043. }
  1044. memset(nand_info, 0, sizeof(struct mxs_nand_info));
  1045. nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  1046. nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1047. /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
  1048. if (is_mx6sx() || is_mx7())
  1049. nand_info->max_ecc_strength_supported = 62;
  1050. else
  1051. nand_info->max_ecc_strength_supported = 40;
  1052. #ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC
  1053. nand_info->use_minimum_ecc = true;
  1054. #endif
  1055. if (mxs_nand_init_ctrl(nand_info) < 0)
  1056. goto err;
  1057. return;
  1058. err:
  1059. free(nand_info);
  1060. }
  1061. #endif