mxc_nand.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004-2007 Freescale Semiconductor, Inc.
  4. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  5. * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
  6. */
  7. #include <common.h>
  8. #include <nand.h>
  9. #include <linux/err.h>
  10. #include <asm/io.h>
  11. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  12. defined(CONFIG_MX51) || defined(CONFIG_MX53)
  13. #include <asm/arch/imx-regs.h>
  14. #endif
  15. #include "mxc_nand.h"
  16. #define DRIVER_NAME "mxc_nand"
  17. struct mxc_nand_host {
  18. struct nand_chip *nand;
  19. struct mxc_nand_regs __iomem *regs;
  20. #ifdef MXC_NFC_V3_2
  21. struct mxc_nand_ip_regs __iomem *ip_regs;
  22. #endif
  23. int spare_only;
  24. int status_request;
  25. int pagesize_2k;
  26. int clk_act;
  27. uint16_t col_addr;
  28. unsigned int page_addr;
  29. };
  30. static struct mxc_nand_host mxc_host;
  31. static struct mxc_nand_host *host = &mxc_host;
  32. /* Define delays in microsec for NAND device operations */
  33. #define TROP_US_DELAY 2000
  34. /* Macros to get byte and bit positions of ECC */
  35. #define COLPOS(x) ((x) >> 3)
  36. #define BITPOS(x) ((x) & 0xf)
  37. /* Define single bit Error positions in Main & Spare area */
  38. #define MAIN_SINGLEBIT_ERROR 0x4
  39. #define SPARE_SINGLEBIT_ERROR 0x1
  40. /* OOB placement block for use with hardware ecc generation */
  41. #if defined(MXC_NFC_V1)
  42. #ifndef CONFIG_SYS_NAND_LARGEPAGE
  43. static struct nand_ecclayout nand_hw_eccoob = {
  44. .eccbytes = 5,
  45. .eccpos = {6, 7, 8, 9, 10},
  46. .oobfree = { {0, 5}, {11, 5}, }
  47. };
  48. #else
  49. static struct nand_ecclayout nand_hw_eccoob2k = {
  50. .eccbytes = 20,
  51. .eccpos = {
  52. 6, 7, 8, 9, 10,
  53. 22, 23, 24, 25, 26,
  54. 38, 39, 40, 41, 42,
  55. 54, 55, 56, 57, 58,
  56. },
  57. .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  58. };
  59. #endif
  60. #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  61. #ifndef CONFIG_SYS_NAND_LARGEPAGE
  62. static struct nand_ecclayout nand_hw_eccoob = {
  63. .eccbytes = 9,
  64. .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  65. .oobfree = { {2, 5} }
  66. };
  67. #else
  68. static struct nand_ecclayout nand_hw_eccoob2k = {
  69. .eccbytes = 36,
  70. .eccpos = {
  71. 7, 8, 9, 10, 11, 12, 13, 14, 15,
  72. 23, 24, 25, 26, 27, 28, 29, 30, 31,
  73. 39, 40, 41, 42, 43, 44, 45, 46, 47,
  74. 55, 56, 57, 58, 59, 60, 61, 62, 63,
  75. },
  76. .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  77. };
  78. #endif
  79. #endif
  80. static int is_16bit_nand(void)
  81. {
  82. #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  83. return 1;
  84. #else
  85. return 0;
  86. #endif
  87. }
  88. static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
  89. {
  90. uint32_t *d = dest;
  91. size >>= 2;
  92. while (size--)
  93. __raw_writel(__raw_readl(source++), d++);
  94. return dest;
  95. }
  96. /*
  97. * This function polls the NANDFC to wait for the basic operation to
  98. * complete by checking the INT bit.
  99. */
  100. static void wait_op_done(struct mxc_nand_host *host, int max_retries,
  101. uint16_t param)
  102. {
  103. uint32_t tmp;
  104. while (max_retries-- > 0) {
  105. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  106. tmp = readnfc(&host->regs->config2);
  107. if (tmp & NFC_V1_V2_CONFIG2_INT) {
  108. tmp &= ~NFC_V1_V2_CONFIG2_INT;
  109. writenfc(tmp, &host->regs->config2);
  110. #elif defined(MXC_NFC_V3_2)
  111. tmp = readnfc(&host->ip_regs->ipc);
  112. if (tmp & NFC_V3_IPC_INT) {
  113. tmp &= ~NFC_V3_IPC_INT;
  114. writenfc(tmp, &host->ip_regs->ipc);
  115. #endif
  116. break;
  117. }
  118. udelay(1);
  119. }
  120. if (max_retries < 0) {
  121. pr_debug("%s(%d): INT not set\n",
  122. __func__, param);
  123. }
  124. }
  125. /*
  126. * This function issues the specified command to the NAND device and
  127. * waits for completion.
  128. */
  129. static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
  130. {
  131. pr_debug("send_cmd(host, 0x%x)\n", cmd);
  132. writenfc(cmd, &host->regs->flash_cmd);
  133. writenfc(NFC_CMD, &host->regs->operation);
  134. /* Wait for operation to complete */
  135. wait_op_done(host, TROP_US_DELAY, cmd);
  136. }
  137. /*
  138. * This function sends an address (or partial address) to the
  139. * NAND device. The address is used to select the source/destination for
  140. * a NAND command.
  141. */
  142. static void send_addr(struct mxc_nand_host *host, uint16_t addr)
  143. {
  144. pr_debug("send_addr(host, 0x%x)\n", addr);
  145. writenfc(addr, &host->regs->flash_addr);
  146. writenfc(NFC_ADDR, &host->regs->operation);
  147. /* Wait for operation to complete */
  148. wait_op_done(host, TROP_US_DELAY, addr);
  149. }
  150. /*
  151. * This function requests the NANDFC to initiate the transfer
  152. * of data currently in the NANDFC RAM buffer to the NAND device.
  153. */
  154. static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
  155. int spare_only)
  156. {
  157. if (spare_only)
  158. pr_debug("send_prog_page (%d)\n", spare_only);
  159. if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
  160. int i;
  161. /*
  162. * The controller copies the 64 bytes of spare data from
  163. * the first 16 bytes of each of the 4 64 byte spare buffers.
  164. * Copy the contiguous data starting in spare_area[0] to
  165. * the four spare area buffers.
  166. */
  167. for (i = 1; i < 4; i++) {
  168. void __iomem *src = &host->regs->spare_area[0][i * 16];
  169. void __iomem *dst = &host->regs->spare_area[i][0];
  170. mxc_nand_memcpy32(dst, src, 16);
  171. }
  172. }
  173. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  174. writenfc(buf_id, &host->regs->buf_addr);
  175. #elif defined(MXC_NFC_V3_2)
  176. uint32_t tmp = readnfc(&host->regs->config1);
  177. tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
  178. tmp |= NFC_V3_CONFIG1_RBA(buf_id);
  179. writenfc(tmp, &host->regs->config1);
  180. #endif
  181. /* Configure spare or page+spare access */
  182. if (!host->pagesize_2k) {
  183. uint32_t config1 = readnfc(&host->regs->config1);
  184. if (spare_only)
  185. config1 |= NFC_CONFIG1_SP_EN;
  186. else
  187. config1 &= ~NFC_CONFIG1_SP_EN;
  188. writenfc(config1, &host->regs->config1);
  189. }
  190. writenfc(NFC_INPUT, &host->regs->operation);
  191. /* Wait for operation to complete */
  192. wait_op_done(host, TROP_US_DELAY, spare_only);
  193. }
  194. /*
  195. * Requests NANDFC to initiate the transfer of data from the
  196. * NAND device into in the NANDFC ram buffer.
  197. */
  198. static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
  199. int spare_only)
  200. {
  201. pr_debug("send_read_page (%d)\n", spare_only);
  202. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  203. writenfc(buf_id, &host->regs->buf_addr);
  204. #elif defined(MXC_NFC_V3_2)
  205. uint32_t tmp = readnfc(&host->regs->config1);
  206. tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
  207. tmp |= NFC_V3_CONFIG1_RBA(buf_id);
  208. writenfc(tmp, &host->regs->config1);
  209. #endif
  210. /* Configure spare or page+spare access */
  211. if (!host->pagesize_2k) {
  212. uint32_t config1 = readnfc(&host->regs->config1);
  213. if (spare_only)
  214. config1 |= NFC_CONFIG1_SP_EN;
  215. else
  216. config1 &= ~NFC_CONFIG1_SP_EN;
  217. writenfc(config1, &host->regs->config1);
  218. }
  219. writenfc(NFC_OUTPUT, &host->regs->operation);
  220. /* Wait for operation to complete */
  221. wait_op_done(host, TROP_US_DELAY, spare_only);
  222. if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
  223. int i;
  224. /*
  225. * The controller copies the 64 bytes of spare data to
  226. * the first 16 bytes of each of the 4 spare buffers.
  227. * Make the data contiguous starting in spare_area[0].
  228. */
  229. for (i = 1; i < 4; i++) {
  230. void __iomem *src = &host->regs->spare_area[i][0];
  231. void __iomem *dst = &host->regs->spare_area[0][i * 16];
  232. mxc_nand_memcpy32(dst, src, 16);
  233. }
  234. }
  235. }
  236. /* Request the NANDFC to perform a read of the NAND device ID. */
  237. static void send_read_id(struct mxc_nand_host *host)
  238. {
  239. uint32_t tmp;
  240. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  241. /* NANDFC buffer 0 is used for device ID output */
  242. writenfc(0x0, &host->regs->buf_addr);
  243. #elif defined(MXC_NFC_V3_2)
  244. tmp = readnfc(&host->regs->config1);
  245. tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
  246. writenfc(tmp, &host->regs->config1);
  247. #endif
  248. /* Read ID into main buffer */
  249. tmp = readnfc(&host->regs->config1);
  250. tmp &= ~NFC_CONFIG1_SP_EN;
  251. writenfc(tmp, &host->regs->config1);
  252. writenfc(NFC_ID, &host->regs->operation);
  253. /* Wait for operation to complete */
  254. wait_op_done(host, TROP_US_DELAY, 0);
  255. }
  256. /*
  257. * This function requests the NANDFC to perform a read of the
  258. * NAND device status and returns the current status.
  259. */
  260. static uint16_t get_dev_status(struct mxc_nand_host *host)
  261. {
  262. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  263. void __iomem *main_buf = host->regs->main_area[1];
  264. uint32_t store;
  265. #endif
  266. uint32_t ret, tmp;
  267. /* Issue status request to NAND device */
  268. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  269. /* store the main area1 first word, later do recovery */
  270. store = readl(main_buf);
  271. /* NANDFC buffer 1 is used for device status */
  272. writenfc(1, &host->regs->buf_addr);
  273. #endif
  274. /* Read status into main buffer */
  275. tmp = readnfc(&host->regs->config1);
  276. tmp &= ~NFC_CONFIG1_SP_EN;
  277. writenfc(tmp, &host->regs->config1);
  278. writenfc(NFC_STATUS, &host->regs->operation);
  279. /* Wait for operation to complete */
  280. wait_op_done(host, TROP_US_DELAY, 0);
  281. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  282. /*
  283. * Status is placed in first word of main buffer
  284. * get status, then recovery area 1 data
  285. */
  286. ret = readw(main_buf);
  287. writel(store, main_buf);
  288. #elif defined(MXC_NFC_V3_2)
  289. ret = readnfc(&host->regs->config1) >> 16;
  290. #endif
  291. return ret;
  292. }
  293. /* This function is used by upper layer to checks if device is ready */
  294. static int mxc_nand_dev_ready(struct mtd_info *mtd)
  295. {
  296. /*
  297. * NFC handles R/B internally. Therefore, this function
  298. * always returns status as ready.
  299. */
  300. return 1;
  301. }
  302. static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
  303. {
  304. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  305. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  306. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  307. uint16_t tmp = readnfc(&host->regs->config1);
  308. if (on)
  309. tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
  310. else
  311. tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
  312. writenfc(tmp, &host->regs->config1);
  313. #elif defined(MXC_NFC_V3_2)
  314. uint32_t tmp = readnfc(&host->ip_regs->config2);
  315. if (on)
  316. tmp |= NFC_V3_CONFIG2_ECC_EN;
  317. else
  318. tmp &= ~NFC_V3_CONFIG2_ECC_EN;
  319. writenfc(tmp, &host->ip_regs->config2);
  320. #endif
  321. }
  322. #ifdef CONFIG_MXC_NAND_HWECC
  323. static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  324. {
  325. /*
  326. * If HW ECC is enabled, we turn it on during init. There is
  327. * no need to enable again here.
  328. */
  329. }
  330. #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  331. static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
  332. struct nand_chip *chip,
  333. int page)
  334. {
  335. struct mxc_nand_host *host = nand_get_controller_data(chip);
  336. uint8_t *buf = chip->oob_poi;
  337. int length = mtd->oobsize;
  338. int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  339. uint8_t *bufpoi = buf;
  340. int i, toread;
  341. pr_debug("%s: Reading OOB area of page %u to oob %p\n",
  342. __func__, page, buf);
  343. chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
  344. for (i = 0; i < chip->ecc.steps; i++) {
  345. toread = min_t(int, length, chip->ecc.prepad);
  346. if (toread) {
  347. chip->read_buf(mtd, bufpoi, toread);
  348. bufpoi += toread;
  349. length -= toread;
  350. }
  351. bufpoi += chip->ecc.bytes;
  352. host->col_addr += chip->ecc.bytes;
  353. length -= chip->ecc.bytes;
  354. toread = min_t(int, length, chip->ecc.postpad);
  355. if (toread) {
  356. chip->read_buf(mtd, bufpoi, toread);
  357. bufpoi += toread;
  358. length -= toread;
  359. }
  360. }
  361. if (length > 0)
  362. chip->read_buf(mtd, bufpoi, length);
  363. _mxc_nand_enable_hwecc(mtd, 0);
  364. chip->cmdfunc(mtd, NAND_CMD_READOOB,
  365. mtd->writesize + chip->ecc.prepad, page);
  366. bufpoi = buf + chip->ecc.prepad;
  367. length = mtd->oobsize - chip->ecc.prepad;
  368. for (i = 0; i < chip->ecc.steps; i++) {
  369. toread = min_t(int, length, chip->ecc.bytes);
  370. chip->read_buf(mtd, bufpoi, toread);
  371. bufpoi += eccpitch;
  372. length -= eccpitch;
  373. host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
  374. }
  375. _mxc_nand_enable_hwecc(mtd, 1);
  376. return 1;
  377. }
  378. static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
  379. struct nand_chip *chip,
  380. uint8_t *buf,
  381. int oob_required,
  382. int page)
  383. {
  384. struct mxc_nand_host *host = nand_get_controller_data(chip);
  385. int eccsize = chip->ecc.size;
  386. int eccbytes = chip->ecc.bytes;
  387. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  388. uint8_t *oob = chip->oob_poi;
  389. int steps, size;
  390. int n;
  391. _mxc_nand_enable_hwecc(mtd, 0);
  392. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  393. for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
  394. host->col_addr = n * eccsize;
  395. chip->read_buf(mtd, buf, eccsize);
  396. buf += eccsize;
  397. host->col_addr = mtd->writesize + n * eccpitch;
  398. if (chip->ecc.prepad) {
  399. chip->read_buf(mtd, oob, chip->ecc.prepad);
  400. oob += chip->ecc.prepad;
  401. }
  402. chip->read_buf(mtd, oob, eccbytes);
  403. oob += eccbytes;
  404. if (chip->ecc.postpad) {
  405. chip->read_buf(mtd, oob, chip->ecc.postpad);
  406. oob += chip->ecc.postpad;
  407. }
  408. }
  409. size = mtd->oobsize - (oob - chip->oob_poi);
  410. if (size)
  411. chip->read_buf(mtd, oob, size);
  412. _mxc_nand_enable_hwecc(mtd, 1);
  413. return 0;
  414. }
  415. static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
  416. struct nand_chip *chip,
  417. uint8_t *buf,
  418. int oob_required,
  419. int page)
  420. {
  421. struct mxc_nand_host *host = nand_get_controller_data(chip);
  422. int n, eccsize = chip->ecc.size;
  423. int eccbytes = chip->ecc.bytes;
  424. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  425. int eccsteps = chip->ecc.steps;
  426. uint8_t *p = buf;
  427. uint8_t *oob = chip->oob_poi;
  428. pr_debug("Reading page %u to buf %p oob %p\n",
  429. page, buf, oob);
  430. /* first read the data area and the available portion of OOB */
  431. for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
  432. int stat;
  433. host->col_addr = n * eccsize;
  434. chip->read_buf(mtd, p, eccsize);
  435. host->col_addr = mtd->writesize + n * eccpitch;
  436. if (chip->ecc.prepad) {
  437. chip->read_buf(mtd, oob, chip->ecc.prepad);
  438. oob += chip->ecc.prepad;
  439. }
  440. stat = chip->ecc.correct(mtd, p, oob, NULL);
  441. if (stat < 0)
  442. mtd->ecc_stats.failed++;
  443. else
  444. mtd->ecc_stats.corrected += stat;
  445. oob += eccbytes;
  446. if (chip->ecc.postpad) {
  447. chip->read_buf(mtd, oob, chip->ecc.postpad);
  448. oob += chip->ecc.postpad;
  449. }
  450. }
  451. /* Calculate remaining oob bytes */
  452. n = mtd->oobsize - (oob - chip->oob_poi);
  453. if (n)
  454. chip->read_buf(mtd, oob, n);
  455. /* Then switch ECC off and read the OOB area to get the ECC code */
  456. _mxc_nand_enable_hwecc(mtd, 0);
  457. chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
  458. eccsteps = chip->ecc.steps;
  459. oob = chip->oob_poi + chip->ecc.prepad;
  460. for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
  461. host->col_addr = mtd->writesize +
  462. n * eccpitch +
  463. chip->ecc.prepad;
  464. chip->read_buf(mtd, oob, eccbytes);
  465. oob += eccbytes + chip->ecc.postpad;
  466. }
  467. _mxc_nand_enable_hwecc(mtd, 1);
  468. return 0;
  469. }
  470. static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
  471. struct nand_chip *chip, int page)
  472. {
  473. struct mxc_nand_host *host = nand_get_controller_data(chip);
  474. int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  475. int length = mtd->oobsize;
  476. int i, len, status, steps = chip->ecc.steps;
  477. const uint8_t *bufpoi = chip->oob_poi;
  478. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  479. for (i = 0; i < steps; i++) {
  480. len = min_t(int, length, eccpitch);
  481. chip->write_buf(mtd, bufpoi, len);
  482. bufpoi += len;
  483. length -= len;
  484. host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
  485. }
  486. if (length > 0)
  487. chip->write_buf(mtd, bufpoi, length);
  488. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  489. status = chip->waitfunc(mtd, chip);
  490. return status & NAND_STATUS_FAIL ? -EIO : 0;
  491. }
  492. static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
  493. struct nand_chip *chip,
  494. const uint8_t *buf,
  495. int oob_required, int page)
  496. {
  497. struct mxc_nand_host *host = nand_get_controller_data(chip);
  498. int eccsize = chip->ecc.size;
  499. int eccbytes = chip->ecc.bytes;
  500. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  501. uint8_t *oob = chip->oob_poi;
  502. int steps, size;
  503. int n;
  504. for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
  505. host->col_addr = n * eccsize;
  506. chip->write_buf(mtd, buf, eccsize);
  507. buf += eccsize;
  508. host->col_addr = mtd->writesize + n * eccpitch;
  509. if (chip->ecc.prepad) {
  510. chip->write_buf(mtd, oob, chip->ecc.prepad);
  511. oob += chip->ecc.prepad;
  512. }
  513. host->col_addr += eccbytes;
  514. oob += eccbytes;
  515. if (chip->ecc.postpad) {
  516. chip->write_buf(mtd, oob, chip->ecc.postpad);
  517. oob += chip->ecc.postpad;
  518. }
  519. }
  520. size = mtd->oobsize - (oob - chip->oob_poi);
  521. if (size)
  522. chip->write_buf(mtd, oob, size);
  523. return 0;
  524. }
  525. static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
  526. struct nand_chip *chip,
  527. const uint8_t *buf,
  528. int oob_required, int page)
  529. {
  530. struct mxc_nand_host *host = nand_get_controller_data(chip);
  531. int i, n, eccsize = chip->ecc.size;
  532. int eccbytes = chip->ecc.bytes;
  533. int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  534. int eccsteps = chip->ecc.steps;
  535. const uint8_t *p = buf;
  536. uint8_t *oob = chip->oob_poi;
  537. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  538. for (i = n = 0;
  539. eccsteps;
  540. n++, eccsteps--, i += eccbytes, p += eccsize) {
  541. host->col_addr = n * eccsize;
  542. chip->write_buf(mtd, p, eccsize);
  543. host->col_addr = mtd->writesize + n * eccpitch;
  544. if (chip->ecc.prepad) {
  545. chip->write_buf(mtd, oob, chip->ecc.prepad);
  546. oob += chip->ecc.prepad;
  547. }
  548. chip->write_buf(mtd, oob, eccbytes);
  549. oob += eccbytes;
  550. if (chip->ecc.postpad) {
  551. chip->write_buf(mtd, oob, chip->ecc.postpad);
  552. oob += chip->ecc.postpad;
  553. }
  554. }
  555. /* Calculate remaining oob bytes */
  556. i = mtd->oobsize - (oob - chip->oob_poi);
  557. if (i)
  558. chip->write_buf(mtd, oob, i);
  559. return 0;
  560. }
  561. static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  562. u_char *read_ecc, u_char *calc_ecc)
  563. {
  564. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  565. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  566. uint32_t ecc_status = readl(&host->regs->ecc_status_result);
  567. int subpages = mtd->writesize / nand_chip->subpagesize;
  568. int pg2blk_shift = nand_chip->phys_erase_shift -
  569. nand_chip->page_shift;
  570. do {
  571. if ((ecc_status & 0xf) > 4) {
  572. static int last_bad = -1;
  573. if (last_bad != host->page_addr >> pg2blk_shift) {
  574. last_bad = host->page_addr >> pg2blk_shift;
  575. printk(KERN_DEBUG
  576. "MXC_NAND: HWECC uncorrectable ECC error"
  577. " in block %u page %u subpage %d\n",
  578. last_bad, host->page_addr,
  579. mtd->writesize / nand_chip->subpagesize
  580. - subpages);
  581. }
  582. return -EBADMSG;
  583. }
  584. ecc_status >>= 4;
  585. subpages--;
  586. } while (subpages > 0);
  587. return 0;
  588. }
  589. #else
  590. #define mxc_nand_read_page_syndrome NULL
  591. #define mxc_nand_read_page_raw_syndrome NULL
  592. #define mxc_nand_read_oob_syndrome NULL
  593. #define mxc_nand_write_page_syndrome NULL
  594. #define mxc_nand_write_page_raw_syndrome NULL
  595. #define mxc_nand_write_oob_syndrome NULL
  596. static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
  597. u_char *read_ecc, u_char *calc_ecc)
  598. {
  599. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  600. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  601. /*
  602. * 1-Bit errors are automatically corrected in HW. No need for
  603. * additional correction. 2-Bit errors cannot be corrected by
  604. * HW ECC, so we need to return failure
  605. */
  606. uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
  607. if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
  608. pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
  609. return -EBADMSG;
  610. }
  611. return 0;
  612. }
  613. #endif
  614. static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  615. u_char *ecc_code)
  616. {
  617. return 0;
  618. }
  619. #endif
  620. static u_char mxc_nand_read_byte(struct mtd_info *mtd)
  621. {
  622. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  623. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  624. uint8_t ret = 0;
  625. uint16_t col;
  626. uint16_t __iomem *main_buf =
  627. (uint16_t __iomem *)host->regs->main_area[0];
  628. uint16_t __iomem *spare_buf =
  629. (uint16_t __iomem *)host->regs->spare_area[0];
  630. union {
  631. uint16_t word;
  632. uint8_t bytes[2];
  633. } nfc_word;
  634. /* Check for status request */
  635. if (host->status_request)
  636. return get_dev_status(host) & 0xFF;
  637. /* Get column for 16-bit access */
  638. col = host->col_addr >> 1;
  639. /* If we are accessing the spare region */
  640. if (host->spare_only)
  641. nfc_word.word = readw(&spare_buf[col]);
  642. else
  643. nfc_word.word = readw(&main_buf[col]);
  644. /* Pick upper/lower byte of word from RAM buffer */
  645. ret = nfc_word.bytes[host->col_addr & 0x1];
  646. /* Update saved column address */
  647. if (nand_chip->options & NAND_BUSWIDTH_16)
  648. host->col_addr += 2;
  649. else
  650. host->col_addr++;
  651. return ret;
  652. }
  653. static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
  654. {
  655. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  656. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  657. uint16_t col, ret;
  658. uint16_t __iomem *p;
  659. pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr);
  660. col = host->col_addr;
  661. /* Adjust saved column address */
  662. if (col < mtd->writesize && host->spare_only)
  663. col += mtd->writesize;
  664. if (col < mtd->writesize) {
  665. p = (uint16_t __iomem *)(host->regs->main_area[0] +
  666. (col >> 1));
  667. } else {
  668. p = (uint16_t __iomem *)(host->regs->spare_area[0] +
  669. ((col - mtd->writesize) >> 1));
  670. }
  671. if (col & 1) {
  672. union {
  673. uint16_t word;
  674. uint8_t bytes[2];
  675. } nfc_word[3];
  676. nfc_word[0].word = readw(p);
  677. nfc_word[1].word = readw(p + 1);
  678. nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
  679. nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
  680. ret = nfc_word[2].word;
  681. } else {
  682. ret = readw(p);
  683. }
  684. /* Update saved column address */
  685. host->col_addr = col + 2;
  686. return ret;
  687. }
  688. /*
  689. * Write data of length len to buffer buf. The data to be
  690. * written on NAND Flash is first copied to RAMbuffer. After the Data Input
  691. * Operation by the NFC, the data is written to NAND Flash
  692. */
  693. static void mxc_nand_write_buf(struct mtd_info *mtd,
  694. const u_char *buf, int len)
  695. {
  696. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  697. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  698. int n, col, i = 0;
  699. pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
  700. len);
  701. col = host->col_addr;
  702. /* Adjust saved column address */
  703. if (col < mtd->writesize && host->spare_only)
  704. col += mtd->writesize;
  705. n = mtd->writesize + mtd->oobsize - col;
  706. n = min(len, n);
  707. pr_debug("%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
  708. while (n > 0) {
  709. void __iomem *p;
  710. if (col < mtd->writesize) {
  711. p = host->regs->main_area[0] + (col & ~3);
  712. } else {
  713. p = host->regs->spare_area[0] -
  714. mtd->writesize + (col & ~3);
  715. }
  716. pr_debug("%s:%d: p = %p\n", __func__,
  717. __LINE__, p);
  718. if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
  719. union {
  720. uint32_t word;
  721. uint8_t bytes[4];
  722. } nfc_word;
  723. nfc_word.word = readl(p);
  724. nfc_word.bytes[col & 3] = buf[i++];
  725. n--;
  726. col++;
  727. writel(nfc_word.word, p);
  728. } else {
  729. int m = mtd->writesize - col;
  730. if (col >= mtd->writesize)
  731. m += mtd->oobsize;
  732. m = min(n, m) & ~3;
  733. pr_debug("%s:%d: n = %d, m = %d, i = %d, col = %d\n",
  734. __func__, __LINE__, n, m, i, col);
  735. mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
  736. col += m;
  737. i += m;
  738. n -= m;
  739. }
  740. }
  741. /* Update saved column address */
  742. host->col_addr = col;
  743. }
  744. /*
  745. * Read the data buffer from the NAND Flash. To read the data from NAND
  746. * Flash first the data output cycle is initiated by the NFC, which copies
  747. * the data to RAMbuffer. This data of length len is then copied to buffer buf.
  748. */
  749. static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  750. {
  751. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  752. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  753. int n, col, i = 0;
  754. pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr,
  755. len);
  756. col = host->col_addr;
  757. /* Adjust saved column address */
  758. if (col < mtd->writesize && host->spare_only)
  759. col += mtd->writesize;
  760. n = mtd->writesize + mtd->oobsize - col;
  761. n = min(len, n);
  762. while (n > 0) {
  763. void __iomem *p;
  764. if (col < mtd->writesize) {
  765. p = host->regs->main_area[0] + (col & ~3);
  766. } else {
  767. p = host->regs->spare_area[0] -
  768. mtd->writesize + (col & ~3);
  769. }
  770. if (((col | (int)&buf[i]) & 3) || n < 4) {
  771. union {
  772. uint32_t word;
  773. uint8_t bytes[4];
  774. } nfc_word;
  775. nfc_word.word = readl(p);
  776. buf[i++] = nfc_word.bytes[col & 3];
  777. n--;
  778. col++;
  779. } else {
  780. int m = mtd->writesize - col;
  781. if (col >= mtd->writesize)
  782. m += mtd->oobsize;
  783. m = min(n, m) & ~3;
  784. mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
  785. col += m;
  786. i += m;
  787. n -= m;
  788. }
  789. }
  790. /* Update saved column address */
  791. host->col_addr = col;
  792. }
  793. /*
  794. * This function is used by upper layer for select and
  795. * deselect of the NAND chip
  796. */
  797. static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
  798. {
  799. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  800. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  801. switch (chip) {
  802. case -1:
  803. /* TODO: Disable the NFC clock */
  804. if (host->clk_act)
  805. host->clk_act = 0;
  806. break;
  807. case 0:
  808. /* TODO: Enable the NFC clock */
  809. if (!host->clk_act)
  810. host->clk_act = 1;
  811. break;
  812. default:
  813. break;
  814. }
  815. }
  816. /*
  817. * Used by the upper layer to write command to NAND Flash for
  818. * different operations to be carried out on NAND Flash
  819. */
  820. void mxc_nand_command(struct mtd_info *mtd, unsigned command,
  821. int column, int page_addr)
  822. {
  823. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  824. struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
  825. pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
  826. command, column, page_addr);
  827. /* Reset command state information */
  828. host->status_request = false;
  829. /* Command pre-processing step */
  830. switch (command) {
  831. case NAND_CMD_STATUS:
  832. host->col_addr = 0;
  833. host->status_request = true;
  834. break;
  835. case NAND_CMD_READ0:
  836. host->page_addr = page_addr;
  837. host->col_addr = column;
  838. host->spare_only = false;
  839. break;
  840. case NAND_CMD_READOOB:
  841. host->col_addr = column;
  842. host->spare_only = true;
  843. if (host->pagesize_2k)
  844. command = NAND_CMD_READ0; /* only READ0 is valid */
  845. break;
  846. case NAND_CMD_SEQIN:
  847. if (column >= mtd->writesize) {
  848. /*
  849. * before sending SEQIN command for partial write,
  850. * we need read one page out. FSL NFC does not support
  851. * partial write. It always sends out 512+ecc+512+ecc
  852. * for large page nand flash. But for small page nand
  853. * flash, it does support SPARE ONLY operation.
  854. */
  855. if (host->pagesize_2k) {
  856. /* call ourself to read a page */
  857. mxc_nand_command(mtd, NAND_CMD_READ0, 0,
  858. page_addr);
  859. }
  860. host->col_addr = column - mtd->writesize;
  861. host->spare_only = true;
  862. /* Set program pointer to spare region */
  863. if (!host->pagesize_2k)
  864. send_cmd(host, NAND_CMD_READOOB);
  865. } else {
  866. host->spare_only = false;
  867. host->col_addr = column;
  868. /* Set program pointer to page start */
  869. if (!host->pagesize_2k)
  870. send_cmd(host, NAND_CMD_READ0);
  871. }
  872. break;
  873. case NAND_CMD_PAGEPROG:
  874. send_prog_page(host, 0, host->spare_only);
  875. if (host->pagesize_2k && is_mxc_nfc_1()) {
  876. /* data in 4 areas */
  877. send_prog_page(host, 1, host->spare_only);
  878. send_prog_page(host, 2, host->spare_only);
  879. send_prog_page(host, 3, host->spare_only);
  880. }
  881. break;
  882. }
  883. /* Write out the command to the device. */
  884. send_cmd(host, command);
  885. /* Write out column address, if necessary */
  886. if (column != -1) {
  887. /*
  888. * MXC NANDFC can only perform full page+spare or
  889. * spare-only read/write. When the upper layers perform
  890. * a read/write buffer operation, we will use the saved
  891. * column address to index into the full page.
  892. */
  893. send_addr(host, 0);
  894. if (host->pagesize_2k)
  895. /* another col addr cycle for 2k page */
  896. send_addr(host, 0);
  897. }
  898. /* Write out page address, if necessary */
  899. if (page_addr != -1) {
  900. u32 page_mask = nand_chip->pagemask;
  901. do {
  902. send_addr(host, page_addr & 0xFF);
  903. page_addr >>= 8;
  904. page_mask >>= 8;
  905. } while (page_mask);
  906. }
  907. /* Command post-processing step */
  908. switch (command) {
  909. case NAND_CMD_RESET:
  910. break;
  911. case NAND_CMD_READOOB:
  912. case NAND_CMD_READ0:
  913. if (host->pagesize_2k) {
  914. /* send read confirm command */
  915. send_cmd(host, NAND_CMD_READSTART);
  916. /* read for each AREA */
  917. send_read_page(host, 0, host->spare_only);
  918. if (is_mxc_nfc_1()) {
  919. send_read_page(host, 1, host->spare_only);
  920. send_read_page(host, 2, host->spare_only);
  921. send_read_page(host, 3, host->spare_only);
  922. }
  923. } else {
  924. send_read_page(host, 0, host->spare_only);
  925. }
  926. break;
  927. case NAND_CMD_READID:
  928. host->col_addr = 0;
  929. send_read_id(host);
  930. break;
  931. case NAND_CMD_PAGEPROG:
  932. break;
  933. case NAND_CMD_STATUS:
  934. break;
  935. case NAND_CMD_ERASE2:
  936. break;
  937. }
  938. }
  939. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  940. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  941. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  942. static struct nand_bbt_descr bbt_main_descr = {
  943. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  944. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  945. .offs = 0,
  946. .len = 4,
  947. .veroffs = 4,
  948. .maxblocks = 4,
  949. .pattern = bbt_pattern,
  950. };
  951. static struct nand_bbt_descr bbt_mirror_descr = {
  952. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  953. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  954. .offs = 0,
  955. .len = 4,
  956. .veroffs = 4,
  957. .maxblocks = 4,
  958. .pattern = mirror_pattern,
  959. };
  960. #endif
  961. int board_nand_init(struct nand_chip *this)
  962. {
  963. struct mtd_info *mtd;
  964. #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  965. uint32_t tmp;
  966. #endif
  967. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  968. this->bbt_options |= NAND_BBT_USE_FLASH;
  969. this->bbt_td = &bbt_main_descr;
  970. this->bbt_md = &bbt_mirror_descr;
  971. #endif
  972. /* structures must be linked */
  973. mtd = &this->mtd;
  974. host->nand = this;
  975. /* 5 us command delay time */
  976. this->chip_delay = 5;
  977. nand_set_controller_data(this, host);
  978. this->dev_ready = mxc_nand_dev_ready;
  979. this->cmdfunc = mxc_nand_command;
  980. this->select_chip = mxc_nand_select_chip;
  981. this->read_byte = mxc_nand_read_byte;
  982. this->read_word = mxc_nand_read_word;
  983. this->write_buf = mxc_nand_write_buf;
  984. this->read_buf = mxc_nand_read_buf;
  985. host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
  986. #ifdef MXC_NFC_V3_2
  987. host->ip_regs =
  988. (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
  989. #endif
  990. host->clk_act = 1;
  991. #ifdef CONFIG_MXC_NAND_HWECC
  992. this->ecc.calculate = mxc_nand_calculate_ecc;
  993. this->ecc.hwctl = mxc_nand_enable_hwecc;
  994. this->ecc.correct = mxc_nand_correct_data;
  995. if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
  996. this->ecc.mode = NAND_ECC_HW_SYNDROME;
  997. this->ecc.read_page = mxc_nand_read_page_syndrome;
  998. this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
  999. this->ecc.read_oob = mxc_nand_read_oob_syndrome;
  1000. this->ecc.write_page = mxc_nand_write_page_syndrome;
  1001. this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
  1002. this->ecc.write_oob = mxc_nand_write_oob_syndrome;
  1003. this->ecc.bytes = 9;
  1004. this->ecc.prepad = 7;
  1005. } else {
  1006. this->ecc.mode = NAND_ECC_HW;
  1007. }
  1008. if (is_mxc_nfc_1())
  1009. this->ecc.strength = 1;
  1010. else
  1011. this->ecc.strength = 4;
  1012. host->pagesize_2k = 0;
  1013. this->ecc.size = 512;
  1014. _mxc_nand_enable_hwecc(mtd, 1);
  1015. #else
  1016. this->ecc.layout = &nand_soft_eccoob;
  1017. this->ecc.mode = NAND_ECC_SOFT;
  1018. _mxc_nand_enable_hwecc(mtd, 0);
  1019. #endif
  1020. /* Reset NAND */
  1021. this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1022. /* NAND bus width determines access functions used by upper layer */
  1023. if (is_16bit_nand())
  1024. this->options |= NAND_BUSWIDTH_16;
  1025. #ifdef CONFIG_SYS_NAND_LARGEPAGE
  1026. host->pagesize_2k = 1;
  1027. this->ecc.layout = &nand_hw_eccoob2k;
  1028. #else
  1029. host->pagesize_2k = 0;
  1030. this->ecc.layout = &nand_hw_eccoob;
  1031. #endif
  1032. #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
  1033. #ifdef MXC_NFC_V2_1
  1034. tmp = readnfc(&host->regs->config1);
  1035. tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
  1036. tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
  1037. writenfc(tmp, &host->regs->config1);
  1038. if (host->pagesize_2k)
  1039. writenfc(64/2, &host->regs->spare_area_size);
  1040. else
  1041. writenfc(16/2, &host->regs->spare_area_size);
  1042. #endif
  1043. /*
  1044. * preset operation
  1045. * Unlock the internal RAM Buffer
  1046. */
  1047. writenfc(0x2, &host->regs->config);
  1048. /* Blocks to be unlocked */
  1049. writenfc(0x0, &host->regs->unlockstart_blkaddr);
  1050. /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
  1051. * unlockend_blkaddr, but the magic 0x4000 does not always work
  1052. * when writing more than some 32 megabytes (on 2k page nands)
  1053. * However 0xFFFF doesn't seem to have this kind
  1054. * of limitation (tried it back and forth several times).
  1055. * The linux kernel driver sets this to 0xFFFF for the v2 controller
  1056. * only, but probably this was not tested there for v1.
  1057. * The very same limitation seems to apply to this kernel driver.
  1058. * This might be NAND chip specific and the i.MX31 datasheet is
  1059. * extremely vague about the semantics of this register.
  1060. */
  1061. writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
  1062. /* Unlock Block Command for given address range */
  1063. writenfc(0x4, &host->regs->wrprot);
  1064. #elif defined(MXC_NFC_V3_2)
  1065. writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
  1066. writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
  1067. /* Unlock the internal RAM Buffer */
  1068. writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
  1069. &host->ip_regs->wrprot);
  1070. /* Blocks to be unlocked */
  1071. for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
  1072. writenfc(0x0 | 0xFFFF << 16,
  1073. &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
  1074. writenfc(0, &host->ip_regs->ipc);
  1075. tmp = readnfc(&host->ip_regs->config2);
  1076. tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
  1077. NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
  1078. tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
  1079. if (host->pagesize_2k) {
  1080. tmp |= NFC_V3_CONFIG2_SPAS(64/2);
  1081. tmp |= NFC_V3_CONFIG2_PS_2048;
  1082. } else {
  1083. tmp |= NFC_V3_CONFIG2_SPAS(16/2);
  1084. tmp |= NFC_V3_CONFIG2_PS_512;
  1085. }
  1086. writenfc(tmp, &host->ip_regs->config2);
  1087. tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
  1088. NFC_V3_CONFIG3_NO_SDMA |
  1089. NFC_V3_CONFIG3_RBB_MODE |
  1090. NFC_V3_CONFIG3_SBB(6) | /* Reset default */
  1091. NFC_V3_CONFIG3_ADD_OP(0);
  1092. if (!(this->options & NAND_BUSWIDTH_16))
  1093. tmp |= NFC_V3_CONFIG3_FW8;
  1094. writenfc(tmp, &host->ip_regs->config3);
  1095. writenfc(0, &host->ip_regs->delay_line);
  1096. #endif
  1097. return 0;
  1098. }