kmeter1_nand.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de
  5. */
  6. #include <common.h>
  7. #include <nand.h>
  8. #include <asm/io.h>
  9. #define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
  10. #define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
  11. #define read_mode() in_8(CONFIG_NAND_MODE_REG)
  12. #define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
  13. #define read_data() in_8(CONFIG_NAND_DATA_REG)
  14. #define write_data(val) out_8(CONFIG_NAND_DATA_REG, val)
  15. #define KPN_RDY2 (1 << 7)
  16. #define KPN_RDY1 (1 << 6)
  17. #define KPN_WPN (1 << 4)
  18. #define KPN_CE2N (1 << 3)
  19. #define KPN_CE1N (1 << 2)
  20. #define KPN_ALE (1 << 1)
  21. #define KPN_CLE (1 << 0)
  22. #define KPN_DEFAULT_CHIP_DELAY 50
  23. static int kpn_chip_ready(void)
  24. {
  25. if (read_mode() & KPN_RDY1)
  26. return 1;
  27. return 0;
  28. }
  29. static void kpn_wait_rdy(void)
  30. {
  31. int cnt = 1000000;
  32. while (--cnt && !kpn_chip_ready())
  33. udelay(1);
  34. if (!cnt)
  35. printf ("timeout while waiting for RDY\n");
  36. }
  37. static void kpn_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  38. {
  39. u8 reg_val = read_mode();
  40. if (ctrl & NAND_CTRL_CHANGE) {
  41. reg_val = reg_val & ~(KPN_ALE + KPN_CLE);
  42. if (ctrl & NAND_CLE)
  43. reg_val = reg_val | KPN_CLE;
  44. if (ctrl & NAND_ALE)
  45. reg_val = reg_val | KPN_ALE;
  46. if (ctrl & NAND_NCE)
  47. reg_val = reg_val & ~KPN_CE1N;
  48. else
  49. reg_val = reg_val | KPN_CE1N;
  50. write_mode(reg_val);
  51. }
  52. if (cmd != NAND_CMD_NONE)
  53. write_data(cmd);
  54. /* wait until flash is ready */
  55. kpn_wait_rdy();
  56. }
  57. static u_char kpn_nand_read_byte(struct mtd_info *mtd)
  58. {
  59. return read_data();
  60. }
  61. static void kpn_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  62. {
  63. int i;
  64. for (i = 0; i < len; i++) {
  65. write_data(buf[i]);
  66. kpn_wait_rdy();
  67. }
  68. }
  69. static void kpn_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  70. {
  71. int i;
  72. for (i = 0; i < len; i++)
  73. buf[i] = read_data();
  74. }
  75. static int kpn_nand_dev_ready(struct mtd_info *mtd)
  76. {
  77. kpn_wait_rdy();
  78. return 1;
  79. }
  80. int board_nand_init(struct nand_chip *nand)
  81. {
  82. #if defined(CONFIG_NAND_ECC_BCH)
  83. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  84. #else
  85. nand->ecc.mode = NAND_ECC_SOFT;
  86. #endif
  87. /* Reference hardware control function */
  88. nand->cmd_ctrl = kpn_nand_hwcontrol;
  89. nand->read_byte = kpn_nand_read_byte;
  90. nand->write_buf = kpn_nand_write_buf;
  91. nand->read_buf = kpn_nand_read_buf;
  92. nand->dev_ready = kpn_nand_dev_ready;
  93. nand->chip_delay = KPN_DEFAULT_CHIP_DELAY;
  94. /* reset mode register */
  95. write_mode(KPN_CE1N + KPN_CE2N + KPN_WPN);
  96. return 0;
  97. }