kb9202_nand.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006
  4. * KwikByte <kb9200_dev@kwikbyte.com>
  5. *
  6. * (C) Copyright 2009
  7. * Matthias Kaehlcke <matthias@kaehlcke.net>
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/AT91RM9200.h>
  12. #include <asm/arch/hardware.h>
  13. #include <nand.h>
  14. /*
  15. * hardware specific access to control-lines
  16. */
  17. #define MASK_ALE (1 << 22) /* our ALE is A22 */
  18. #define MASK_CLE (1 << 21) /* our CLE is A21 */
  19. #define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
  20. #define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
  21. #define KB9202_SMC2_NWS (1 << 2)
  22. #define KB9202_SMC2_TDF (1 << 8)
  23. #define KB9202_SMC2_RWSETUP (1 << 24)
  24. #define KB9202_SMC2_RWHOLD (1 << 29)
  25. /*
  26. * Board-specific function to access device control signals
  27. */
  28. static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  29. {
  30. struct nand_chip *this = mtd_to_nand(mtd);
  31. if (ctrl & NAND_CTRL_CHANGE) {
  32. ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  33. /* clear ALE and CLE bits */
  34. IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
  35. if (ctrl & NAND_CLE)
  36. IO_ADDR_W |= MASK_CLE;
  37. if (ctrl & NAND_ALE)
  38. IO_ADDR_W |= MASK_ALE;
  39. this->IO_ADDR_W = (void *) IO_ADDR_W;
  40. if (ctrl & NAND_NCE)
  41. writel(KB9202_NAND_NCE, AT91C_PIOC_CODR);
  42. else
  43. writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
  44. }
  45. if (cmd != NAND_CMD_NONE)
  46. writeb(cmd, this->IO_ADDR_W);
  47. }
  48. /*
  49. * Board-specific function to access the device ready signal.
  50. */
  51. static int kb9202_nand_ready(struct mtd_info *mtd)
  52. {
  53. return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY;
  54. }
  55. /*
  56. * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference.
  57. *
  58. * struct nand_chip - NAND Private Flash Chip Data
  59. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
  60. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
  61. * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
  62. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
  63. * If set to NULL no access to ready/busy is available and the ready/busy information
  64. * is read from the chip status register
  65. * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
  66. * be provided if a hardware ECC is available
  67. * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
  68. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
  69. * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
  70. * special functionality. See the defines for further explanation
  71. */
  72. /*
  73. * This routine initializes controller and GPIOs.
  74. */
  75. int board_nand_init(struct nand_chip *nand)
  76. {
  77. unsigned int value;
  78. nand->ecc.mode = NAND_ECC_SOFT;
  79. nand->cmd_ctrl = kb9202_nand_hwcontrol;
  80. nand->dev_ready = kb9202_nand_ready;
  81. /* in case running outside of bootloader */
  82. writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
  83. /* setup nand flash access (allow ample margin) */
  84. /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
  85. writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
  86. AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,
  87. AT91C_SMC_CSR3);
  88. /* enable internal NAND controller */
  89. value = readl(AT91C_EBI_CSA);
  90. value |= AT91C_EBI_CS3A_SMC_SmartMedia;
  91. writel(value, AT91C_EBI_CSA);
  92. /* enable SMOE/SMWE */
  93. writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR);
  94. writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR);
  95. writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER);
  96. /* set NCE to high */
  97. writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
  98. /* disable output on pin connected to the busy line of the NAND */
  99. writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR);
  100. /* enable the PIO to control NCE and BUSY */
  101. writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER);
  102. /* enable output for NCE */
  103. writel(KB9202_NAND_NCE, AT91C_PIOC_OER);
  104. return (0);
  105. }