fsl_upm.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * FSL UPM NAND driver
  4. *
  5. * Copyright (C) 2007 MontaVista Software, Inc.
  6. * Anton Vorontsov <avorontsov@ru.mvista.com>
  7. */
  8. #include <config.h>
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/fsl_upm.h>
  14. #include <nand.h>
  15. static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
  16. {
  17. clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
  18. (void)in_be32(upm->mxmr);
  19. }
  20. static void fsl_upm_end_pattern(struct fsl_upm *upm)
  21. {
  22. clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
  23. while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
  24. eieio();
  25. }
  26. static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
  27. void __iomem *io_addr, u32 mar)
  28. {
  29. out_be32(upm->mar, mar);
  30. (void)in_be32(upm->mar);
  31. switch (width) {
  32. case 8:
  33. out_8(io_addr, 0x0);
  34. break;
  35. case 16:
  36. out_be16(io_addr, 0x0);
  37. break;
  38. case 32:
  39. out_be32(io_addr, 0x0);
  40. break;
  41. }
  42. }
  43. static void fun_wait(struct fsl_upm_nand *fun)
  44. {
  45. if (fun->dev_ready) {
  46. while (!fun->dev_ready(fun->chip_nr))
  47. debug("unexpected busy state\n");
  48. } else {
  49. /*
  50. * If the R/B pin is not connected,
  51. * a short delay is necessary.
  52. */
  53. udelay(1);
  54. }
  55. }
  56. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  57. static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
  58. {
  59. struct nand_chip *chip = mtd_to_nand(mtd);
  60. struct fsl_upm_nand *fun = nand_get_controller_data(chip);
  61. if (chip_nr >= 0) {
  62. fun->chip_nr = chip_nr;
  63. chip->IO_ADDR_R = chip->IO_ADDR_W =
  64. fun->upm.io_addr + fun->chip_offset * chip_nr;
  65. } else if (chip_nr == -1) {
  66. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  67. }
  68. }
  69. #endif
  70. static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  71. {
  72. struct nand_chip *chip = mtd_to_nand(mtd);
  73. struct fsl_upm_nand *fun = nand_get_controller_data(chip);
  74. void __iomem *io_addr;
  75. u32 mar;
  76. if (!(ctrl & fun->last_ctrl)) {
  77. fsl_upm_end_pattern(&fun->upm);
  78. if (cmd == NAND_CMD_NONE)
  79. return;
  80. fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  81. }
  82. if (ctrl & NAND_CTRL_CHANGE) {
  83. if (ctrl & NAND_ALE)
  84. fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
  85. else if (ctrl & NAND_CLE)
  86. fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
  87. }
  88. mar = cmd << (32 - fun->width);
  89. io_addr = fun->upm.io_addr;
  90. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  91. if (fun->chip_nr > 0) {
  92. io_addr += fun->chip_offset * fun->chip_nr;
  93. if (fun->upm_mar_chip_offset)
  94. mar |= fun->upm_mar_chip_offset * fun->chip_nr;
  95. }
  96. #endif
  97. fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
  98. /*
  99. * Some boards/chips needs this. At least the MPC8360E-RDK
  100. * needs it. Probably weird chip, because I don't see any
  101. * need for this on MPC8555E + Samsung K9F1G08U0A. Usually
  102. * here are 0-2 unexpected busy states per block read.
  103. */
  104. if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
  105. fun_wait(fun);
  106. }
  107. static u8 upm_nand_read_byte(struct mtd_info *mtd)
  108. {
  109. struct nand_chip *chip = mtd_to_nand(mtd);
  110. return in_8(chip->IO_ADDR_R);
  111. }
  112. static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  113. {
  114. int i;
  115. struct nand_chip *chip = mtd_to_nand(mtd);
  116. struct fsl_upm_nand *fun = nand_get_controller_data(chip);
  117. for (i = 0; i < len; i++) {
  118. out_8(chip->IO_ADDR_W, buf[i]);
  119. if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
  120. fun_wait(fun);
  121. }
  122. if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
  123. fun_wait(fun);
  124. }
  125. static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  126. {
  127. int i;
  128. struct nand_chip *chip = mtd_to_nand(mtd);
  129. for (i = 0; i < len; i++)
  130. buf[i] = in_8(chip->IO_ADDR_R);
  131. }
  132. static int nand_dev_ready(struct mtd_info *mtd)
  133. {
  134. struct nand_chip *chip = mtd_to_nand(mtd);
  135. struct fsl_upm_nand *fun = nand_get_controller_data(chip);
  136. return fun->dev_ready(fun->chip_nr);
  137. }
  138. int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
  139. {
  140. if (fun->width != 8 && fun->width != 16 && fun->width != 32)
  141. return -ENOSYS;
  142. fun->last_ctrl = NAND_CLE;
  143. nand_set_controller_data(chip, fun);
  144. chip->chip_delay = fun->chip_delay;
  145. chip->ecc.mode = NAND_ECC_SOFT;
  146. chip->cmd_ctrl = fun_cmd_ctrl;
  147. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  148. chip->select_chip = fun_select_chip;
  149. #endif
  150. chip->read_byte = upm_nand_read_byte;
  151. chip->read_buf = upm_nand_read_buf;
  152. chip->write_buf = upm_nand_write_buf;
  153. if (fun->dev_ready)
  154. chip->dev_ready = nand_dev_ready;
  155. return 0;
  156. }