fsl_elbc_spl.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
  4. *
  5. * (C) Copyright 2006-2008
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * Copyright (c) 2008 Freescale Semiconductor, Inc.
  9. * Author: Scott Wood <scottwood@freescale.com>
  10. */
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <asm/fsl_lbc.h>
  14. #include <nand.h>
  15. #define WINDOW_SIZE 8192
  16. static void nand_wait(void)
  17. {
  18. fsl_lbc_t *regs = LBC_BASE_ADDR;
  19. for (;;) {
  20. uint32_t status = in_be32(&regs->ltesr);
  21. if (status == 1)
  22. return;
  23. if (status & 1) {
  24. puts("read failed (ltesr)\n");
  25. for (;;);
  26. }
  27. }
  28. }
  29. #ifdef CONFIG_TPL_BUILD
  30. int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  31. #else
  32. static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  33. #endif
  34. {
  35. fsl_lbc_t *regs = LBC_BASE_ADDR;
  36. uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  37. const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
  38. const int block_shift = large ? 17 : 14;
  39. const int block_size = 1 << block_shift;
  40. const int page_size = large ? 2048 : 512;
  41. const int bad_marker = large ? page_size + 0 : page_size + 5;
  42. int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
  43. int pos = 0;
  44. char *dst = vdst;
  45. if (offs & (block_size - 1)) {
  46. puts("bad offset\n");
  47. for (;;);
  48. }
  49. if (large) {
  50. fmr |= FMR_ECCM;
  51. out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
  52. (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
  53. out_be32(&regs->fir,
  54. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  55. (FIR_OP_CA << FIR_OP1_SHIFT) |
  56. (FIR_OP_PA << FIR_OP2_SHIFT) |
  57. (FIR_OP_CW1 << FIR_OP3_SHIFT) |
  58. (FIR_OP_RBW << FIR_OP4_SHIFT));
  59. } else {
  60. out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
  61. out_be32(&regs->fir,
  62. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  63. (FIR_OP_CA << FIR_OP1_SHIFT) |
  64. (FIR_OP_PA << FIR_OP2_SHIFT) |
  65. (FIR_OP_RBW << FIR_OP3_SHIFT));
  66. }
  67. out_be32(&regs->fbcr, 0);
  68. clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
  69. while (pos < uboot_size) {
  70. int i = 0;
  71. out_be32(&regs->fbar, offs >> block_shift);
  72. do {
  73. int j;
  74. unsigned int page_offs = (offs & (block_size - 1)) << 1;
  75. out_be32(&regs->ltesr, ~0);
  76. out_be32(&regs->lteatr, 0);
  77. out_be32(&regs->fpar, page_offs);
  78. out_be32(&regs->fmr, fmr);
  79. out_be32(&regs->lsor, 0);
  80. nand_wait();
  81. page_offs %= WINDOW_SIZE;
  82. /*
  83. * If either of the first two pages are marked bad,
  84. * continue to the next block.
  85. */
  86. if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
  87. puts("skipping\n");
  88. offs = (offs + block_size) & ~(block_size - 1);
  89. pos &= ~(block_size - 1);
  90. break;
  91. }
  92. for (j = 0; j < page_size; j++)
  93. dst[pos + j] = buf[page_offs + j];
  94. pos += page_size;
  95. offs += page_size;
  96. } while ((offs & (block_size - 1)) && (pos < uboot_size));
  97. }
  98. return 0;
  99. }
  100. /*
  101. * Defines a static function nand_load_image() here, because non-static makes
  102. * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
  103. */
  104. #ifndef CONFIG_TPL_BUILD
  105. #define nand_spl_load_image(offs, uboot_size, vdst) \
  106. nand_load_image(offs, uboot_size, vdst)
  107. #endif
  108. /*
  109. * The main entry for NAND booting. It's necessary that SDRAM is already
  110. * configured and available since this code loads the main U-Boot image
  111. * from NAND into SDRAM and starts it from there.
  112. */
  113. void nand_boot(void)
  114. {
  115. __attribute__((noreturn)) void (*uboot)(void);
  116. /*
  117. * Load U-Boot image from NAND into RAM
  118. */
  119. nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
  120. CONFIG_SYS_NAND_U_BOOT_SIZE,
  121. (void *)CONFIG_SYS_NAND_U_BOOT_DST);
  122. #ifdef CONFIG_NAND_ENV_DST
  123. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  124. (void *)CONFIG_NAND_ENV_DST);
  125. #ifdef CONFIG_ENV_OFFSET_REDUND
  126. nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
  127. (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
  128. #endif
  129. #endif
  130. #ifdef CONFIG_SPL_FLUSH_IMAGE
  131. /*
  132. * Clean d-cache and invalidate i-cache, to
  133. * make sure that no stale data is executed.
  134. */
  135. flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
  136. #endif
  137. puts("transfering control\n");
  138. /*
  139. * Jump to U-Boot image
  140. */
  141. uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
  142. (*uboot)();
  143. }