fsl_elbc_nand.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Freescale Enhanced Local Bus Controller FCM NAND driver
  3. *
  4. * Copyright (c) 2006-2008 Freescale Semiconductor
  5. *
  6. * Authors: Nick Spence <nick.spence@freescale.com>,
  7. * Scott Wood <scottwood@freescale.com>
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <nand.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/rawnand.h>
  14. #include <linux/mtd/nand_ecc.h>
  15. #include <asm/io.h>
  16. #include <linux/errno.h>
  17. #ifdef VERBOSE_DEBUG
  18. #define DEBUG_ELBC
  19. #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  20. #else
  21. #define vdbg(format, arg...) do {} while (0)
  22. #endif
  23. /* Can't use plain old DEBUG because the linux mtd
  24. * headers define it as a macro.
  25. */
  26. #ifdef DEBUG_ELBC
  27. #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  28. #else
  29. #define dbg(format, arg...) do {} while (0)
  30. #endif
  31. #define MAX_BANKS 8
  32. #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  33. #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  34. struct fsl_elbc_ctrl;
  35. /* mtd information per set */
  36. struct fsl_elbc_mtd {
  37. struct nand_chip chip;
  38. struct fsl_elbc_ctrl *ctrl;
  39. struct device *dev;
  40. int bank; /* Chip select bank number */
  41. u8 __iomem *vbase; /* Chip select base virtual address */
  42. int page_size; /* NAND page size (0=512, 1=2048) */
  43. unsigned int fmr; /* FCM Flash Mode Register value */
  44. };
  45. /* overview of the fsl elbc controller */
  46. struct fsl_elbc_ctrl {
  47. struct nand_hw_control controller;
  48. struct fsl_elbc_mtd *chips[MAX_BANKS];
  49. /* device info */
  50. fsl_lbc_t *regs;
  51. u8 __iomem *addr; /* Address of assigned FCM buffer */
  52. unsigned int page; /* Last page written to / read from */
  53. unsigned int read_bytes; /* Number of bytes read during command */
  54. unsigned int column; /* Saved column from SEQIN */
  55. unsigned int index; /* Pointer to next byte to 'read' */
  56. unsigned int status; /* status read from LTESR after last op */
  57. unsigned int mdr; /* UPM/FCM Data Register value */
  58. unsigned int use_mdr; /* Non zero if the MDR is to be set */
  59. unsigned int oob; /* Non zero if operating on OOB data */
  60. };
  61. /* These map to the positions used by the FCM hardware ECC generator */
  62. /* Small Page FLASH with FMR[ECCM] = 0 */
  63. static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  64. .eccbytes = 3,
  65. .eccpos = {6, 7, 8},
  66. .oobfree = { {0, 5}, {9, 7} },
  67. };
  68. /* Small Page FLASH with FMR[ECCM] = 1 */
  69. static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  70. .eccbytes = 3,
  71. .eccpos = {8, 9, 10},
  72. .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  73. };
  74. /* Large Page FLASH with FMR[ECCM] = 0 */
  75. static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  76. .eccbytes = 12,
  77. .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
  78. .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
  79. };
  80. /* Large Page FLASH with FMR[ECCM] = 1 */
  81. static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
  82. .eccbytes = 12,
  83. .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
  84. .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
  85. };
  86. /*
  87. * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
  88. * 1, so we have to adjust bad block pattern. This pattern should be used for
  89. * x8 chips only. So far hardware does not support x16 chips anyway.
  90. */
  91. static u8 scan_ff_pattern[] = { 0xff, };
  92. static struct nand_bbt_descr largepage_memorybased = {
  93. .options = 0,
  94. .offs = 0,
  95. .len = 1,
  96. .pattern = scan_ff_pattern,
  97. };
  98. /*
  99. * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
  100. * interfere with ECC positions, that's why we implement our own descriptors.
  101. * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
  102. */
  103. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  104. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  105. static struct nand_bbt_descr bbt_main_descr = {
  106. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  107. NAND_BBT_2BIT | NAND_BBT_VERSION,
  108. .offs = 11,
  109. .len = 4,
  110. .veroffs = 15,
  111. .maxblocks = 4,
  112. .pattern = bbt_pattern,
  113. };
  114. static struct nand_bbt_descr bbt_mirror_descr = {
  115. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  116. NAND_BBT_2BIT | NAND_BBT_VERSION,
  117. .offs = 11,
  118. .len = 4,
  119. .veroffs = 15,
  120. .maxblocks = 4,
  121. .pattern = mirror_pattern,
  122. };
  123. /*=================================*/
  124. /*
  125. * Set up the FCM hardware block and page address fields, and the fcm
  126. * structure addr field to point to the correct FCM buffer in memory
  127. */
  128. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  129. {
  130. struct nand_chip *chip = mtd_to_nand(mtd);
  131. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  132. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  133. fsl_lbc_t *lbc = ctrl->regs;
  134. int buf_num;
  135. ctrl->page = page_addr;
  136. if (priv->page_size) {
  137. out_be32(&lbc->fbar, page_addr >> 6);
  138. out_be32(&lbc->fpar,
  139. ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
  140. (oob ? FPAR_LP_MS : 0) | column);
  141. buf_num = (page_addr & 1) << 2;
  142. } else {
  143. out_be32(&lbc->fbar, page_addr >> 5);
  144. out_be32(&lbc->fpar,
  145. ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
  146. (oob ? FPAR_SP_MS : 0) | column);
  147. buf_num = page_addr & 7;
  148. }
  149. ctrl->addr = priv->vbase + buf_num * 1024;
  150. ctrl->index = column;
  151. /* for OOB data point to the second half of the buffer */
  152. if (oob)
  153. ctrl->index += priv->page_size ? 2048 : 512;
  154. vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
  155. "index %x, pes %d ps %d\n",
  156. buf_num, ctrl->addr, priv->vbase, ctrl->index,
  157. chip->phys_erase_shift, chip->page_shift);
  158. }
  159. /*
  160. * execute FCM command and wait for it to complete
  161. */
  162. static int fsl_elbc_run_command(struct mtd_info *mtd)
  163. {
  164. struct nand_chip *chip = mtd_to_nand(mtd);
  165. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  166. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  167. fsl_lbc_t *lbc = ctrl->regs;
  168. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  169. u32 time_start;
  170. u32 ltesr;
  171. /* Setup the FMR[OP] to execute without write protection */
  172. out_be32(&lbc->fmr, priv->fmr | 3);
  173. if (ctrl->use_mdr)
  174. out_be32(&lbc->mdr, ctrl->mdr);
  175. vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
  176. in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
  177. vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
  178. "fbcr=%08x bank=%d\n",
  179. in_be32(&lbc->fbar), in_be32(&lbc->fpar),
  180. in_be32(&lbc->fbcr), priv->bank);
  181. /* execute special operation */
  182. out_be32(&lbc->lsor, priv->bank);
  183. /* wait for FCM complete flag or timeout */
  184. time_start = get_timer(0);
  185. ltesr = 0;
  186. while (get_timer(time_start) < timeo) {
  187. ltesr = in_be32(&lbc->ltesr);
  188. if (ltesr & LTESR_CC)
  189. break;
  190. }
  191. ctrl->status = ltesr & LTESR_NAND_MASK;
  192. out_be32(&lbc->ltesr, ctrl->status);
  193. out_be32(&lbc->lteatr, 0);
  194. /* store mdr value in case it was needed */
  195. if (ctrl->use_mdr)
  196. ctrl->mdr = in_be32(&lbc->mdr);
  197. ctrl->use_mdr = 0;
  198. vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
  199. ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
  200. /* returns 0 on success otherwise non-zero) */
  201. return ctrl->status == LTESR_CC ? 0 : -EIO;
  202. }
  203. static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
  204. {
  205. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  206. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  207. fsl_lbc_t *lbc = ctrl->regs;
  208. if (priv->page_size) {
  209. out_be32(&lbc->fir,
  210. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  211. (FIR_OP_CA << FIR_OP1_SHIFT) |
  212. (FIR_OP_PA << FIR_OP2_SHIFT) |
  213. (FIR_OP_CW1 << FIR_OP3_SHIFT) |
  214. (FIR_OP_RBW << FIR_OP4_SHIFT));
  215. out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
  216. (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
  217. } else {
  218. out_be32(&lbc->fir,
  219. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  220. (FIR_OP_CA << FIR_OP1_SHIFT) |
  221. (FIR_OP_PA << FIR_OP2_SHIFT) |
  222. (FIR_OP_RBW << FIR_OP3_SHIFT));
  223. if (oob)
  224. out_be32(&lbc->fcr,
  225. NAND_CMD_READOOB << FCR_CMD0_SHIFT);
  226. else
  227. out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
  228. }
  229. }
  230. /* cmdfunc send commands to the FCM */
  231. static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  232. int column, int page_addr)
  233. {
  234. struct nand_chip *chip = mtd_to_nand(mtd);
  235. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  236. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  237. fsl_lbc_t *lbc = ctrl->regs;
  238. ctrl->use_mdr = 0;
  239. /* clear the read buffer */
  240. ctrl->read_bytes = 0;
  241. if (command != NAND_CMD_PAGEPROG)
  242. ctrl->index = 0;
  243. switch (command) {
  244. /* READ0 and READ1 read the entire buffer to use hardware ECC. */
  245. case NAND_CMD_READ1:
  246. column += 256;
  247. /* fall-through */
  248. case NAND_CMD_READ0:
  249. vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
  250. " 0x%x, column: 0x%x.\n", page_addr, column);
  251. out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
  252. set_addr(mtd, 0, page_addr, 0);
  253. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  254. ctrl->index += column;
  255. fsl_elbc_do_read(chip, 0);
  256. fsl_elbc_run_command(mtd);
  257. return;
  258. /* READOOB reads only the OOB because no ECC is performed. */
  259. case NAND_CMD_READOOB:
  260. vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
  261. " 0x%x, column: 0x%x.\n", page_addr, column);
  262. out_be32(&lbc->fbcr, mtd->oobsize - column);
  263. set_addr(mtd, column, page_addr, 1);
  264. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  265. fsl_elbc_do_read(chip, 1);
  266. fsl_elbc_run_command(mtd);
  267. return;
  268. /* READID must read all 5 possible bytes while CEB is active */
  269. case NAND_CMD_READID:
  270. case NAND_CMD_PARAM:
  271. vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
  272. out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  273. (FIR_OP_UA << FIR_OP1_SHIFT) |
  274. (FIR_OP_RBW << FIR_OP2_SHIFT));
  275. out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
  276. /*
  277. * although currently it's 8 bytes for READID, we always read
  278. * the maximum 256 bytes(for PARAM)
  279. */
  280. out_be32(&lbc->fbcr, 256);
  281. ctrl->read_bytes = 256;
  282. ctrl->use_mdr = 1;
  283. ctrl->mdr = column;
  284. set_addr(mtd, 0, 0, 0);
  285. fsl_elbc_run_command(mtd);
  286. return;
  287. /* ERASE1 stores the block and page address */
  288. case NAND_CMD_ERASE1:
  289. vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
  290. "page_addr: 0x%x.\n", page_addr);
  291. set_addr(mtd, 0, page_addr, 0);
  292. return;
  293. /* ERASE2 uses the block and page address from ERASE1 */
  294. case NAND_CMD_ERASE2:
  295. vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
  296. out_be32(&lbc->fir,
  297. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  298. (FIR_OP_PA << FIR_OP1_SHIFT) |
  299. (FIR_OP_CM1 << FIR_OP2_SHIFT));
  300. out_be32(&lbc->fcr,
  301. (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
  302. (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
  303. out_be32(&lbc->fbcr, 0);
  304. ctrl->read_bytes = 0;
  305. fsl_elbc_run_command(mtd);
  306. return;
  307. /* SEQIN sets up the addr buffer and all registers except the length */
  308. case NAND_CMD_SEQIN: {
  309. u32 fcr;
  310. vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
  311. "page_addr: 0x%x, column: 0x%x.\n",
  312. page_addr, column);
  313. ctrl->column = column;
  314. ctrl->oob = 0;
  315. if (priv->page_size) {
  316. fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
  317. (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
  318. out_be32(&lbc->fir,
  319. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  320. (FIR_OP_CA << FIR_OP1_SHIFT) |
  321. (FIR_OP_PA << FIR_OP2_SHIFT) |
  322. (FIR_OP_WB << FIR_OP3_SHIFT) |
  323. (FIR_OP_CW1 << FIR_OP4_SHIFT));
  324. } else {
  325. fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
  326. (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
  327. out_be32(&lbc->fir,
  328. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  329. (FIR_OP_CM2 << FIR_OP1_SHIFT) |
  330. (FIR_OP_CA << FIR_OP2_SHIFT) |
  331. (FIR_OP_PA << FIR_OP3_SHIFT) |
  332. (FIR_OP_WB << FIR_OP4_SHIFT) |
  333. (FIR_OP_CW1 << FIR_OP5_SHIFT));
  334. if (column >= mtd->writesize) {
  335. /* OOB area --> READOOB */
  336. column -= mtd->writesize;
  337. fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
  338. ctrl->oob = 1;
  339. } else if (column < 256) {
  340. /* First 256 bytes --> READ0 */
  341. fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
  342. } else {
  343. /* Second 256 bytes --> READ1 */
  344. fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
  345. }
  346. }
  347. out_be32(&lbc->fcr, fcr);
  348. set_addr(mtd, column, page_addr, ctrl->oob);
  349. return;
  350. }
  351. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  352. case NAND_CMD_PAGEPROG: {
  353. vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
  354. "writing %d bytes.\n", ctrl->index);
  355. /* if the write did not start at 0 or is not a full page
  356. * then set the exact length, otherwise use a full page
  357. * write so the HW generates the ECC.
  358. */
  359. if (ctrl->oob || ctrl->column != 0 ||
  360. ctrl->index != mtd->writesize + mtd->oobsize)
  361. out_be32(&lbc->fbcr, ctrl->index);
  362. else
  363. out_be32(&lbc->fbcr, 0);
  364. fsl_elbc_run_command(mtd);
  365. return;
  366. }
  367. /* CMD_STATUS must read the status byte while CEB is active */
  368. /* Note - it does not wait for the ready line */
  369. case NAND_CMD_STATUS:
  370. out_be32(&lbc->fir,
  371. (FIR_OP_CM0 << FIR_OP0_SHIFT) |
  372. (FIR_OP_RBW << FIR_OP1_SHIFT));
  373. out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
  374. out_be32(&lbc->fbcr, 1);
  375. set_addr(mtd, 0, 0, 0);
  376. ctrl->read_bytes = 1;
  377. fsl_elbc_run_command(mtd);
  378. /* The chip always seems to report that it is
  379. * write-protected, even when it is not.
  380. */
  381. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  382. return;
  383. /* RESET without waiting for the ready line */
  384. case NAND_CMD_RESET:
  385. dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
  386. out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
  387. out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
  388. fsl_elbc_run_command(mtd);
  389. return;
  390. default:
  391. printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
  392. command);
  393. }
  394. }
  395. static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
  396. {
  397. /* The hardware does not seem to support multiple
  398. * chips per bank.
  399. */
  400. }
  401. /*
  402. * Write buf to the FCM Controller Data Buffer
  403. */
  404. static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  405. {
  406. struct nand_chip *chip = mtd_to_nand(mtd);
  407. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  408. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  409. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  410. if (len <= 0) {
  411. printf("write_buf of %d bytes", len);
  412. ctrl->status = 0;
  413. return;
  414. }
  415. if ((unsigned int)len > bufsize - ctrl->index) {
  416. printf("write_buf beyond end of buffer "
  417. "(%d requested, %u available)\n",
  418. len, bufsize - ctrl->index);
  419. len = bufsize - ctrl->index;
  420. }
  421. memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
  422. /*
  423. * This is workaround for the weird elbc hangs during nand write,
  424. * Scott Wood says: "...perhaps difference in how long it takes a
  425. * write to make it through the localbus compared to a write to IMMR
  426. * is causing problems, and sync isn't helping for some reason."
  427. * Reading back the last byte helps though.
  428. */
  429. in_8(&ctrl->addr[ctrl->index] + len - 1);
  430. ctrl->index += len;
  431. }
  432. /*
  433. * read a byte from either the FCM hardware buffer if it has any data left
  434. * otherwise issue a command to read a single byte.
  435. */
  436. static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
  437. {
  438. struct nand_chip *chip = mtd_to_nand(mtd);
  439. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  440. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  441. /* If there are still bytes in the FCM, then use the next byte. */
  442. if (ctrl->index < ctrl->read_bytes)
  443. return in_8(&ctrl->addr[ctrl->index++]);
  444. printf("read_byte beyond end of buffer\n");
  445. return ERR_BYTE;
  446. }
  447. /*
  448. * Read from the FCM Controller Data Buffer
  449. */
  450. static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  451. {
  452. struct nand_chip *chip = mtd_to_nand(mtd);
  453. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  454. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  455. int avail;
  456. if (len < 0)
  457. return;
  458. avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
  459. memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
  460. ctrl->index += avail;
  461. if (len > avail)
  462. printf("read_buf beyond end of buffer "
  463. "(%d requested, %d available)\n",
  464. len, avail);
  465. }
  466. /* This function is called after Program and Erase Operations to
  467. * check for success or failure.
  468. */
  469. static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  470. {
  471. struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
  472. struct fsl_elbc_ctrl *ctrl = priv->ctrl;
  473. fsl_lbc_t *lbc = ctrl->regs;
  474. if (ctrl->status != LTESR_CC)
  475. return NAND_STATUS_FAIL;
  476. /* Use READ_STATUS command, but wait for the device to be ready */
  477. ctrl->use_mdr = 0;
  478. out_be32(&lbc->fir,
  479. (FIR_OP_CW0 << FIR_OP0_SHIFT) |
  480. (FIR_OP_RBW << FIR_OP1_SHIFT));
  481. out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
  482. out_be32(&lbc->fbcr, 1);
  483. set_addr(mtd, 0, 0, 0);
  484. ctrl->read_bytes = 1;
  485. fsl_elbc_run_command(mtd);
  486. if (ctrl->status != LTESR_CC)
  487. return NAND_STATUS_FAIL;
  488. /* The chip always seems to report that it is
  489. * write-protected, even when it is not.
  490. */
  491. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  492. return fsl_elbc_read_byte(mtd);
  493. }
  494. static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  495. uint8_t *buf, int oob_required, int page)
  496. {
  497. fsl_elbc_read_buf(mtd, buf, mtd->writesize);
  498. fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  499. if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
  500. mtd->ecc_stats.failed++;
  501. return 0;
  502. }
  503. /* ECC will be calculated automatically, and errors will be detected in
  504. * waitfunc.
  505. */
  506. static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  507. const uint8_t *buf, int oob_required,
  508. int page)
  509. {
  510. fsl_elbc_write_buf(mtd, buf, mtd->writesize);
  511. fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  512. return 0;
  513. }
  514. static struct fsl_elbc_ctrl *elbc_ctrl;
  515. /* ECC will be calculated automatically, and errors will be detected in
  516. * waitfunc.
  517. */
  518. static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  519. uint32_t offset, uint32_t data_len,
  520. const uint8_t *buf, int oob_required, int page)
  521. {
  522. fsl_elbc_write_buf(mtd, buf, mtd->writesize);
  523. fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  524. return 0;
  525. }
  526. static void fsl_elbc_ctrl_init(void)
  527. {
  528. elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
  529. if (!elbc_ctrl)
  530. return;
  531. elbc_ctrl->regs = LBC_BASE_ADDR;
  532. /* clear event registers */
  533. out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
  534. out_be32(&elbc_ctrl->regs->lteatr, 0);
  535. /* Enable interrupts for any detected events */
  536. out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
  537. elbc_ctrl->read_bytes = 0;
  538. elbc_ctrl->index = 0;
  539. elbc_ctrl->addr = NULL;
  540. }
  541. static int fsl_elbc_chip_init(int devnum, u8 *addr)
  542. {
  543. struct mtd_info *mtd;
  544. struct nand_chip *nand;
  545. struct fsl_elbc_mtd *priv;
  546. uint32_t br = 0, or = 0;
  547. int ret;
  548. if (!elbc_ctrl) {
  549. fsl_elbc_ctrl_init();
  550. if (!elbc_ctrl)
  551. return -1;
  552. }
  553. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  554. if (!priv)
  555. return -ENOMEM;
  556. priv->ctrl = elbc_ctrl;
  557. priv->vbase = addr;
  558. /* Find which chip select it is connected to. It'd be nice
  559. * if we could pass more than one datum to the NAND driver...
  560. */
  561. for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
  562. phys_addr_t phys_addr = virt_to_phys(addr);
  563. br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
  564. or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
  565. if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
  566. (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
  567. break;
  568. }
  569. if (priv->bank >= MAX_BANKS) {
  570. printf("fsl_elbc_nand: address did not match any "
  571. "chip selects\n");
  572. kfree(priv);
  573. return -ENODEV;
  574. }
  575. nand = &priv->chip;
  576. mtd = nand_to_mtd(nand);
  577. elbc_ctrl->chips[priv->bank] = priv;
  578. /* fill in nand_chip structure */
  579. /* set up function call table */
  580. nand->read_byte = fsl_elbc_read_byte;
  581. nand->write_buf = fsl_elbc_write_buf;
  582. nand->read_buf = fsl_elbc_read_buf;
  583. nand->select_chip = fsl_elbc_select_chip;
  584. nand->cmdfunc = fsl_elbc_cmdfunc;
  585. nand->waitfunc = fsl_elbc_wait;
  586. /* set up nand options */
  587. nand->bbt_td = &bbt_main_descr;
  588. nand->bbt_md = &bbt_mirror_descr;
  589. /* set up nand options */
  590. nand->options = NAND_NO_SUBPAGE_WRITE;
  591. nand->bbt_options = NAND_BBT_USE_FLASH;
  592. nand->controller = &elbc_ctrl->controller;
  593. nand_set_controller_data(nand, priv);
  594. nand->ecc.read_page = fsl_elbc_read_page;
  595. nand->ecc.write_page = fsl_elbc_write_page;
  596. nand->ecc.write_subpage = fsl_elbc_write_subpage;
  597. priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
  598. /* If CS Base Register selects full hardware ECC then use it */
  599. if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
  600. nand->ecc.mode = NAND_ECC_HW;
  601. nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
  602. &fsl_elbc_oob_sp_eccm1 :
  603. &fsl_elbc_oob_sp_eccm0;
  604. nand->ecc.size = 512;
  605. nand->ecc.bytes = 3;
  606. nand->ecc.steps = 1;
  607. nand->ecc.strength = 1;
  608. } else {
  609. /* otherwise fall back to software ECC */
  610. #if defined(CONFIG_NAND_ECC_BCH)
  611. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  612. #else
  613. nand->ecc.mode = NAND_ECC_SOFT;
  614. #endif
  615. }
  616. ret = nand_scan_ident(mtd, 1, NULL);
  617. if (ret)
  618. return ret;
  619. /* Large-page-specific setup */
  620. if (mtd->writesize == 2048) {
  621. setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
  622. OR_FCM_PGS);
  623. in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
  624. priv->page_size = 1;
  625. nand->badblock_pattern = &largepage_memorybased;
  626. /*
  627. * Hardware expects small page has ECCM0, large page has
  628. * ECCM1 when booting from NAND, and we follow that even
  629. * when not booting from NAND.
  630. */
  631. priv->fmr |= FMR_ECCM;
  632. /* adjust ecc setup if needed */
  633. if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
  634. nand->ecc.steps = 4;
  635. nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
  636. &fsl_elbc_oob_lp_eccm1 :
  637. &fsl_elbc_oob_lp_eccm0;
  638. }
  639. } else if (mtd->writesize == 512) {
  640. clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
  641. OR_FCM_PGS);
  642. in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
  643. } else {
  644. return -ENODEV;
  645. }
  646. ret = nand_scan_tail(mtd);
  647. if (ret)
  648. return ret;
  649. ret = nand_register(devnum, mtd);
  650. if (ret)
  651. return ret;
  652. return 0;
  653. }
  654. #ifndef CONFIG_SYS_NAND_BASE_LIST
  655. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  656. #endif
  657. static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
  658. CONFIG_SYS_NAND_BASE_LIST;
  659. void board_nand_init(void)
  660. {
  661. int i;
  662. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  663. fsl_elbc_chip_init(i, (u8 *)base_address[i]);
  664. }