denali.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
  4. * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
  5. */
  6. #ifndef __DENALI_H__
  7. #define __DENALI_H__
  8. #include <linux/bitops.h>
  9. #include <linux/mtd/rawnand.h>
  10. #include <linux/types.h>
  11. #define DEVICE_RESET 0x0
  12. #define DEVICE_RESET__BANK(bank) BIT(bank)
  13. #define TRANSFER_SPARE_REG 0x10
  14. #define TRANSFER_SPARE_REG__FLAG BIT(0)
  15. #define LOAD_WAIT_CNT 0x20
  16. #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
  17. #define PROGRAM_WAIT_CNT 0x30
  18. #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
  19. #define ERASE_WAIT_CNT 0x40
  20. #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
  21. #define INT_MON_CYCCNT 0x50
  22. #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
  23. #define RB_PIN_ENABLED 0x60
  24. #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
  25. #define MULTIPLANE_OPERATION 0x70
  26. #define MULTIPLANE_OPERATION__FLAG BIT(0)
  27. #define MULTIPLANE_READ_ENABLE 0x80
  28. #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
  29. #define COPYBACK_DISABLE 0x90
  30. #define COPYBACK_DISABLE__FLAG BIT(0)
  31. #define CACHE_WRITE_ENABLE 0xa0
  32. #define CACHE_WRITE_ENABLE__FLAG BIT(0)
  33. #define CACHE_READ_ENABLE 0xb0
  34. #define CACHE_READ_ENABLE__FLAG BIT(0)
  35. #define PREFETCH_MODE 0xc0
  36. #define PREFETCH_MODE__PREFETCH_EN BIT(0)
  37. #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
  38. #define CHIP_ENABLE_DONT_CARE 0xd0
  39. #define CHIP_EN_DONT_CARE__FLAG BIT(0)
  40. #define ECC_ENABLE 0xe0
  41. #define ECC_ENABLE__FLAG BIT(0)
  42. #define GLOBAL_INT_ENABLE 0xf0
  43. #define GLOBAL_INT_EN_FLAG BIT(0)
  44. #define TWHR2_AND_WE_2_RE 0x100
  45. #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
  46. #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
  47. #define TCWAW_AND_ADDR_2_DATA 0x110
  48. /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
  49. #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
  50. #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
  51. #define RE_2_WE 0x120
  52. #define RE_2_WE__VALUE GENMASK(5, 0)
  53. #define ACC_CLKS 0x130
  54. #define ACC_CLKS__VALUE GENMASK(3, 0)
  55. #define NUMBER_OF_PLANES 0x140
  56. #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
  57. #define PAGES_PER_BLOCK 0x150
  58. #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
  59. #define DEVICE_WIDTH 0x160
  60. #define DEVICE_WIDTH__VALUE GENMASK(1, 0)
  61. #define DEVICE_MAIN_AREA_SIZE 0x170
  62. #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
  63. #define DEVICE_SPARE_AREA_SIZE 0x180
  64. #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
  65. #define TWO_ROW_ADDR_CYCLES 0x190
  66. #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
  67. #define MULTIPLANE_ADDR_RESTRICT 0x1a0
  68. #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
  69. #define ECC_CORRECTION 0x1b0
  70. #define ECC_CORRECTION__VALUE GENMASK(4, 0)
  71. #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
  72. #define READ_MODE 0x1c0
  73. #define READ_MODE__VALUE GENMASK(3, 0)
  74. #define WRITE_MODE 0x1d0
  75. #define WRITE_MODE__VALUE GENMASK(3, 0)
  76. #define COPYBACK_MODE 0x1e0
  77. #define COPYBACK_MODE__VALUE GENMASK(3, 0)
  78. #define RDWR_EN_LO_CNT 0x1f0
  79. #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
  80. #define RDWR_EN_HI_CNT 0x200
  81. #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
  82. #define MAX_RD_DELAY 0x210
  83. #define MAX_RD_DELAY__VALUE GENMASK(3, 0)
  84. #define CS_SETUP_CNT 0x220
  85. #define CS_SETUP_CNT__VALUE GENMASK(4, 0)
  86. #define CS_SETUP_CNT__TWB GENMASK(17, 12)
  87. #define SPARE_AREA_SKIP_BYTES 0x230
  88. #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
  89. #define SPARE_AREA_MARKER 0x240
  90. #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
  91. #define DEVICES_CONNECTED 0x250
  92. #define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
  93. #define DIE_MASK 0x260
  94. #define DIE_MASK__VALUE GENMASK(7, 0)
  95. #define FIRST_BLOCK_OF_NEXT_PLANE 0x270
  96. #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
  97. #define WRITE_PROTECT 0x280
  98. #define WRITE_PROTECT__FLAG BIT(0)
  99. #define RE_2_RE 0x290
  100. #define RE_2_RE__VALUE GENMASK(5, 0)
  101. #define MANUFACTURER_ID 0x300
  102. #define MANUFACTURER_ID__VALUE GENMASK(7, 0)
  103. #define DEVICE_ID 0x310
  104. #define DEVICE_ID__VALUE GENMASK(7, 0)
  105. #define DEVICE_PARAM_0 0x320
  106. #define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
  107. #define DEVICE_PARAM_1 0x330
  108. #define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
  109. #define DEVICE_PARAM_2 0x340
  110. #define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
  111. #define LOGICAL_PAGE_DATA_SIZE 0x350
  112. #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
  113. #define LOGICAL_PAGE_SPARE_SIZE 0x360
  114. #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
  115. #define REVISION 0x370
  116. #define REVISION__VALUE GENMASK(15, 0)
  117. #define ONFI_DEVICE_FEATURES 0x380
  118. #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
  119. #define ONFI_OPTIONAL_COMMANDS 0x390
  120. #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
  121. #define ONFI_TIMING_MODE 0x3a0
  122. #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
  123. #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
  124. #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
  125. #define ONFI_DEVICE_NO_OF_LUNS 0x3c0
  126. #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
  127. #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
  128. #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
  129. #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
  130. #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
  131. #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
  132. #define FEATURES 0x3f0
  133. #define FEATURES__N_BANKS GENMASK(1, 0)
  134. #define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
  135. #define FEATURES__DMA BIT(6)
  136. #define FEATURES__CMD_DMA BIT(7)
  137. #define FEATURES__PARTITION BIT(8)
  138. #define FEATURES__XDMA_SIDEBAND BIT(9)
  139. #define FEATURES__GPREG BIT(10)
  140. #define FEATURES__INDEX_ADDR BIT(11)
  141. #define TRANSFER_MODE 0x400
  142. #define TRANSFER_MODE__VALUE GENMASK(1, 0)
  143. #define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
  144. #define INTR_EN(bank) (0x420 + (bank) * 0x50)
  145. /* bit[1:0] is used differently depending on IP version */
  146. #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
  147. #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
  148. #define INTR__ECC_ERR BIT(1) /* old IP */
  149. #define INTR__DMA_CMD_COMP BIT(2)
  150. #define INTR__TIME_OUT BIT(3)
  151. #define INTR__PROGRAM_FAIL BIT(4)
  152. #define INTR__ERASE_FAIL BIT(5)
  153. #define INTR__LOAD_COMP BIT(6)
  154. #define INTR__PROGRAM_COMP BIT(7)
  155. #define INTR__ERASE_COMP BIT(8)
  156. #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
  157. #define INTR__LOCKED_BLK BIT(10)
  158. #define INTR__UNSUP_CMD BIT(11)
  159. #define INTR__INT_ACT BIT(12)
  160. #define INTR__RST_COMP BIT(13)
  161. #define INTR__PIPE_CMD_ERR BIT(14)
  162. #define INTR__PAGE_XFER_INC BIT(15)
  163. #define INTR__ERASED_PAGE BIT(16)
  164. #define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
  165. #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
  166. #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
  167. #define ECC_THRESHOLD 0x600
  168. #define ECC_THRESHOLD__VALUE GENMASK(9, 0)
  169. #define ECC_ERROR_BLOCK_ADDRESS 0x610
  170. #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
  171. #define ECC_ERROR_PAGE_ADDRESS 0x620
  172. #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
  173. #define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
  174. #define ECC_ERROR_ADDRESS 0x630
  175. #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
  176. #define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12)
  177. #define ERR_CORRECTION_INFO 0x640
  178. #define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
  179. #define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8)
  180. #define ERR_CORRECTION_INFO__UNCOR BIT(14)
  181. #define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
  182. #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
  183. #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
  184. #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
  185. #define ECC_COR_INFO__UNCOR_ERR BIT(7)
  186. #define CFG_DATA_BLOCK_SIZE 0x6b0
  187. #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
  188. #define CFG_NUM_DATA_BLOCKS 0x6d0
  189. #define CFG_META_DATA_SIZE 0x6e0
  190. #define DMA_ENABLE 0x700
  191. #define DMA_ENABLE__FLAG BIT(0)
  192. #define IGNORE_ECC_DONE 0x710
  193. #define IGNORE_ECC_DONE__FLAG BIT(0)
  194. #define DMA_INTR 0x720
  195. #define DMA_INTR_EN 0x730
  196. #define DMA_INTR__TARGET_ERROR BIT(0)
  197. #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
  198. #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
  199. #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
  200. #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
  201. #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
  202. #define TARGET_ERR_ADDR_LO 0x740
  203. #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
  204. #define TARGET_ERR_ADDR_HI 0x750
  205. #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
  206. #define CHNL_ACTIVE 0x760
  207. #define CHNL_ACTIVE__CHANNEL0 BIT(0)
  208. #define CHNL_ACTIVE__CHANNEL1 BIT(1)
  209. #define CHNL_ACTIVE__CHANNEL2 BIT(2)
  210. #define CHNL_ACTIVE__CHANNEL3 BIT(3)
  211. struct udevice;
  212. struct denali_nand_info {
  213. struct nand_chip nand;
  214. unsigned long clk_x_rate; /* bus interface clock rate */
  215. int active_bank; /* currently selected bank */
  216. struct udevice *dev;
  217. uint32_t page;
  218. void __iomem *reg; /* Register Interface */
  219. void __iomem *host; /* Host Data/Command Interface */
  220. u32 irq_mask; /* interrupts we are waiting for */
  221. u32 irq_status; /* interrupts that have happened */
  222. int irq;
  223. void *buf; /* for syndrome layout conversion */
  224. dma_addr_t dma_addr;
  225. int dma_avail; /* can support DMA? */
  226. int devs_per_cs; /* devices connected in parallel */
  227. int oob_skip_bytes; /* number of bytes reserved for BBM */
  228. int max_banks;
  229. unsigned int revision; /* IP revision */
  230. unsigned int caps; /* IP capability (or quirk) */
  231. const struct nand_ecc_caps *ecc_caps;
  232. u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
  233. void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
  234. void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
  235. int page, int write);
  236. };
  237. #define DENALI_CAP_HW_ECC_FIXUP BIT(0)
  238. #define DENALI_CAP_DMA_64BIT BIT(1)
  239. int denali_calc_ecc_bytes(int step_size, int strength);
  240. int denali_init(struct denali_nand_info *denali);
  241. #endif /* __DENALI_H__ */