denali.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Panasonic Corporation
  4. * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
  5. * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
  6. */
  7. #include <dm.h>
  8. #include <nand.h>
  9. #include <linux/bitfield.h>
  10. #include <linux/dma-direction.h>
  11. #include <linux/errno.h>
  12. #include <linux/io.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/rawnand.h>
  15. #include "denali.h"
  16. static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
  17. enum dma_data_direction dir)
  18. {
  19. unsigned long addr = (unsigned long)ptr;
  20. size = ALIGN(size, ARCH_DMA_MINALIGN);
  21. if (dir == DMA_FROM_DEVICE)
  22. invalidate_dcache_range(addr, addr + size);
  23. else
  24. flush_dcache_range(addr, addr + size);
  25. return addr;
  26. }
  27. static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
  28. enum dma_data_direction dir)
  29. {
  30. size = ALIGN(size, ARCH_DMA_MINALIGN);
  31. if (dir != DMA_TO_DEVICE)
  32. invalidate_dcache_range(addr, addr + size);
  33. }
  34. static int dma_mapping_error(void *dev, dma_addr_t addr)
  35. {
  36. return 0;
  37. }
  38. #define DENALI_NAND_NAME "denali-nand"
  39. /* for Indexed Addressing */
  40. #define DENALI_INDEXED_CTRL 0x00
  41. #define DENALI_INDEXED_DATA 0x10
  42. #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
  43. #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
  44. #define DENALI_MAP10 (2 << 26) /* high-level control plane */
  45. #define DENALI_MAP11 (3 << 26) /* direct controller access */
  46. /* MAP11 access cycle type */
  47. #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
  48. #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
  49. #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
  50. /* MAP10 commands */
  51. #define DENALI_ERASE 0x01
  52. #define DENALI_BANK(denali) ((denali)->active_bank << 24)
  53. #define DENALI_INVALID_BANK -1
  54. #define DENALI_NR_BANKS 4
  55. /*
  56. * The bus interface clock, clk_x, is phase aligned with the core clock. The
  57. * clk_x is an integral multiple N of the core clk. The value N is configured
  58. * at IP delivery time, and its available value is 4, 5, or 6. We need to align
  59. * to the largest value to make it work with any possible configuration.
  60. */
  61. #define DENALI_CLK_X_MULT 6
  62. static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
  63. {
  64. return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
  65. }
  66. /*
  67. * Direct Addressing - the slave address forms the control information (command
  68. * type, bank, block, and page address). The slave data is the actual data to
  69. * be transferred. This mode requires 28 bits of address region allocated.
  70. */
  71. static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
  72. {
  73. return ioread32(denali->host + addr);
  74. }
  75. static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
  76. u32 data)
  77. {
  78. iowrite32(data, denali->host + addr);
  79. }
  80. /*
  81. * Indexed Addressing - address translation module intervenes in passing the
  82. * control information. This mode reduces the required address range. The
  83. * control information and transferred data are latched by the registers in
  84. * the translation module.
  85. */
  86. static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
  87. {
  88. iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
  89. return ioread32(denali->host + DENALI_INDEXED_DATA);
  90. }
  91. static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
  92. u32 data)
  93. {
  94. iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
  95. iowrite32(data, denali->host + DENALI_INDEXED_DATA);
  96. }
  97. /*
  98. * Use the configuration feature register to determine the maximum number of
  99. * banks that the hardware supports.
  100. */
  101. static void denali_detect_max_banks(struct denali_nand_info *denali)
  102. {
  103. uint32_t features = ioread32(denali->reg + FEATURES);
  104. denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
  105. /* the encoding changed from rev 5.0 to 5.1 */
  106. if (denali->revision < 0x0501)
  107. denali->max_banks <<= 1;
  108. }
  109. static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
  110. {
  111. int i;
  112. for (i = 0; i < DENALI_NR_BANKS; i++)
  113. iowrite32(U32_MAX, denali->reg + INTR_EN(i));
  114. iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
  115. }
  116. static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
  117. {
  118. int i;
  119. for (i = 0; i < DENALI_NR_BANKS; i++)
  120. iowrite32(0, denali->reg + INTR_EN(i));
  121. iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
  122. }
  123. static void denali_clear_irq(struct denali_nand_info *denali,
  124. int bank, uint32_t irq_status)
  125. {
  126. /* write one to clear bits */
  127. iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
  128. }
  129. static void denali_clear_irq_all(struct denali_nand_info *denali)
  130. {
  131. int i;
  132. for (i = 0; i < DENALI_NR_BANKS; i++)
  133. denali_clear_irq(denali, i, U32_MAX);
  134. }
  135. static void __denali_check_irq(struct denali_nand_info *denali)
  136. {
  137. uint32_t irq_status;
  138. int i;
  139. for (i = 0; i < DENALI_NR_BANKS; i++) {
  140. irq_status = ioread32(denali->reg + INTR_STATUS(i));
  141. denali_clear_irq(denali, i, irq_status);
  142. if (i != denali->active_bank)
  143. continue;
  144. denali->irq_status |= irq_status;
  145. }
  146. }
  147. static void denali_reset_irq(struct denali_nand_info *denali)
  148. {
  149. denali->irq_status = 0;
  150. denali->irq_mask = 0;
  151. }
  152. static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
  153. uint32_t irq_mask)
  154. {
  155. unsigned long time_left = 1000000;
  156. while (time_left) {
  157. __denali_check_irq(denali);
  158. if (irq_mask & denali->irq_status)
  159. return denali->irq_status;
  160. udelay(1);
  161. time_left--;
  162. }
  163. if (!time_left) {
  164. dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
  165. irq_mask);
  166. return 0;
  167. }
  168. return denali->irq_status;
  169. }
  170. static uint32_t denali_check_irq(struct denali_nand_info *denali)
  171. {
  172. __denali_check_irq(denali);
  173. return denali->irq_status;
  174. }
  175. static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  176. {
  177. struct denali_nand_info *denali = mtd_to_denali(mtd);
  178. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  179. int i;
  180. for (i = 0; i < len; i++)
  181. buf[i] = denali->host_read(denali, addr);
  182. }
  183. static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  184. {
  185. struct denali_nand_info *denali = mtd_to_denali(mtd);
  186. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  187. int i;
  188. for (i = 0; i < len; i++)
  189. denali->host_write(denali, addr, buf[i]);
  190. }
  191. static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  192. {
  193. struct denali_nand_info *denali = mtd_to_denali(mtd);
  194. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  195. uint16_t *buf16 = (uint16_t *)buf;
  196. int i;
  197. for (i = 0; i < len / 2; i++)
  198. buf16[i] = denali->host_read(denali, addr);
  199. }
  200. static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
  201. int len)
  202. {
  203. struct denali_nand_info *denali = mtd_to_denali(mtd);
  204. u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
  205. const uint16_t *buf16 = (const uint16_t *)buf;
  206. int i;
  207. for (i = 0; i < len / 2; i++)
  208. denali->host_write(denali, addr, buf16[i]);
  209. }
  210. static uint8_t denali_read_byte(struct mtd_info *mtd)
  211. {
  212. uint8_t byte;
  213. denali_read_buf(mtd, &byte, 1);
  214. return byte;
  215. }
  216. static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
  217. {
  218. denali_write_buf(mtd, &byte, 1);
  219. }
  220. static uint16_t denali_read_word(struct mtd_info *mtd)
  221. {
  222. uint16_t word;
  223. denali_read_buf16(mtd, (uint8_t *)&word, 2);
  224. return word;
  225. }
  226. static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
  227. {
  228. struct denali_nand_info *denali = mtd_to_denali(mtd);
  229. uint32_t type;
  230. if (ctrl & NAND_CLE)
  231. type = DENALI_MAP11_CMD;
  232. else if (ctrl & NAND_ALE)
  233. type = DENALI_MAP11_ADDR;
  234. else
  235. return;
  236. /*
  237. * Some commands are followed by chip->dev_ready or chip->waitfunc.
  238. * irq_status must be cleared here to catch the R/B# interrupt later.
  239. */
  240. if (ctrl & NAND_CTRL_CHANGE)
  241. denali_reset_irq(denali);
  242. denali->host_write(denali, DENALI_BANK(denali) | type, dat);
  243. }
  244. static int denali_dev_ready(struct mtd_info *mtd)
  245. {
  246. struct denali_nand_info *denali = mtd_to_denali(mtd);
  247. return !!(denali_check_irq(denali) & INTR__INT_ACT);
  248. }
  249. static int denali_check_erased_page(struct mtd_info *mtd,
  250. struct nand_chip *chip, uint8_t *buf,
  251. unsigned long uncor_ecc_flags,
  252. unsigned int max_bitflips)
  253. {
  254. uint8_t *ecc_code = chip->buffers->ecccode;
  255. int ecc_steps = chip->ecc.steps;
  256. int ecc_size = chip->ecc.size;
  257. int ecc_bytes = chip->ecc.bytes;
  258. int i, ret, stat;
  259. ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
  260. chip->ecc.total);
  261. if (ret)
  262. return ret;
  263. for (i = 0; i < ecc_steps; i++) {
  264. if (!(uncor_ecc_flags & BIT(i)))
  265. continue;
  266. stat = nand_check_erased_ecc_chunk(buf, ecc_size,
  267. ecc_code, ecc_bytes,
  268. NULL, 0,
  269. chip->ecc.strength);
  270. if (stat < 0) {
  271. mtd->ecc_stats.failed++;
  272. } else {
  273. mtd->ecc_stats.corrected += stat;
  274. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  275. }
  276. buf += ecc_size;
  277. ecc_code += ecc_bytes;
  278. }
  279. return max_bitflips;
  280. }
  281. static int denali_hw_ecc_fixup(struct mtd_info *mtd,
  282. struct denali_nand_info *denali,
  283. unsigned long *uncor_ecc_flags)
  284. {
  285. struct nand_chip *chip = mtd_to_nand(mtd);
  286. int bank = denali->active_bank;
  287. uint32_t ecc_cor;
  288. unsigned int max_bitflips;
  289. ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
  290. ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
  291. if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
  292. /*
  293. * This flag is set when uncorrectable error occurs at least in
  294. * one ECC sector. We can not know "how many sectors", or
  295. * "which sector(s)". We need erase-page check for all sectors.
  296. */
  297. *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
  298. return 0;
  299. }
  300. max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
  301. /*
  302. * The register holds the maximum of per-sector corrected bitflips.
  303. * This is suitable for the return value of the ->read_page() callback.
  304. * Unfortunately, we can not know the total number of corrected bits in
  305. * the page. Increase the stats by max_bitflips. (compromised solution)
  306. */
  307. mtd->ecc_stats.corrected += max_bitflips;
  308. return max_bitflips;
  309. }
  310. static int denali_sw_ecc_fixup(struct mtd_info *mtd,
  311. struct denali_nand_info *denali,
  312. unsigned long *uncor_ecc_flags, uint8_t *buf)
  313. {
  314. unsigned int ecc_size = denali->nand.ecc.size;
  315. unsigned int bitflips = 0;
  316. unsigned int max_bitflips = 0;
  317. uint32_t err_addr, err_cor_info;
  318. unsigned int err_byte, err_sector, err_device;
  319. uint8_t err_cor_value;
  320. unsigned int prev_sector = 0;
  321. uint32_t irq_status;
  322. denali_reset_irq(denali);
  323. do {
  324. err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
  325. err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
  326. err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
  327. err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
  328. err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
  329. err_cor_info);
  330. err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
  331. err_cor_info);
  332. /* reset the bitflip counter when crossing ECC sector */
  333. if (err_sector != prev_sector)
  334. bitflips = 0;
  335. if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
  336. /*
  337. * Check later if this is a real ECC error, or
  338. * an erased sector.
  339. */
  340. *uncor_ecc_flags |= BIT(err_sector);
  341. } else if (err_byte < ecc_size) {
  342. /*
  343. * If err_byte is larger than ecc_size, means error
  344. * happened in OOB, so we ignore it. It's no need for
  345. * us to correct it err_device is represented the NAND
  346. * error bits are happened in if there are more than
  347. * one NAND connected.
  348. */
  349. int offset;
  350. unsigned int flips_in_byte;
  351. offset = (err_sector * ecc_size + err_byte) *
  352. denali->devs_per_cs + err_device;
  353. /* correct the ECC error */
  354. flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
  355. buf[offset] ^= err_cor_value;
  356. mtd->ecc_stats.corrected += flips_in_byte;
  357. bitflips += flips_in_byte;
  358. max_bitflips = max(max_bitflips, bitflips);
  359. }
  360. prev_sector = err_sector;
  361. } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
  362. /*
  363. * Once handle all ECC errors, controller will trigger an
  364. * ECC_TRANSACTION_DONE interrupt.
  365. */
  366. irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
  367. if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
  368. return -EIO;
  369. return max_bitflips;
  370. }
  371. static void denali_setup_dma64(struct denali_nand_info *denali,
  372. dma_addr_t dma_addr, int page, int write)
  373. {
  374. uint32_t mode;
  375. const int page_count = 1;
  376. mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
  377. /* DMA is a three step process */
  378. /*
  379. * 1. setup transfer type, interrupt when complete,
  380. * burst len = 64 bytes, the number of pages
  381. */
  382. denali->host_write(denali, mode,
  383. 0x01002000 | (64 << 16) | (write << 8) | page_count);
  384. /* 2. set memory low address */
  385. denali->host_write(denali, mode, lower_32_bits(dma_addr));
  386. /* 3. set memory high address */
  387. denali->host_write(denali, mode, upper_32_bits(dma_addr));
  388. }
  389. static void denali_setup_dma32(struct denali_nand_info *denali,
  390. dma_addr_t dma_addr, int page, int write)
  391. {
  392. uint32_t mode;
  393. const int page_count = 1;
  394. mode = DENALI_MAP10 | DENALI_BANK(denali);
  395. /* DMA is a four step process */
  396. /* 1. setup transfer type and # of pages */
  397. denali->host_write(denali, mode | page,
  398. 0x2000 | (write << 8) | page_count);
  399. /* 2. set memory high address bits 23:8 */
  400. denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
  401. /* 3. set memory low address bits 23:8 */
  402. denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
  403. /* 4. interrupt when complete, burst len = 64 bytes */
  404. denali->host_write(denali, mode | 0x14000, 0x2400);
  405. }
  406. static int denali_pio_read(struct denali_nand_info *denali, void *buf,
  407. size_t size, int page, int raw)
  408. {
  409. u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
  410. uint32_t *buf32 = (uint32_t *)buf;
  411. uint32_t irq_status, ecc_err_mask;
  412. int i;
  413. if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
  414. ecc_err_mask = INTR__ECC_UNCOR_ERR;
  415. else
  416. ecc_err_mask = INTR__ECC_ERR;
  417. denali_reset_irq(denali);
  418. for (i = 0; i < size / 4; i++)
  419. *buf32++ = denali->host_read(denali, addr);
  420. irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
  421. if (!(irq_status & INTR__PAGE_XFER_INC))
  422. return -EIO;
  423. if (irq_status & INTR__ERASED_PAGE)
  424. memset(buf, 0xff, size);
  425. return irq_status & ecc_err_mask ? -EBADMSG : 0;
  426. }
  427. static int denali_pio_write(struct denali_nand_info *denali,
  428. const void *buf, size_t size, int page, int raw)
  429. {
  430. u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
  431. const uint32_t *buf32 = (uint32_t *)buf;
  432. uint32_t irq_status;
  433. int i;
  434. denali_reset_irq(denali);
  435. for (i = 0; i < size / 4; i++)
  436. denali->host_write(denali, addr, *buf32++);
  437. irq_status = denali_wait_for_irq(denali,
  438. INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
  439. if (!(irq_status & INTR__PROGRAM_COMP))
  440. return -EIO;
  441. return 0;
  442. }
  443. static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
  444. size_t size, int page, int raw, int write)
  445. {
  446. if (write)
  447. return denali_pio_write(denali, buf, size, page, raw);
  448. else
  449. return denali_pio_read(denali, buf, size, page, raw);
  450. }
  451. static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
  452. size_t size, int page, int raw, int write)
  453. {
  454. dma_addr_t dma_addr;
  455. uint32_t irq_mask, irq_status, ecc_err_mask;
  456. enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  457. int ret = 0;
  458. dma_addr = dma_map_single(denali->dev, buf, size, dir);
  459. if (dma_mapping_error(denali->dev, dma_addr)) {
  460. dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
  461. return denali_pio_xfer(denali, buf, size, page, raw, write);
  462. }
  463. if (write) {
  464. /*
  465. * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
  466. * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
  467. * when the page program is completed.
  468. */
  469. irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
  470. ecc_err_mask = 0;
  471. } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
  472. irq_mask = INTR__DMA_CMD_COMP;
  473. ecc_err_mask = INTR__ECC_UNCOR_ERR;
  474. } else {
  475. irq_mask = INTR__DMA_CMD_COMP;
  476. ecc_err_mask = INTR__ECC_ERR;
  477. }
  478. iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
  479. denali_reset_irq(denali);
  480. denali->setup_dma(denali, dma_addr, page, write);
  481. irq_status = denali_wait_for_irq(denali, irq_mask);
  482. if (!(irq_status & INTR__DMA_CMD_COMP))
  483. ret = -EIO;
  484. else if (irq_status & ecc_err_mask)
  485. ret = -EBADMSG;
  486. iowrite32(0, denali->reg + DMA_ENABLE);
  487. dma_unmap_single(denali->dev, dma_addr, size, dir);
  488. if (irq_status & INTR__ERASED_PAGE)
  489. memset(buf, 0xff, size);
  490. return ret;
  491. }
  492. static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
  493. size_t size, int page, int raw, int write)
  494. {
  495. iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
  496. iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
  497. denali->reg + TRANSFER_SPARE_REG);
  498. if (denali->dma_avail)
  499. return denali_dma_xfer(denali, buf, size, page, raw, write);
  500. else
  501. return denali_pio_xfer(denali, buf, size, page, raw, write);
  502. }
  503. static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
  504. int page, int write)
  505. {
  506. struct denali_nand_info *denali = mtd_to_denali(mtd);
  507. unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
  508. unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
  509. int writesize = mtd->writesize;
  510. int oobsize = mtd->oobsize;
  511. uint8_t *bufpoi = chip->oob_poi;
  512. int ecc_steps = chip->ecc.steps;
  513. int ecc_size = chip->ecc.size;
  514. int ecc_bytes = chip->ecc.bytes;
  515. int oob_skip = denali->oob_skip_bytes;
  516. size_t size = writesize + oobsize;
  517. int i, pos, len;
  518. /* BBM at the beginning of the OOB area */
  519. chip->cmdfunc(mtd, start_cmd, writesize, page);
  520. if (write)
  521. chip->write_buf(mtd, bufpoi, oob_skip);
  522. else
  523. chip->read_buf(mtd, bufpoi, oob_skip);
  524. bufpoi += oob_skip;
  525. /* OOB ECC */
  526. for (i = 0; i < ecc_steps; i++) {
  527. pos = ecc_size + i * (ecc_size + ecc_bytes);
  528. len = ecc_bytes;
  529. if (pos >= writesize)
  530. pos += oob_skip;
  531. else if (pos + len > writesize)
  532. len = writesize - pos;
  533. chip->cmdfunc(mtd, rnd_cmd, pos, -1);
  534. if (write)
  535. chip->write_buf(mtd, bufpoi, len);
  536. else
  537. chip->read_buf(mtd, bufpoi, len);
  538. bufpoi += len;
  539. if (len < ecc_bytes) {
  540. len = ecc_bytes - len;
  541. chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
  542. if (write)
  543. chip->write_buf(mtd, bufpoi, len);
  544. else
  545. chip->read_buf(mtd, bufpoi, len);
  546. bufpoi += len;
  547. }
  548. }
  549. /* OOB free */
  550. len = oobsize - (bufpoi - chip->oob_poi);
  551. chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
  552. if (write)
  553. chip->write_buf(mtd, bufpoi, len);
  554. else
  555. chip->read_buf(mtd, bufpoi, len);
  556. }
  557. static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  558. uint8_t *buf, int oob_required, int page)
  559. {
  560. struct denali_nand_info *denali = mtd_to_denali(mtd);
  561. int writesize = mtd->writesize;
  562. int oobsize = mtd->oobsize;
  563. int ecc_steps = chip->ecc.steps;
  564. int ecc_size = chip->ecc.size;
  565. int ecc_bytes = chip->ecc.bytes;
  566. void *tmp_buf = denali->buf;
  567. int oob_skip = denali->oob_skip_bytes;
  568. size_t size = writesize + oobsize;
  569. int ret, i, pos, len;
  570. ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
  571. if (ret)
  572. return ret;
  573. /* Arrange the buffer for syndrome payload/ecc layout */
  574. if (buf) {
  575. for (i = 0; i < ecc_steps; i++) {
  576. pos = i * (ecc_size + ecc_bytes);
  577. len = ecc_size;
  578. if (pos >= writesize)
  579. pos += oob_skip;
  580. else if (pos + len > writesize)
  581. len = writesize - pos;
  582. memcpy(buf, tmp_buf + pos, len);
  583. buf += len;
  584. if (len < ecc_size) {
  585. len = ecc_size - len;
  586. memcpy(buf, tmp_buf + writesize + oob_skip,
  587. len);
  588. buf += len;
  589. }
  590. }
  591. }
  592. if (oob_required) {
  593. uint8_t *oob = chip->oob_poi;
  594. /* BBM at the beginning of the OOB area */
  595. memcpy(oob, tmp_buf + writesize, oob_skip);
  596. oob += oob_skip;
  597. /* OOB ECC */
  598. for (i = 0; i < ecc_steps; i++) {
  599. pos = ecc_size + i * (ecc_size + ecc_bytes);
  600. len = ecc_bytes;
  601. if (pos >= writesize)
  602. pos += oob_skip;
  603. else if (pos + len > writesize)
  604. len = writesize - pos;
  605. memcpy(oob, tmp_buf + pos, len);
  606. oob += len;
  607. if (len < ecc_bytes) {
  608. len = ecc_bytes - len;
  609. memcpy(oob, tmp_buf + writesize + oob_skip,
  610. len);
  611. oob += len;
  612. }
  613. }
  614. /* OOB free */
  615. len = oobsize - (oob - chip->oob_poi);
  616. memcpy(oob, tmp_buf + size - len, len);
  617. }
  618. return 0;
  619. }
  620. static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  621. int page)
  622. {
  623. denali_oob_xfer(mtd, chip, page, 0);
  624. return 0;
  625. }
  626. static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  627. int page)
  628. {
  629. struct denali_nand_info *denali = mtd_to_denali(mtd);
  630. int status;
  631. denali_reset_irq(denali);
  632. denali_oob_xfer(mtd, chip, page, 1);
  633. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  634. status = chip->waitfunc(mtd, chip);
  635. return status & NAND_STATUS_FAIL ? -EIO : 0;
  636. }
  637. static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  638. uint8_t *buf, int oob_required, int page)
  639. {
  640. struct denali_nand_info *denali = mtd_to_denali(mtd);
  641. unsigned long uncor_ecc_flags = 0;
  642. int stat = 0;
  643. int ret;
  644. ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
  645. if (ret && ret != -EBADMSG)
  646. return ret;
  647. if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
  648. stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
  649. else if (ret == -EBADMSG)
  650. stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
  651. if (stat < 0)
  652. return stat;
  653. if (uncor_ecc_flags) {
  654. ret = denali_read_oob(mtd, chip, page);
  655. if (ret)
  656. return ret;
  657. stat = denali_check_erased_page(mtd, chip, buf,
  658. uncor_ecc_flags, stat);
  659. }
  660. return stat;
  661. }
  662. static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  663. const uint8_t *buf, int oob_required, int page)
  664. {
  665. struct denali_nand_info *denali = mtd_to_denali(mtd);
  666. int writesize = mtd->writesize;
  667. int oobsize = mtd->oobsize;
  668. int ecc_steps = chip->ecc.steps;
  669. int ecc_size = chip->ecc.size;
  670. int ecc_bytes = chip->ecc.bytes;
  671. void *tmp_buf = denali->buf;
  672. int oob_skip = denali->oob_skip_bytes;
  673. size_t size = writesize + oobsize;
  674. int i, pos, len;
  675. /*
  676. * Fill the buffer with 0xff first except the full page transfer.
  677. * This simplifies the logic.
  678. */
  679. if (!buf || !oob_required)
  680. memset(tmp_buf, 0xff, size);
  681. /* Arrange the buffer for syndrome payload/ecc layout */
  682. if (buf) {
  683. for (i = 0; i < ecc_steps; i++) {
  684. pos = i * (ecc_size + ecc_bytes);
  685. len = ecc_size;
  686. if (pos >= writesize)
  687. pos += oob_skip;
  688. else if (pos + len > writesize)
  689. len = writesize - pos;
  690. memcpy(tmp_buf + pos, buf, len);
  691. buf += len;
  692. if (len < ecc_size) {
  693. len = ecc_size - len;
  694. memcpy(tmp_buf + writesize + oob_skip, buf,
  695. len);
  696. buf += len;
  697. }
  698. }
  699. }
  700. if (oob_required) {
  701. const uint8_t *oob = chip->oob_poi;
  702. /* BBM at the beginning of the OOB area */
  703. memcpy(tmp_buf + writesize, oob, oob_skip);
  704. oob += oob_skip;
  705. /* OOB ECC */
  706. for (i = 0; i < ecc_steps; i++) {
  707. pos = ecc_size + i * (ecc_size + ecc_bytes);
  708. len = ecc_bytes;
  709. if (pos >= writesize)
  710. pos += oob_skip;
  711. else if (pos + len > writesize)
  712. len = writesize - pos;
  713. memcpy(tmp_buf + pos, oob, len);
  714. oob += len;
  715. if (len < ecc_bytes) {
  716. len = ecc_bytes - len;
  717. memcpy(tmp_buf + writesize + oob_skip, oob,
  718. len);
  719. oob += len;
  720. }
  721. }
  722. /* OOB free */
  723. len = oobsize - (oob - chip->oob_poi);
  724. memcpy(tmp_buf + size - len, oob, len);
  725. }
  726. return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
  727. }
  728. static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  729. const uint8_t *buf, int oob_required, int page)
  730. {
  731. struct denali_nand_info *denali = mtd_to_denali(mtd);
  732. return denali_data_xfer(denali, (void *)buf, mtd->writesize,
  733. page, 0, 1);
  734. }
  735. static void denali_select_chip(struct mtd_info *mtd, int chip)
  736. {
  737. struct denali_nand_info *denali = mtd_to_denali(mtd);
  738. denali->active_bank = chip;
  739. }
  740. static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
  741. {
  742. struct denali_nand_info *denali = mtd_to_denali(mtd);
  743. uint32_t irq_status;
  744. /* R/B# pin transitioned from low to high? */
  745. irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
  746. return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
  747. }
  748. static int denali_erase(struct mtd_info *mtd, int page)
  749. {
  750. struct denali_nand_info *denali = mtd_to_denali(mtd);
  751. uint32_t irq_status;
  752. denali_reset_irq(denali);
  753. denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
  754. DENALI_ERASE);
  755. /* wait for erase to complete or failure to occur */
  756. irq_status = denali_wait_for_irq(denali,
  757. INTR__ERASE_COMP | INTR__ERASE_FAIL);
  758. return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
  759. }
  760. static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
  761. const struct nand_data_interface *conf)
  762. {
  763. struct denali_nand_info *denali = mtd_to_denali(mtd);
  764. const struct nand_sdr_timings *timings;
  765. unsigned long t_clk;
  766. int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
  767. int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
  768. int addr_2_data_mask;
  769. uint32_t tmp;
  770. timings = nand_get_sdr_timings(conf);
  771. if (IS_ERR(timings))
  772. return PTR_ERR(timings);
  773. /* clk_x period in picoseconds */
  774. t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
  775. if (!t_clk)
  776. return -EINVAL;
  777. if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
  778. return 0;
  779. /* tREA -> ACC_CLKS */
  780. acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
  781. acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
  782. tmp = ioread32(denali->reg + ACC_CLKS);
  783. tmp &= ~ACC_CLKS__VALUE;
  784. tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
  785. iowrite32(tmp, denali->reg + ACC_CLKS);
  786. /* tRWH -> RE_2_WE */
  787. re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
  788. re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
  789. tmp = ioread32(denali->reg + RE_2_WE);
  790. tmp &= ~RE_2_WE__VALUE;
  791. tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
  792. iowrite32(tmp, denali->reg + RE_2_WE);
  793. /* tRHZ -> RE_2_RE */
  794. re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
  795. re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
  796. tmp = ioread32(denali->reg + RE_2_RE);
  797. tmp &= ~RE_2_RE__VALUE;
  798. tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
  799. iowrite32(tmp, denali->reg + RE_2_RE);
  800. /*
  801. * tCCS, tWHR -> WE_2_RE
  802. *
  803. * With WE_2_RE properly set, the Denali controller automatically takes
  804. * care of the delay; the driver need not set NAND_WAIT_TCCS.
  805. */
  806. we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
  807. t_clk);
  808. we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
  809. tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
  810. tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
  811. tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
  812. iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
  813. /* tADL -> ADDR_2_DATA */
  814. /* for older versions, ADDR_2_DATA is only 6 bit wide */
  815. addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
  816. if (denali->revision < 0x0501)
  817. addr_2_data_mask >>= 1;
  818. addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
  819. addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
  820. tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
  821. tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
  822. tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
  823. iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
  824. /* tREH, tWH -> RDWR_EN_HI_CNT */
  825. rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
  826. t_clk);
  827. rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
  828. tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
  829. tmp &= ~RDWR_EN_HI_CNT__VALUE;
  830. tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
  831. iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
  832. /* tRP, tWP -> RDWR_EN_LO_CNT */
  833. rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
  834. t_clk);
  835. rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
  836. t_clk);
  837. rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
  838. rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
  839. rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
  840. tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
  841. tmp &= ~RDWR_EN_LO_CNT__VALUE;
  842. tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
  843. iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
  844. /* tCS, tCEA -> CS_SETUP_CNT */
  845. cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
  846. (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
  847. 0);
  848. cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
  849. tmp = ioread32(denali->reg + CS_SETUP_CNT);
  850. tmp &= ~CS_SETUP_CNT__VALUE;
  851. tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
  852. iowrite32(tmp, denali->reg + CS_SETUP_CNT);
  853. return 0;
  854. }
  855. static void denali_reset_banks(struct denali_nand_info *denali)
  856. {
  857. u32 irq_status;
  858. int i;
  859. for (i = 0; i < denali->max_banks; i++) {
  860. denali->active_bank = i;
  861. denali_reset_irq(denali);
  862. iowrite32(DEVICE_RESET__BANK(i),
  863. denali->reg + DEVICE_RESET);
  864. irq_status = denali_wait_for_irq(denali,
  865. INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
  866. if (!(irq_status & INTR__INT_ACT))
  867. break;
  868. }
  869. dev_dbg(denali->dev, "%d chips connected\n", i);
  870. denali->max_banks = i;
  871. }
  872. static void denali_hw_init(struct denali_nand_info *denali)
  873. {
  874. /*
  875. * The REVISION register may not be reliable. Platforms are allowed to
  876. * override it.
  877. */
  878. if (!denali->revision)
  879. denali->revision = swab16(ioread32(denali->reg + REVISION));
  880. /*
  881. * tell driver how many bit controller will skip before writing
  882. * ECC code in OOB. This is normally used for bad block marker
  883. */
  884. denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES;
  885. iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES);
  886. denali_detect_max_banks(denali);
  887. iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
  888. iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
  889. iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
  890. }
  891. int denali_calc_ecc_bytes(int step_size, int strength)
  892. {
  893. /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
  894. return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
  895. }
  896. EXPORT_SYMBOL(denali_calc_ecc_bytes);
  897. static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
  898. struct denali_nand_info *denali)
  899. {
  900. int oobavail = mtd->oobsize - denali->oob_skip_bytes;
  901. int ret;
  902. /*
  903. * If .size and .strength are already set (usually by DT),
  904. * check if they are supported by this controller.
  905. */
  906. if (chip->ecc.size && chip->ecc.strength)
  907. return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
  908. /*
  909. * We want .size and .strength closest to the chip's requirement
  910. * unless NAND_ECC_MAXIMIZE is requested.
  911. */
  912. if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
  913. ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
  914. if (!ret)
  915. return 0;
  916. }
  917. /* Max ECC strength is the last thing we can do */
  918. return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
  919. }
  920. static struct nand_ecclayout nand_oob;
  921. static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
  922. struct mtd_oob_region *oobregion)
  923. {
  924. struct denali_nand_info *denali = mtd_to_denali(mtd);
  925. struct nand_chip *chip = mtd_to_nand(mtd);
  926. if (section)
  927. return -ERANGE;
  928. oobregion->offset = denali->oob_skip_bytes;
  929. oobregion->length = chip->ecc.total;
  930. return 0;
  931. }
  932. static int denali_ooblayout_free(struct mtd_info *mtd, int section,
  933. struct mtd_oob_region *oobregion)
  934. {
  935. struct denali_nand_info *denali = mtd_to_denali(mtd);
  936. struct nand_chip *chip = mtd_to_nand(mtd);
  937. if (section)
  938. return -ERANGE;
  939. oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
  940. oobregion->length = mtd->oobsize - oobregion->offset;
  941. return 0;
  942. }
  943. static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
  944. .ecc = denali_ooblayout_ecc,
  945. .free = denali_ooblayout_free,
  946. };
  947. static int denali_multidev_fixup(struct denali_nand_info *denali)
  948. {
  949. struct nand_chip *chip = &denali->nand;
  950. struct mtd_info *mtd = nand_to_mtd(chip);
  951. /*
  952. * Support for multi device:
  953. * When the IP configuration is x16 capable and two x8 chips are
  954. * connected in parallel, DEVICES_CONNECTED should be set to 2.
  955. * In this case, the core framework knows nothing about this fact,
  956. * so we should tell it the _logical_ pagesize and anything necessary.
  957. */
  958. denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
  959. /*
  960. * On some SoCs, DEVICES_CONNECTED is not auto-detected.
  961. * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
  962. */
  963. if (denali->devs_per_cs == 0) {
  964. denali->devs_per_cs = 1;
  965. iowrite32(1, denali->reg + DEVICES_CONNECTED);
  966. }
  967. if (denali->devs_per_cs == 1)
  968. return 0;
  969. if (denali->devs_per_cs != 2) {
  970. dev_err(denali->dev, "unsupported number of devices %d\n",
  971. denali->devs_per_cs);
  972. return -EINVAL;
  973. }
  974. /* 2 chips in parallel */
  975. mtd->size <<= 1;
  976. mtd->erasesize <<= 1;
  977. mtd->writesize <<= 1;
  978. mtd->oobsize <<= 1;
  979. chip->chipsize <<= 1;
  980. chip->page_shift += 1;
  981. chip->phys_erase_shift += 1;
  982. chip->bbt_erase_shift += 1;
  983. chip->chip_shift += 1;
  984. chip->pagemask <<= 1;
  985. chip->ecc.size <<= 1;
  986. chip->ecc.bytes <<= 1;
  987. chip->ecc.strength <<= 1;
  988. denali->oob_skip_bytes <<= 1;
  989. return 0;
  990. }
  991. int denali_init(struct denali_nand_info *denali)
  992. {
  993. struct nand_chip *chip = &denali->nand;
  994. struct mtd_info *mtd = nand_to_mtd(chip);
  995. u32 features = ioread32(denali->reg + FEATURES);
  996. int ret;
  997. denali_hw_init(denali);
  998. denali_clear_irq_all(denali);
  999. denali_reset_banks(denali);
  1000. denali->active_bank = DENALI_INVALID_BANK;
  1001. chip->flash_node = dev_of_offset(denali->dev);
  1002. /* Fallback to the default name if DT did not give "label" property */
  1003. if (!mtd->name)
  1004. mtd->name = "denali-nand";
  1005. chip->select_chip = denali_select_chip;
  1006. chip->read_byte = denali_read_byte;
  1007. chip->write_byte = denali_write_byte;
  1008. chip->read_word = denali_read_word;
  1009. chip->cmd_ctrl = denali_cmd_ctrl;
  1010. chip->dev_ready = denali_dev_ready;
  1011. chip->waitfunc = denali_waitfunc;
  1012. if (features & FEATURES__INDEX_ADDR) {
  1013. denali->host_read = denali_indexed_read;
  1014. denali->host_write = denali_indexed_write;
  1015. } else {
  1016. denali->host_read = denali_direct_read;
  1017. denali->host_write = denali_direct_write;
  1018. }
  1019. /* clk rate info is needed for setup_data_interface */
  1020. if (denali->clk_x_rate)
  1021. chip->setup_data_interface = denali_setup_data_interface;
  1022. ret = nand_scan_ident(mtd, denali->max_banks, NULL);
  1023. if (ret)
  1024. return ret;
  1025. if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
  1026. denali->dma_avail = 1;
  1027. if (denali->dma_avail) {
  1028. chip->buf_align = ARCH_DMA_MINALIGN;
  1029. if (denali->caps & DENALI_CAP_DMA_64BIT)
  1030. denali->setup_dma = denali_setup_dma64;
  1031. else
  1032. denali->setup_dma = denali_setup_dma32;
  1033. } else {
  1034. chip->buf_align = 4;
  1035. }
  1036. chip->options |= NAND_USE_BOUNCE_BUFFER;
  1037. chip->bbt_options |= NAND_BBT_USE_FLASH;
  1038. chip->bbt_options |= NAND_BBT_NO_OOB;
  1039. denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
  1040. /* no subpage writes on denali */
  1041. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1042. ret = denali_ecc_setup(mtd, chip, denali);
  1043. if (ret) {
  1044. dev_err(denali->dev, "Failed to setup ECC settings.\n");
  1045. return ret;
  1046. }
  1047. dev_dbg(denali->dev,
  1048. "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
  1049. chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
  1050. iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
  1051. FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
  1052. denali->reg + ECC_CORRECTION);
  1053. iowrite32(mtd->erasesize / mtd->writesize,
  1054. denali->reg + PAGES_PER_BLOCK);
  1055. iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
  1056. denali->reg + DEVICE_WIDTH);
  1057. iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
  1058. denali->reg + TWO_ROW_ADDR_CYCLES);
  1059. iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
  1060. iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
  1061. iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
  1062. iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
  1063. /* chip->ecc.steps is set by nand_scan_tail(); not available here */
  1064. iowrite32(mtd->writesize / chip->ecc.size,
  1065. denali->reg + CFG_NUM_DATA_BLOCKS);
  1066. mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
  1067. nand_oob.eccbytes = denali->nand.ecc.bytes;
  1068. denali->nand.ecc.layout = &nand_oob;
  1069. if (chip->options & NAND_BUSWIDTH_16) {
  1070. chip->read_buf = denali_read_buf16;
  1071. chip->write_buf = denali_write_buf16;
  1072. } else {
  1073. chip->read_buf = denali_read_buf;
  1074. chip->write_buf = denali_write_buf;
  1075. }
  1076. chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
  1077. chip->ecc.read_page = denali_read_page;
  1078. chip->ecc.read_page_raw = denali_read_page_raw;
  1079. chip->ecc.write_page = denali_write_page;
  1080. chip->ecc.write_page_raw = denali_write_page_raw;
  1081. chip->ecc.read_oob = denali_read_oob;
  1082. chip->ecc.write_oob = denali_write_oob;
  1083. chip->erase = denali_erase;
  1084. ret = denali_multidev_fixup(denali);
  1085. if (ret)
  1086. return ret;
  1087. /*
  1088. * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
  1089. * use devm_kmalloc() because the memory allocated by devm_ does not
  1090. * guarantee DMA-safe alignment.
  1091. */
  1092. denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
  1093. if (!denali->buf)
  1094. return -ENOMEM;
  1095. ret = nand_scan_tail(mtd);
  1096. if (ret)
  1097. goto free_buf;
  1098. ret = nand_register(0, mtd);
  1099. if (ret) {
  1100. dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
  1101. goto free_buf;
  1102. }
  1103. return 0;
  1104. free_buf:
  1105. kfree(denali->buf);
  1106. return ret;
  1107. }