davinci_nand.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NAND driver for TI DaVinci based boards.
  4. *
  5. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6. *
  7. * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
  8. */
  9. /*
  10. *
  11. * linux/drivers/mtd/nand/raw/nand_davinci.c
  12. *
  13. * NAND Flash Driver
  14. *
  15. * Copyright (C) 2006 Texas Instruments.
  16. *
  17. * ----------------------------------------------------------------------------
  18. *
  19. * ----------------------------------------------------------------------------
  20. *
  21. * Overview:
  22. * This is a device driver for the NAND flash device found on the
  23. * DaVinci board which utilizes the Samsung k9k2g08 part.
  24. *
  25. Modifications:
  26. ver. 1.0: Feb 2005, Vinod/Sudhakar
  27. -
  28. */
  29. #include <common.h>
  30. #include <asm/io.h>
  31. #include <nand.h>
  32. #include <asm/ti-common/davinci_nand.h>
  33. /* Definitions for 4-bit hardware ECC */
  34. #define NAND_TIMEOUT 10240
  35. #define NAND_ECC_BUSY 0xC
  36. #define NAND_4BITECC_MASK 0x03FF03FF
  37. #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
  38. #define ECC_STATE_NO_ERR 0x0
  39. #define ECC_STATE_TOO_MANY_ERRS 0x1
  40. #define ECC_STATE_ERR_CORR_COMP_P 0x2
  41. #define ECC_STATE_ERR_CORR_COMP_N 0x3
  42. /*
  43. * Exploit the little endianness of the ARM to do multi-byte transfers
  44. * per device read. This can perform over twice as quickly as individual
  45. * byte transfers when buffer alignment is conducive.
  46. *
  47. * NOTE: This only works if the NAND is not connected to the 2 LSBs of
  48. * the address bus. On Davinci EVM platforms this has always been true.
  49. */
  50. static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  51. {
  52. struct nand_chip *chip = mtd_to_nand(mtd);
  53. const u32 *nand = chip->IO_ADDR_R;
  54. /* Make sure that buf is 32 bit aligned */
  55. if (((int)buf & 0x3) != 0) {
  56. if (((int)buf & 0x1) != 0) {
  57. if (len) {
  58. *buf = readb(nand);
  59. buf += 1;
  60. len--;
  61. }
  62. }
  63. if (((int)buf & 0x3) != 0) {
  64. if (len >= 2) {
  65. *(u16 *)buf = readw(nand);
  66. buf += 2;
  67. len -= 2;
  68. }
  69. }
  70. }
  71. /* copy aligned data */
  72. while (len >= 4) {
  73. *(u32 *)buf = __raw_readl(nand);
  74. buf += 4;
  75. len -= 4;
  76. }
  77. /* mop up any remaining bytes */
  78. if (len) {
  79. if (len >= 2) {
  80. *(u16 *)buf = readw(nand);
  81. buf += 2;
  82. len -= 2;
  83. }
  84. if (len)
  85. *buf = readb(nand);
  86. }
  87. }
  88. static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  89. int len)
  90. {
  91. struct nand_chip *chip = mtd_to_nand(mtd);
  92. const u32 *nand = chip->IO_ADDR_W;
  93. /* Make sure that buf is 32 bit aligned */
  94. if (((int)buf & 0x3) != 0) {
  95. if (((int)buf & 0x1) != 0) {
  96. if (len) {
  97. writeb(*buf, nand);
  98. buf += 1;
  99. len--;
  100. }
  101. }
  102. if (((int)buf & 0x3) != 0) {
  103. if (len >= 2) {
  104. writew(*(u16 *)buf, nand);
  105. buf += 2;
  106. len -= 2;
  107. }
  108. }
  109. }
  110. /* copy aligned data */
  111. while (len >= 4) {
  112. __raw_writel(*(u32 *)buf, nand);
  113. buf += 4;
  114. len -= 4;
  115. }
  116. /* mop up any remaining bytes */
  117. if (len) {
  118. if (len >= 2) {
  119. writew(*(u16 *)buf, nand);
  120. buf += 2;
  121. len -= 2;
  122. }
  123. if (len)
  124. writeb(*buf, nand);
  125. }
  126. }
  127. static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
  128. unsigned int ctrl)
  129. {
  130. struct nand_chip *this = mtd_to_nand(mtd);
  131. u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
  132. if (ctrl & NAND_CTRL_CHANGE) {
  133. IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
  134. if (ctrl & NAND_CLE)
  135. IO_ADDR_W |= MASK_CLE;
  136. if (ctrl & NAND_ALE)
  137. IO_ADDR_W |= MASK_ALE;
  138. this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
  139. }
  140. if (cmd != NAND_CMD_NONE)
  141. writeb(cmd, IO_ADDR_W);
  142. }
  143. #ifdef CONFIG_SYS_NAND_HW_ECC
  144. static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
  145. {
  146. u_int32_t ecc = 0;
  147. ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
  148. CONFIG_SYS_NAND_CS - 2]));
  149. return ecc;
  150. }
  151. static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
  152. {
  153. u_int32_t val;
  154. /* reading the ECC result register resets the ECC calculation */
  155. nand_davinci_readecc(mtd);
  156. val = __raw_readl(&davinci_emif_regs->nandfcr);
  157. val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
  158. val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
  159. __raw_writel(val, &davinci_emif_regs->nandfcr);
  160. }
  161. static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  162. u_char *ecc_code)
  163. {
  164. u_int32_t tmp;
  165. tmp = nand_davinci_readecc(mtd);
  166. /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
  167. * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
  168. tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
  169. /* Invert so that erased block ECC is correct */
  170. tmp = ~tmp;
  171. *ecc_code++ = tmp;
  172. *ecc_code++ = tmp >> 8;
  173. *ecc_code++ = tmp >> 16;
  174. /* NOTE: the above code matches mainline Linux:
  175. * .PQR.stu ==> ~PQRstu
  176. *
  177. * MontaVista/TI kernels encode those bytes differently, use
  178. * complicated (and allegedly sometimes-wrong) correction code,
  179. * and usually shipped with U-Boot that uses software ECC:
  180. * .PQR.stu ==> PsQRtu
  181. *
  182. * If you need MV/TI compatible NAND I/O in U-Boot, it should
  183. * be possible to (a) change the mangling above, (b) reverse
  184. * that mangling in nand_davinci_correct_data() below.
  185. */
  186. return 0;
  187. }
  188. static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
  189. u_char *read_ecc, u_char *calc_ecc)
  190. {
  191. struct nand_chip *this = mtd_to_nand(mtd);
  192. u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
  193. (read_ecc[2] << 16);
  194. u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
  195. (calc_ecc[2] << 16);
  196. u_int32_t diff = ecc_calc ^ ecc_nand;
  197. if (diff) {
  198. if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
  199. /* Correctable error */
  200. if ((diff >> (12 + 3)) < this->ecc.size) {
  201. uint8_t find_bit = 1 << ((diff >> 12) & 7);
  202. uint32_t find_byte = diff >> (12 + 3);
  203. dat[find_byte] ^= find_bit;
  204. pr_debug("Correcting single "
  205. "bit ECC error at offset: %d, bit: "
  206. "%d\n", find_byte, find_bit);
  207. return 1;
  208. } else {
  209. return -EBADMSG;
  210. }
  211. } else if (!(diff & (diff - 1))) {
  212. /* Single bit ECC error in the ECC itself,
  213. nothing to fix */
  214. pr_debug("Single bit ECC error in " "ECC.\n");
  215. return 1;
  216. } else {
  217. /* Uncorrectable error */
  218. pr_debug("ECC UNCORRECTED_ERROR 1\n");
  219. return -EBADMSG;
  220. }
  221. }
  222. return 0;
  223. }
  224. #endif /* CONFIG_SYS_NAND_HW_ECC */
  225. #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  226. static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
  227. #if defined(CONFIG_SYS_NAND_PAGE_2K)
  228. .eccbytes = 40,
  229. #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
  230. .eccpos = {
  231. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  232. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  233. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  234. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  235. },
  236. .oobfree = {
  237. {2, 4}, {16, 6}, {32, 6}, {48, 6},
  238. },
  239. #else
  240. .eccpos = {
  241. 24, 25, 26, 27, 28,
  242. 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
  243. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
  244. 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
  245. 59, 60, 61, 62, 63,
  246. },
  247. .oobfree = {
  248. {.offset = 2, .length = 22, },
  249. },
  250. #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
  251. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  252. .eccbytes = 80,
  253. .eccpos = {
  254. 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
  255. 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
  256. 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
  257. 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
  258. 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
  259. 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
  260. 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
  261. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  262. },
  263. .oobfree = {
  264. {.offset = 2, .length = 46, },
  265. },
  266. #endif
  267. };
  268. #if defined CONFIG_KEYSTONE_RBL_NAND
  269. static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
  270. #if defined(CONFIG_SYS_NAND_PAGE_2K)
  271. .eccbytes = 40,
  272. .eccpos = {
  273. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  274. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  275. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  276. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  277. },
  278. .oobfree = {
  279. {.offset = 2, .length = 4, },
  280. {.offset = 16, .length = 6, },
  281. {.offset = 32, .length = 6, },
  282. {.offset = 48, .length = 6, },
  283. },
  284. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  285. .eccbytes = 80,
  286. .eccpos = {
  287. 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  288. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
  289. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
  290. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  291. 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
  292. 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
  293. 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
  294. 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
  295. },
  296. .oobfree = {
  297. {.offset = 2, .length = 4, },
  298. {.offset = 16, .length = 6, },
  299. {.offset = 32, .length = 6, },
  300. {.offset = 48, .length = 6, },
  301. {.offset = 64, .length = 6, },
  302. {.offset = 80, .length = 6, },
  303. {.offset = 96, .length = 6, },
  304. {.offset = 112, .length = 6, },
  305. },
  306. #endif
  307. };
  308. #ifdef CONFIG_SYS_NAND_PAGE_2K
  309. #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
  310. #elif defined(CONFIG_SYS_NAND_PAGE_4K)
  311. #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
  312. #endif
  313. /**
  314. * nand_davinci_write_page - write one page
  315. * @mtd: MTD device structure
  316. * @chip: NAND chip descriptor
  317. * @buf: the data to write
  318. * @oob_required: must write chip->oob_poi to OOB
  319. * @page: page number to write
  320. * @raw: use _raw version of write_page
  321. */
  322. static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  323. uint32_t offset, int data_len,
  324. const uint8_t *buf, int oob_required,
  325. int page, int raw)
  326. {
  327. int status;
  328. int ret = 0;
  329. struct nand_ecclayout *saved_ecc_layout;
  330. /* save current ECC layout and assign Keystone RBL ECC layout */
  331. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  332. saved_ecc_layout = chip->ecc.layout;
  333. chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  334. mtd->oobavail = chip->ecc.layout->oobavail;
  335. }
  336. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
  337. if (unlikely(raw)) {
  338. status = chip->ecc.write_page_raw(mtd, chip, buf,
  339. oob_required, page);
  340. } else {
  341. status = chip->ecc.write_page(mtd, chip, buf,
  342. oob_required, page);
  343. }
  344. if (status < 0) {
  345. ret = status;
  346. goto err;
  347. }
  348. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  349. status = chip->waitfunc(mtd, chip);
  350. if (status & NAND_STATUS_FAIL) {
  351. ret = -EIO;
  352. goto err;
  353. }
  354. err:
  355. /* restore ECC layout */
  356. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  357. chip->ecc.layout = saved_ecc_layout;
  358. mtd->oobavail = saved_ecc_layout->oobavail;
  359. }
  360. return ret;
  361. }
  362. /**
  363. * nand_davinci_read_page_hwecc - hardware ECC based page read function
  364. * @mtd: mtd info structure
  365. * @chip: nand chip info structure
  366. * @buf: buffer to store read data
  367. * @oob_required: caller requires OOB data read to chip->oob_poi
  368. * @page: page number to read
  369. *
  370. * Not for syndrome calculating ECC controllers which need a special oob layout.
  371. */
  372. static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  373. uint8_t *buf, int oob_required, int page)
  374. {
  375. int i, eccsize = chip->ecc.size;
  376. int eccbytes = chip->ecc.bytes;
  377. int eccsteps = chip->ecc.steps;
  378. uint32_t *eccpos;
  379. uint8_t *p = buf;
  380. uint8_t *ecc_code = chip->buffers->ecccode;
  381. uint8_t *ecc_calc = chip->buffers->ecccalc;
  382. struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
  383. /* save current ECC layout and assign Keystone RBL ECC layout */
  384. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  385. chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  386. mtd->oobavail = chip->ecc.layout->oobavail;
  387. }
  388. eccpos = chip->ecc.layout->eccpos;
  389. /* Read the OOB area first */
  390. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  391. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  392. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  393. for (i = 0; i < chip->ecc.total; i++)
  394. ecc_code[i] = chip->oob_poi[eccpos[i]];
  395. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  396. int stat;
  397. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  398. chip->read_buf(mtd, p, eccsize);
  399. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  400. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  401. if (stat < 0)
  402. mtd->ecc_stats.failed++;
  403. else
  404. mtd->ecc_stats.corrected += stat;
  405. }
  406. /* restore ECC layout */
  407. if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
  408. chip->ecc.layout = saved_ecc_layout;
  409. mtd->oobavail = saved_ecc_layout->oobavail;
  410. }
  411. return 0;
  412. }
  413. #endif /* CONFIG_KEYSTONE_RBL_NAND */
  414. static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
  415. {
  416. u32 val;
  417. switch (mode) {
  418. case NAND_ECC_WRITE:
  419. case NAND_ECC_READ:
  420. /*
  421. * Start a new ECC calculation for reading or writing 512 bytes
  422. * of data.
  423. */
  424. val = __raw_readl(&davinci_emif_regs->nandfcr);
  425. val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
  426. val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
  427. val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
  428. val |= DAVINCI_NANDFCR_4BIT_ECC_START;
  429. __raw_writel(val, &davinci_emif_regs->nandfcr);
  430. break;
  431. case NAND_ECC_READSYN:
  432. val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
  433. break;
  434. default:
  435. break;
  436. }
  437. }
  438. static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
  439. {
  440. int i;
  441. for (i = 0; i < 4; i++) {
  442. ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
  443. NAND_4BITECC_MASK;
  444. }
  445. return 0;
  446. }
  447. static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
  448. const uint8_t *dat,
  449. uint8_t *ecc_code)
  450. {
  451. unsigned int hw_4ecc[4];
  452. unsigned int i;
  453. nand_davinci_4bit_readecc(mtd, hw_4ecc);
  454. /*Convert 10 bit ecc value to 8 bit */
  455. for (i = 0; i < 2; i++) {
  456. unsigned int hw_ecc_low = hw_4ecc[i * 2];
  457. unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
  458. /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
  459. *ecc_code++ = hw_ecc_low & 0xFF;
  460. /*
  461. * Take 2 bits as LSB bits from val1 (count1=0) or val5
  462. * (count1=1) and 6 bits from val2 (count1=0) or
  463. * val5 (count1=1)
  464. */
  465. *ecc_code++ =
  466. ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
  467. /*
  468. * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
  469. * 4 bits from val3 (count1=0) or val6 (count1=1)
  470. */
  471. *ecc_code++ =
  472. ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
  473. /*
  474. * Take 6 bits from val3(count1=0) or val6 (count1=1) and
  475. * 2 bits from val4 (count1=0) or val7 (count1=1)
  476. */
  477. *ecc_code++ =
  478. ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
  479. /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
  480. *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
  481. }
  482. return 0;
  483. }
  484. static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
  485. uint8_t *read_ecc, uint8_t *calc_ecc)
  486. {
  487. int i;
  488. unsigned int hw_4ecc[4];
  489. unsigned int iserror;
  490. unsigned short *ecc16;
  491. unsigned int numerrors, erroraddress, errorvalue;
  492. u32 val;
  493. /*
  494. * Check for an ECC where all bytes are 0xFF. If this is the case, we
  495. * will assume we are looking at an erased page and we should ignore
  496. * the ECC.
  497. */
  498. for (i = 0; i < 10; i++) {
  499. if (read_ecc[i] != 0xFF)
  500. break;
  501. }
  502. if (i == 10)
  503. return 0;
  504. /* Convert 8 bit in to 10 bit */
  505. ecc16 = (unsigned short *)&read_ecc[0];
  506. /*
  507. * Write the parity values in the NAND Flash 4-bit ECC Load register.
  508. * Write each parity value one at a time starting from 4bit_ecc_val8
  509. * to 4bit_ecc_val1.
  510. */
  511. /*Take 2 bits from 8th byte and 8 bits from 9th byte */
  512. __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
  513. &davinci_emif_regs->nand4biteccload);
  514. /* Take 4 bits from 7th byte and 6 bits from 8th byte */
  515. __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
  516. &davinci_emif_regs->nand4biteccload);
  517. /* Take 6 bits from 6th byte and 4 bits from 7th byte */
  518. __raw_writel((ecc16[3] >> 2) & 0x3FF,
  519. &davinci_emif_regs->nand4biteccload);
  520. /* Take 8 bits from 5th byte and 2 bits from 6th byte */
  521. __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
  522. &davinci_emif_regs->nand4biteccload);
  523. /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
  524. __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
  525. &davinci_emif_regs->nand4biteccload);
  526. /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
  527. __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
  528. &davinci_emif_regs->nand4biteccload);
  529. /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
  530. __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
  531. &davinci_emif_regs->nand4biteccload);
  532. /* Take 10 bits from 0th and 1st bytes */
  533. __raw_writel((ecc16[0]) & 0x3FF,
  534. &davinci_emif_regs->nand4biteccload);
  535. /*
  536. * Perform a dummy read to the EMIF Revision Code and Status register.
  537. * This is required to ensure time for syndrome calculation after
  538. * writing the ECC values in previous step.
  539. */
  540. val = __raw_readl(&davinci_emif_regs->nandfsr);
  541. /*
  542. * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
  543. * A syndrome value of 0 means no bit errors. If the syndrome is
  544. * non-zero then go further otherwise return.
  545. */
  546. nand_davinci_4bit_readecc(mtd, hw_4ecc);
  547. if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
  548. return 0;
  549. /*
  550. * Clear any previous address calculation by doing a dummy read of an
  551. * error address register.
  552. */
  553. val = __raw_readl(&davinci_emif_regs->nanderradd1);
  554. /*
  555. * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
  556. * register to 1.
  557. */
  558. __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
  559. &davinci_emif_regs->nandfcr);
  560. /*
  561. * Wait for the corr_state field (bits 8 to 11) in the
  562. * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
  563. * Otherwise ECC calculation has not even begun and the next loop might
  564. * fail because of a false positive!
  565. */
  566. i = NAND_TIMEOUT;
  567. do {
  568. val = __raw_readl(&davinci_emif_regs->nandfsr);
  569. val &= 0xc00;
  570. i--;
  571. } while ((i > 0) && !val);
  572. /*
  573. * Wait for the corr_state field (bits 8 to 11) in the
  574. * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
  575. */
  576. i = NAND_TIMEOUT;
  577. do {
  578. val = __raw_readl(&davinci_emif_regs->nandfsr);
  579. val &= 0xc00;
  580. i--;
  581. } while ((i > 0) && val);
  582. iserror = __raw_readl(&davinci_emif_regs->nandfsr);
  583. iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
  584. iserror = iserror >> 8;
  585. /*
  586. * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
  587. * corrected (five or more errors). The number of errors
  588. * calculated (err_num field) differs from the number of errors
  589. * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
  590. * correction complete (errors on bit 8 or 9).
  591. * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
  592. * complete (error exists).
  593. */
  594. if (iserror == ECC_STATE_NO_ERR) {
  595. val = __raw_readl(&davinci_emif_regs->nanderrval1);
  596. return 0;
  597. } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
  598. val = __raw_readl(&davinci_emif_regs->nanderrval1);
  599. return -EBADMSG;
  600. }
  601. numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
  602. & 0x3) + 1;
  603. /* Read the error address, error value and correct */
  604. for (i = 0; i < numerrors; i++) {
  605. if (i > 1) {
  606. erroraddress =
  607. ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
  608. (16 * (i & 1))) & 0x3FF);
  609. erroraddress = ((512 + 7) - erroraddress);
  610. errorvalue =
  611. ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
  612. (16 * (i & 1))) & 0xFF);
  613. } else {
  614. erroraddress =
  615. ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
  616. (16 * (i & 1))) & 0x3FF);
  617. erroraddress = ((512 + 7) - erroraddress);
  618. errorvalue =
  619. ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
  620. (16 * (i & 1))) & 0xFF);
  621. }
  622. /* xor the corrupt data with error value */
  623. if (erroraddress < 512)
  624. dat[erroraddress] ^= errorvalue;
  625. }
  626. return numerrors;
  627. }
  628. #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
  629. static int nand_davinci_dev_ready(struct mtd_info *mtd)
  630. {
  631. return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
  632. }
  633. static void nand_flash_init(void)
  634. {
  635. /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
  636. * Instead, have your board_init() set EMIF timings, based on its
  637. * knowledge of the clocks and what devices are hooked up ... and
  638. * don't even do that unless no UBL handled it.
  639. */
  640. #ifdef CONFIG_SOC_DM644X
  641. u_int32_t acfg1 = 0x3ffffffc;
  642. /*------------------------------------------------------------------*
  643. * NAND FLASH CHIP TIMEOUT @ 459 MHz *
  644. * *
  645. * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
  646. * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
  647. * *
  648. *------------------------------------------------------------------*/
  649. acfg1 = 0
  650. | (0 << 31) /* selectStrobe */
  651. | (0 << 30) /* extWait */
  652. | (1 << 26) /* writeSetup 10 ns */
  653. | (3 << 20) /* writeStrobe 40 ns */
  654. | (1 << 17) /* writeHold 10 ns */
  655. | (1 << 13) /* readSetup 10 ns */
  656. | (5 << 7) /* readStrobe 60 ns */
  657. | (1 << 4) /* readHold 10 ns */
  658. | (3 << 2) /* turnAround ?? ns */
  659. | (0 << 0) /* asyncSize 8-bit bus */
  660. ;
  661. __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
  662. /* NAND flash on CS2 */
  663. __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
  664. #endif
  665. }
  666. void davinci_nand_init(struct nand_chip *nand)
  667. {
  668. #if defined CONFIG_KEYSTONE_RBL_NAND
  669. int i;
  670. struct nand_ecclayout *layout;
  671. layout = &nand_keystone_rbl_4bit_layout_oobfirst;
  672. layout->oobavail = 0;
  673. for (i = 0; layout->oobfree[i].length &&
  674. i < ARRAY_SIZE(layout->oobfree); i++)
  675. layout->oobavail += layout->oobfree[i].length;
  676. nand->write_page = nand_davinci_write_page;
  677. nand->ecc.read_page = nand_davinci_read_page_hwecc;
  678. #endif
  679. nand->chip_delay = 0;
  680. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  681. nand->bbt_options |= NAND_BBT_USE_FLASH;
  682. #endif
  683. #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
  684. nand->options |= NAND_NO_SUBPAGE_WRITE;
  685. #endif
  686. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  687. nand->options |= NAND_BUSWIDTH_16;
  688. #endif
  689. #ifdef CONFIG_SYS_NAND_HW_ECC
  690. nand->ecc.mode = NAND_ECC_HW;
  691. nand->ecc.size = 512;
  692. nand->ecc.bytes = 3;
  693. nand->ecc.strength = 1;
  694. nand->ecc.calculate = nand_davinci_calculate_ecc;
  695. nand->ecc.correct = nand_davinci_correct_data;
  696. nand->ecc.hwctl = nand_davinci_enable_hwecc;
  697. #else
  698. nand->ecc.mode = NAND_ECC_SOFT;
  699. #endif /* CONFIG_SYS_NAND_HW_ECC */
  700. #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
  701. nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
  702. nand->ecc.size = 512;
  703. nand->ecc.bytes = 10;
  704. nand->ecc.strength = 4;
  705. nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
  706. nand->ecc.correct = nand_davinci_4bit_correct_data;
  707. nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
  708. nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
  709. #endif
  710. /* Set address of hardware control function */
  711. nand->cmd_ctrl = nand_davinci_hwcontrol;
  712. nand->read_buf = nand_davinci_read_buf;
  713. nand->write_buf = nand_davinci_write_buf;
  714. nand->dev_ready = nand_davinci_dev_ready;
  715. nand_flash_init();
  716. }
  717. int board_nand_init(struct nand_chip *chip) __attribute__((weak));
  718. int board_nand_init(struct nand_chip *chip)
  719. {
  720. davinci_nand_init(chip);
  721. return 0;
  722. }