atmel_nand_ecc.h 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Error Corrected Code Controller (ECC) - System peripherals regsters.
  4. * Based on AT91SAM9260 datasheet revision B.
  5. */
  6. #ifndef ATMEL_NAND_ECC_H
  7. #define ATMEL_NAND_ECC_H
  8. #define ATMEL_ECC_CR 0x00 /* Control register */
  9. #define ATMEL_ECC_RST (1 << 0) /* Reset parity */
  10. #define ATMEL_ECC_MR 0x04 /* Mode register */
  11. #define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
  12. #define ATMEL_ECC_PAGESIZE_528 (0)
  13. #define ATMEL_ECC_PAGESIZE_1056 (1)
  14. #define ATMEL_ECC_PAGESIZE_2112 (2)
  15. #define ATMEL_ECC_PAGESIZE_4224 (3)
  16. #define ATMEL_ECC_SR 0x08 /* Status register */
  17. #define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
  18. #define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
  19. #define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
  20. #define ATMEL_ECC_PR 0x0c /* Parity register */
  21. #define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
  22. #define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
  23. #define ATMEL_ECC_NPR 0x10 /* NParity register */
  24. #define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
  25. /* Register access macros for PMECC */
  26. #define pmecc_readl(addr, reg) \
  27. readl(&addr->reg)
  28. #define pmecc_readb(addr, reg) \
  29. readb(&addr->reg)
  30. #define pmecc_writel(addr, reg, value) \
  31. writel((value), &addr->reg)
  32. /* PMECC Register Definitions */
  33. #define PMECC_MAX_SECTOR_NUM 8
  34. struct pmecc_regs {
  35. u32 cfg; /* 0x00 PMECC Configuration Register */
  36. u32 sarea; /* 0x04 PMECC Spare Area Size Register */
  37. u32 saddr; /* 0x08 PMECC Start Address Register */
  38. u32 eaddr; /* 0x0C PMECC End Address Register */
  39. u32 clk; /* 0x10 PMECC Clock Control Register */
  40. u32 ctrl; /* 0x14 PMECC Control Register */
  41. u32 sr; /* 0x18 PMECC Status Register */
  42. u32 ier; /* 0x1C PMECC Interrupt Enable Register */
  43. u32 idr; /* 0x20 PMECC Interrupt Disable Register */
  44. u32 imr; /* 0x24 PMECC Interrupt Mask Register */
  45. u32 isr; /* 0x28 PMECC Interrupt Status Register */
  46. u32 reserved0[5]; /* 0x2C-0x3C Reserved */
  47. /* 0x40 + sector_num * (0x40), Redundancy Registers */
  48. struct {
  49. #ifdef CONFIG_SAMA5D2
  50. u8 ecc[56]; /* PMECC Generated Redundancy Byte Per Sector */
  51. u32 reserved1[2];
  52. #else
  53. u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */
  54. u32 reserved1[5];
  55. #endif
  56. } ecc_port[PMECC_MAX_SECTOR_NUM];
  57. /* 0x240 + sector_num * (0x40) Remainder Registers */
  58. struct {
  59. #ifdef CONFIG_SAMA5D2
  60. u32 rem[16];
  61. #else
  62. u32 rem[12];
  63. u32 reserved2[4];
  64. #endif
  65. } rem_port[PMECC_MAX_SECTOR_NUM];
  66. u32 reserved3[16]; /* 0x440-0x47C Reserved */
  67. };
  68. /* For PMECC Configuration Register */
  69. #define PMECC_CFG_BCH_ERR2 (0 << 0)
  70. #define PMECC_CFG_BCH_ERR4 (1 << 0)
  71. #define PMECC_CFG_BCH_ERR8 (2 << 0)
  72. #define PMECC_CFG_BCH_ERR12 (3 << 0)
  73. #define PMECC_CFG_BCH_ERR24 (4 << 0)
  74. #define PMECC_CFG_BCH_ERR32 (5 << 0)
  75. #define PMECC_CFG_SECTOR512 (0 << 4)
  76. #define PMECC_CFG_SECTOR1024 (1 << 4)
  77. #define PMECC_CFG_PAGE_1SECTOR (0 << 8)
  78. #define PMECC_CFG_PAGE_2SECTORS (1 << 8)
  79. #define PMECC_CFG_PAGE_4SECTORS (2 << 8)
  80. #define PMECC_CFG_PAGE_8SECTORS (3 << 8)
  81. #define PMECC_CFG_READ_OP (0 << 12)
  82. #define PMECC_CFG_WRITE_OP (1 << 12)
  83. #define PMECC_CFG_SPARE_ENABLE (1 << 16)
  84. #define PMECC_CFG_SPARE_DISABLE (0 << 16)
  85. #define PMECC_CFG_AUTO_ENABLE (1 << 20)
  86. #define PMECC_CFG_AUTO_DISABLE (0 << 20)
  87. /* For PMECC Clock Control Register */
  88. #define PMECC_CLK_133MHZ (2 << 0)
  89. /* For PMECC Control Register */
  90. #define PMECC_CTRL_RST (1 << 0)
  91. #define PMECC_CTRL_DATA (1 << 1)
  92. #define PMECC_CTRL_USER (1 << 2)
  93. #define PMECC_CTRL_ENABLE (1 << 4)
  94. #define PMECC_CTRL_DISABLE (1 << 5)
  95. /* For PMECC Status Register */
  96. #define PMECC_SR_BUSY (1 << 0)
  97. #define PMECC_SR_ENABLE (1 << 4)
  98. /* PMERRLOC Register Definitions */
  99. struct pmecc_errloc_regs {
  100. u32 elcfg; /* 0x00 Error Location Configuration Register */
  101. u32 elprim; /* 0x04 Error Location Primitive Register */
  102. u32 elen; /* 0x08 Error Location Enable Register */
  103. u32 eldis; /* 0x0C Error Location Disable Register */
  104. u32 elsr; /* 0x10 Error Location Status Register */
  105. u32 elier; /* 0x14 Error Location Interrupt Enable Register */
  106. u32 elidr; /* 0x08 Error Location Interrupt Disable Register */
  107. u32 elimr; /* 0x0C Error Location Interrupt Mask Register */
  108. u32 elisr; /* 0x20 Error Location Interrupt Status Register */
  109. u32 reserved0; /* 0x24 Reserved */
  110. #ifdef CONFIG_SAMA5D2
  111. u32 sigma[33]; /* 0x28-0xA8 Error Location Sigma Registers */
  112. u32 el[32]; /* 0xAC-0x128 Error Location Registers */
  113. /*
  114. * 0x12C-0x1FC:
  115. * Reserved for SAMA5D2.
  116. */
  117. u32 reserved1[53];
  118. #else
  119. u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */
  120. u32 el[24]; /* 0x8C-0xE8 Error Location Registers */
  121. u32 reserved1[5]; /* 0xEC-0xFC Reserved */
  122. #endif
  123. /*
  124. * SAMA5 chip HSMC registers start here. But for 9X5 chip it is just
  125. * reserved.
  126. *
  127. * Offset 0x00-0xF8:
  128. */
  129. u32 reserved2[63];
  130. /*
  131. * Offset 0xFC:
  132. * PMECC version for AT91SAM9X5, AT91SAM9N12.
  133. * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version.
  134. */
  135. u32 version;
  136. };
  137. /* For Error Location Configuration Register */
  138. #define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
  139. #define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
  140. #define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
  141. /* For Error Location Disable Register */
  142. #define PMERRLOC_DISABLE (1 << 0)
  143. /* For Error Location Interrupt Status Register */
  144. #ifdef CONFIG_SAMA5D2
  145. #define PMERRLOC_ERR_NUM_MASK (0x3f << 8)
  146. #else
  147. #define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
  148. #endif
  149. #define PMERRLOC_CALC_DONE (1 << 0)
  150. /* PMECC IP version */
  151. #define PMECC_VERSION_SAMA5D2 0x210
  152. #define PMECC_VERSION_SAMA5D4 0x113
  153. #define PMECC_VERSION_SAMA5D3 0x112
  154. #define PMECC_VERSION_AT91SAM9N12 0x102
  155. #define PMECC_VERSION_AT91SAM9X5 0x101
  156. /* Galois field dimension */
  157. #define PMECC_GF_DIMENSION_13 13
  158. #define PMECC_GF_DIMENSION_14 14
  159. /* Primitive Polynomial used by PMECC */
  160. #define PMECC_GF_13_PRIMITIVE_POLY 0x201b
  161. #define PMECC_GF_14_PRIMITIVE_POLY 0x4443
  162. #define PMECC_INDEX_TABLE_SIZE_512 0x2000
  163. #define PMECC_INDEX_TABLE_SIZE_1024 0x4000
  164. #define PMECC_MAX_TIMEOUT_US (100 * 1000)
  165. /* Reserved bytes in oob area */
  166. #define PMECC_OOB_RESERVED_BYTES 2
  167. #endif