atmel_nand.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  8. *
  9. * Add Programmable Multibit ECC support for various AT91 SoC
  10. * (C) Copyright 2012 ATMEL, Hong Xu
  11. */
  12. #include <common.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/gpio.h>
  15. #include <malloc.h>
  16. #include <nand.h>
  17. #include <watchdog.h>
  18. #include <linux/mtd/nand_ecc.h>
  19. #ifdef CONFIG_ATMEL_NAND_HWECC
  20. /* Register access macros */
  21. #define ecc_readl(add, reg) \
  22. readl(add + ATMEL_ECC_##reg)
  23. #define ecc_writel(add, reg, value) \
  24. writel((value), add + ATMEL_ECC_##reg)
  25. #include "atmel_nand_ecc.h" /* Hardware ECC registers */
  26. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  27. #ifdef CONFIG_SPL_BUILD
  28. #undef CONFIG_SYS_NAND_ONFI_DETECTION
  29. #endif
  30. struct atmel_nand_host {
  31. struct pmecc_regs __iomem *pmecc;
  32. struct pmecc_errloc_regs __iomem *pmerrloc;
  33. void __iomem *pmecc_rom_base;
  34. u8 pmecc_corr_cap;
  35. u16 pmecc_sector_size;
  36. u32 pmecc_index_table_offset;
  37. u32 pmecc_version;
  38. int pmecc_bytes_per_sector;
  39. int pmecc_sector_number;
  40. int pmecc_degree; /* Degree of remainders */
  41. int pmecc_cw_len; /* Length of codeword */
  42. /* lookup table for alpha_to and index_of */
  43. void __iomem *pmecc_alpha_to;
  44. void __iomem *pmecc_index_of;
  45. /* data for pmecc computation */
  46. int16_t *pmecc_smu;
  47. int16_t *pmecc_partial_syn;
  48. int16_t *pmecc_si;
  49. int16_t *pmecc_lmu; /* polynomal order */
  50. int *pmecc_mu;
  51. int *pmecc_dmu;
  52. int *pmecc_delta;
  53. };
  54. static struct atmel_nand_host pmecc_host;
  55. static struct nand_ecclayout atmel_pmecc_oobinfo;
  56. /*
  57. * Return number of ecc bytes per sector according to sector size and
  58. * correction capability
  59. *
  60. * Following table shows what at91 PMECC supported:
  61. * Correction Capability Sector_512_bytes Sector_1024_bytes
  62. * ===================== ================ =================
  63. * 2-bits 4-bytes 4-bytes
  64. * 4-bits 7-bytes 7-bytes
  65. * 8-bits 13-bytes 14-bytes
  66. * 12-bits 20-bytes 21-bytes
  67. * 24-bits 39-bytes 42-bytes
  68. * 32-bits 52-bytes 56-bytes
  69. */
  70. static int pmecc_get_ecc_bytes(int cap, int sector_size)
  71. {
  72. int m = 12 + sector_size / 512;
  73. return (m * cap + 7) / 8;
  74. }
  75. static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  76. int oobsize, int ecc_len)
  77. {
  78. int i;
  79. layout->eccbytes = ecc_len;
  80. /* ECC will occupy the last ecc_len bytes continuously */
  81. for (i = 0; i < ecc_len; i++)
  82. layout->eccpos[i] = oobsize - ecc_len + i;
  83. layout->oobfree[0].offset = 2;
  84. layout->oobfree[0].length =
  85. oobsize - ecc_len - layout->oobfree[0].offset;
  86. }
  87. static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
  88. {
  89. int table_size;
  90. table_size = host->pmecc_sector_size == 512 ?
  91. PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
  92. /* the ALPHA lookup table is right behind the INDEX lookup table. */
  93. return host->pmecc_rom_base + host->pmecc_index_table_offset +
  94. table_size * sizeof(int16_t);
  95. }
  96. static void pmecc_data_free(struct atmel_nand_host *host)
  97. {
  98. free(host->pmecc_partial_syn);
  99. free(host->pmecc_si);
  100. free(host->pmecc_lmu);
  101. free(host->pmecc_smu);
  102. free(host->pmecc_mu);
  103. free(host->pmecc_dmu);
  104. free(host->pmecc_delta);
  105. }
  106. static int pmecc_data_alloc(struct atmel_nand_host *host)
  107. {
  108. const int cap = host->pmecc_corr_cap;
  109. int size;
  110. size = (2 * cap + 1) * sizeof(int16_t);
  111. host->pmecc_partial_syn = malloc(size);
  112. host->pmecc_si = malloc(size);
  113. host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
  114. host->pmecc_smu = malloc((cap + 2) * size);
  115. size = (cap + 1) * sizeof(int);
  116. host->pmecc_mu = malloc(size);
  117. host->pmecc_dmu = malloc(size);
  118. host->pmecc_delta = malloc(size);
  119. if (host->pmecc_partial_syn &&
  120. host->pmecc_si &&
  121. host->pmecc_lmu &&
  122. host->pmecc_smu &&
  123. host->pmecc_mu &&
  124. host->pmecc_dmu &&
  125. host->pmecc_delta)
  126. return 0;
  127. /* error happened */
  128. pmecc_data_free(host);
  129. return -ENOMEM;
  130. }
  131. static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
  132. {
  133. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  134. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  135. int i;
  136. uint32_t value;
  137. /* Fill odd syndromes */
  138. for (i = 0; i < host->pmecc_corr_cap; i++) {
  139. value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
  140. if (i & 1)
  141. value >>= 16;
  142. value &= 0xffff;
  143. host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
  144. }
  145. }
  146. static void pmecc_substitute(struct mtd_info *mtd)
  147. {
  148. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  149. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  150. int16_t __iomem *alpha_to = host->pmecc_alpha_to;
  151. int16_t __iomem *index_of = host->pmecc_index_of;
  152. int16_t *partial_syn = host->pmecc_partial_syn;
  153. const int cap = host->pmecc_corr_cap;
  154. int16_t *si;
  155. int i, j;
  156. /* si[] is a table that holds the current syndrome value,
  157. * an element of that table belongs to the field
  158. */
  159. si = host->pmecc_si;
  160. memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
  161. /* Computation 2t syndromes based on S(x) */
  162. /* Odd syndromes */
  163. for (i = 1; i < 2 * cap; i += 2) {
  164. for (j = 0; j < host->pmecc_degree; j++) {
  165. if (partial_syn[i] & (0x1 << j))
  166. si[i] = readw(alpha_to + i * j) ^ si[i];
  167. }
  168. }
  169. /* Even syndrome = (Odd syndrome) ** 2 */
  170. for (i = 2, j = 1; j <= cap; i = ++j << 1) {
  171. if (si[j] == 0) {
  172. si[i] = 0;
  173. } else {
  174. int16_t tmp;
  175. tmp = readw(index_of + si[j]);
  176. tmp = (tmp * 2) % host->pmecc_cw_len;
  177. si[i] = readw(alpha_to + tmp);
  178. }
  179. }
  180. }
  181. /*
  182. * This function defines a Berlekamp iterative procedure for
  183. * finding the value of the error location polynomial.
  184. * The input is si[], initialize by pmecc_substitute().
  185. * The output is smu[][].
  186. *
  187. * This function is written according to chip datasheet Chapter:
  188. * Find the Error Location Polynomial Sigma(x) of Section:
  189. * Programmable Multibit ECC Control (PMECC).
  190. */
  191. static void pmecc_get_sigma(struct mtd_info *mtd)
  192. {
  193. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  194. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  195. int16_t *lmu = host->pmecc_lmu;
  196. int16_t *si = host->pmecc_si;
  197. int *mu = host->pmecc_mu;
  198. int *dmu = host->pmecc_dmu; /* Discrepancy */
  199. int *delta = host->pmecc_delta; /* Delta order */
  200. int cw_len = host->pmecc_cw_len;
  201. const int16_t cap = host->pmecc_corr_cap;
  202. const int num = 2 * cap + 1;
  203. int16_t __iomem *index_of = host->pmecc_index_of;
  204. int16_t __iomem *alpha_to = host->pmecc_alpha_to;
  205. int i, j, k;
  206. uint32_t dmu_0_count, tmp;
  207. int16_t *smu = host->pmecc_smu;
  208. /* index of largest delta */
  209. int ro;
  210. int largest;
  211. int diff;
  212. /* Init the Sigma(x) */
  213. memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
  214. dmu_0_count = 0;
  215. /* First Row */
  216. /* Mu */
  217. mu[0] = -1;
  218. smu[0] = 1;
  219. /* discrepancy set to 1 */
  220. dmu[0] = 1;
  221. /* polynom order set to 0 */
  222. lmu[0] = 0;
  223. /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
  224. delta[0] = -1;
  225. /* Second Row */
  226. /* Mu */
  227. mu[1] = 0;
  228. /* Sigma(x) set to 1 */
  229. smu[num] = 1;
  230. /* discrepancy set to S1 */
  231. dmu[1] = si[1];
  232. /* polynom order set to 0 */
  233. lmu[1] = 0;
  234. /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
  235. delta[1] = 0;
  236. for (i = 1; i <= cap; i++) {
  237. mu[i + 1] = i << 1;
  238. /* Begin Computing Sigma (Mu+1) and L(mu) */
  239. /* check if discrepancy is set to 0 */
  240. if (dmu[i] == 0) {
  241. dmu_0_count++;
  242. tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
  243. if ((cap - (lmu[i] >> 1) - 1) & 0x1)
  244. tmp += 2;
  245. else
  246. tmp += 1;
  247. if (dmu_0_count == tmp) {
  248. for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
  249. smu[(cap + 1) * num + j] =
  250. smu[i * num + j];
  251. lmu[cap + 1] = lmu[i];
  252. return;
  253. }
  254. /* copy polynom */
  255. for (j = 0; j <= lmu[i] >> 1; j++)
  256. smu[(i + 1) * num + j] = smu[i * num + j];
  257. /* copy previous polynom order to the next */
  258. lmu[i + 1] = lmu[i];
  259. } else {
  260. ro = 0;
  261. largest = -1;
  262. /* find largest delta with dmu != 0 */
  263. for (j = 0; j < i; j++) {
  264. if ((dmu[j]) && (delta[j] > largest)) {
  265. largest = delta[j];
  266. ro = j;
  267. }
  268. }
  269. /* compute difference */
  270. diff = (mu[i] - mu[ro]);
  271. /* Compute degree of the new smu polynomial */
  272. if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
  273. lmu[i + 1] = lmu[i];
  274. else
  275. lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
  276. /* Init smu[i+1] with 0 */
  277. for (k = 0; k < num; k++)
  278. smu[(i + 1) * num + k] = 0;
  279. /* Compute smu[i+1] */
  280. for (k = 0; k <= lmu[ro] >> 1; k++) {
  281. int16_t a, b, c;
  282. if (!(smu[ro * num + k] && dmu[i]))
  283. continue;
  284. a = readw(index_of + dmu[i]);
  285. b = readw(index_of + dmu[ro]);
  286. c = readw(index_of + smu[ro * num + k]);
  287. tmp = a + (cw_len - b) + c;
  288. a = readw(alpha_to + tmp % cw_len);
  289. smu[(i + 1) * num + (k + diff)] = a;
  290. }
  291. for (k = 0; k <= lmu[i] >> 1; k++)
  292. smu[(i + 1) * num + k] ^= smu[i * num + k];
  293. }
  294. /* End Computing Sigma (Mu+1) and L(mu) */
  295. /* In either case compute delta */
  296. delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
  297. /* Do not compute discrepancy for the last iteration */
  298. if (i >= cap)
  299. continue;
  300. for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
  301. tmp = 2 * (i - 1);
  302. if (k == 0) {
  303. dmu[i + 1] = si[tmp + 3];
  304. } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
  305. int16_t a, b, c;
  306. a = readw(index_of +
  307. smu[(i + 1) * num + k]);
  308. b = si[2 * (i - 1) + 3 - k];
  309. c = readw(index_of + b);
  310. tmp = a + c;
  311. tmp %= cw_len;
  312. dmu[i + 1] = readw(alpha_to + tmp) ^
  313. dmu[i + 1];
  314. }
  315. }
  316. }
  317. }
  318. static int pmecc_err_location(struct mtd_info *mtd)
  319. {
  320. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  321. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  322. const int cap = host->pmecc_corr_cap;
  323. const int num = 2 * cap + 1;
  324. int sector_size = host->pmecc_sector_size;
  325. int err_nbr = 0; /* number of error */
  326. int roots_nbr; /* number of roots */
  327. int i;
  328. uint32_t val;
  329. int16_t *smu = host->pmecc_smu;
  330. int timeout = PMECC_MAX_TIMEOUT_US;
  331. pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
  332. for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
  333. pmecc_writel(host->pmerrloc, sigma[i],
  334. smu[(cap + 1) * num + i]);
  335. err_nbr++;
  336. }
  337. val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
  338. if (sector_size == 1024)
  339. val |= PMERRLOC_ELCFG_SECTOR_1024;
  340. pmecc_writel(host->pmerrloc, elcfg, val);
  341. pmecc_writel(host->pmerrloc, elen,
  342. sector_size * 8 + host->pmecc_degree * cap);
  343. while (--timeout) {
  344. if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
  345. break;
  346. WATCHDOG_RESET();
  347. udelay(1);
  348. }
  349. if (!timeout) {
  350. dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
  351. return -1;
  352. }
  353. roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
  354. >> 8;
  355. /* Number of roots == degree of smu hence <= cap */
  356. if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
  357. return err_nbr - 1;
  358. /* Number of roots does not match the degree of smu
  359. * unable to correct error */
  360. return -1;
  361. }
  362. static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
  363. int sector_num, int extra_bytes, int err_nbr)
  364. {
  365. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  366. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  367. int i = 0;
  368. int byte_pos, bit_pos, sector_size, pos;
  369. uint32_t tmp;
  370. uint8_t err_byte;
  371. sector_size = host->pmecc_sector_size;
  372. while (err_nbr) {
  373. tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
  374. byte_pos = tmp / 8;
  375. bit_pos = tmp % 8;
  376. if (byte_pos >= (sector_size + extra_bytes))
  377. BUG(); /* should never happen */
  378. if (byte_pos < sector_size) {
  379. err_byte = *(buf + byte_pos);
  380. *(buf + byte_pos) ^= (1 << bit_pos);
  381. pos = sector_num * host->pmecc_sector_size + byte_pos;
  382. dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
  383. pos, bit_pos, err_byte, *(buf + byte_pos));
  384. } else {
  385. /* Bit flip in OOB area */
  386. tmp = sector_num * host->pmecc_bytes_per_sector
  387. + (byte_pos - sector_size);
  388. err_byte = ecc[tmp];
  389. ecc[tmp] ^= (1 << bit_pos);
  390. pos = tmp + nand_chip->ecc.layout->eccpos[0];
  391. dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
  392. pos, bit_pos, err_byte, ecc[tmp]);
  393. }
  394. i++;
  395. err_nbr--;
  396. }
  397. return;
  398. }
  399. static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
  400. u8 *ecc)
  401. {
  402. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  403. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  404. int i, err_nbr, eccbytes;
  405. uint8_t *buf_pos;
  406. /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
  407. if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
  408. goto normal_check;
  409. eccbytes = nand_chip->ecc.bytes;
  410. for (i = 0; i < eccbytes; i++)
  411. if (ecc[i] != 0xff)
  412. goto normal_check;
  413. /* Erased page, return OK */
  414. return 0;
  415. normal_check:
  416. for (i = 0; i < host->pmecc_sector_number; i++) {
  417. err_nbr = 0;
  418. if (pmecc_stat & 0x1) {
  419. buf_pos = buf + i * host->pmecc_sector_size;
  420. pmecc_gen_syndrome(mtd, i);
  421. pmecc_substitute(mtd);
  422. pmecc_get_sigma(mtd);
  423. err_nbr = pmecc_err_location(mtd);
  424. if (err_nbr == -1) {
  425. dev_err(host->dev, "PMECC: Too many errors\n");
  426. mtd->ecc_stats.failed++;
  427. return -EBADMSG;
  428. } else {
  429. pmecc_correct_data(mtd, buf_pos, ecc, i,
  430. host->pmecc_bytes_per_sector, err_nbr);
  431. mtd->ecc_stats.corrected += err_nbr;
  432. }
  433. }
  434. pmecc_stat >>= 1;
  435. }
  436. return 0;
  437. }
  438. static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
  439. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  440. {
  441. struct atmel_nand_host *host = nand_get_controller_data(chip);
  442. int eccsize = chip->ecc.size;
  443. uint8_t *oob = chip->oob_poi;
  444. uint32_t *eccpos = chip->ecc.layout->eccpos;
  445. uint32_t stat;
  446. int timeout = PMECC_MAX_TIMEOUT_US;
  447. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  448. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  449. pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
  450. & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
  451. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  452. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
  453. chip->read_buf(mtd, buf, eccsize);
  454. chip->read_buf(mtd, oob, mtd->oobsize);
  455. while (--timeout) {
  456. if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
  457. break;
  458. WATCHDOG_RESET();
  459. udelay(1);
  460. }
  461. if (!timeout) {
  462. dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
  463. return -1;
  464. }
  465. stat = pmecc_readl(host->pmecc, isr);
  466. if (stat != 0)
  467. if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
  468. return -EBADMSG;
  469. return 0;
  470. }
  471. static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
  472. struct nand_chip *chip, const uint8_t *buf,
  473. int oob_required, int page)
  474. {
  475. struct atmel_nand_host *host = nand_get_controller_data(chip);
  476. uint32_t *eccpos = chip->ecc.layout->eccpos;
  477. int i, j;
  478. int timeout = PMECC_MAX_TIMEOUT_US;
  479. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  480. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  481. pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
  482. PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
  483. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  484. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
  485. chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
  486. while (--timeout) {
  487. if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
  488. break;
  489. WATCHDOG_RESET();
  490. udelay(1);
  491. }
  492. if (!timeout) {
  493. dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
  494. goto out;
  495. }
  496. for (i = 0; i < host->pmecc_sector_number; i++) {
  497. for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
  498. int pos;
  499. pos = i * host->pmecc_bytes_per_sector + j;
  500. chip->oob_poi[eccpos[pos]] =
  501. pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
  502. }
  503. }
  504. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  505. out:
  506. return 0;
  507. }
  508. static void atmel_pmecc_core_init(struct mtd_info *mtd)
  509. {
  510. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  511. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  512. uint32_t val = 0;
  513. struct nand_ecclayout *ecc_layout;
  514. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  515. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  516. switch (host->pmecc_corr_cap) {
  517. case 2:
  518. val = PMECC_CFG_BCH_ERR2;
  519. break;
  520. case 4:
  521. val = PMECC_CFG_BCH_ERR4;
  522. break;
  523. case 8:
  524. val = PMECC_CFG_BCH_ERR8;
  525. break;
  526. case 12:
  527. val = PMECC_CFG_BCH_ERR12;
  528. break;
  529. case 24:
  530. val = PMECC_CFG_BCH_ERR24;
  531. break;
  532. case 32:
  533. val = PMECC_CFG_BCH_ERR32;
  534. break;
  535. }
  536. if (host->pmecc_sector_size == 512)
  537. val |= PMECC_CFG_SECTOR512;
  538. else if (host->pmecc_sector_size == 1024)
  539. val |= PMECC_CFG_SECTOR1024;
  540. switch (host->pmecc_sector_number) {
  541. case 1:
  542. val |= PMECC_CFG_PAGE_1SECTOR;
  543. break;
  544. case 2:
  545. val |= PMECC_CFG_PAGE_2SECTORS;
  546. break;
  547. case 4:
  548. val |= PMECC_CFG_PAGE_4SECTORS;
  549. break;
  550. case 8:
  551. val |= PMECC_CFG_PAGE_8SECTORS;
  552. break;
  553. }
  554. val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
  555. | PMECC_CFG_AUTO_DISABLE);
  556. pmecc_writel(host->pmecc, cfg, val);
  557. ecc_layout = nand_chip->ecc.layout;
  558. pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
  559. pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
  560. pmecc_writel(host->pmecc, eaddr,
  561. ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
  562. /* See datasheet about PMECC Clock Control Register */
  563. pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
  564. pmecc_writel(host->pmecc, idr, 0xff);
  565. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  566. }
  567. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  568. /*
  569. * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
  570. * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
  571. * ONFI ECC parameters.
  572. * @host: point to an atmel_nand_host structure.
  573. * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
  574. * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
  575. * @chip: point to an nand_chip structure.
  576. * @cap: store the ONFI ECC correct bits capbility
  577. * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
  578. *
  579. * Return 0 if success. otherwise return the error code.
  580. */
  581. static int pmecc_choose_ecc(struct atmel_nand_host *host,
  582. struct nand_chip *chip,
  583. int *cap, int *sector_size)
  584. {
  585. /* Get ECC requirement from ONFI parameters */
  586. *cap = *sector_size = 0;
  587. if (chip->onfi_version) {
  588. *cap = chip->ecc_strength_ds;
  589. *sector_size = chip->ecc_step_ds;
  590. pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
  591. *cap, *sector_size);
  592. }
  593. if (*cap == 0 && *sector_size == 0) {
  594. /* Non-ONFI compliant */
  595. dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
  596. *cap = 2;
  597. *sector_size = 512;
  598. }
  599. /* If head file doesn't specify then use the one in ONFI parameters */
  600. if (host->pmecc_corr_cap == 0) {
  601. /* use the most fitable ecc bits (the near bigger one ) */
  602. if (*cap <= 2)
  603. host->pmecc_corr_cap = 2;
  604. else if (*cap <= 4)
  605. host->pmecc_corr_cap = 4;
  606. else if (*cap <= 8)
  607. host->pmecc_corr_cap = 8;
  608. else if (*cap <= 12)
  609. host->pmecc_corr_cap = 12;
  610. else if (*cap <= 24)
  611. host->pmecc_corr_cap = 24;
  612. else
  613. #ifdef CONFIG_SAMA5D2
  614. host->pmecc_corr_cap = 32;
  615. #else
  616. host->pmecc_corr_cap = 24;
  617. #endif
  618. }
  619. if (host->pmecc_sector_size == 0) {
  620. /* use the most fitable sector size (the near smaller one ) */
  621. if (*sector_size >= 1024)
  622. host->pmecc_sector_size = 1024;
  623. else if (*sector_size >= 512)
  624. host->pmecc_sector_size = 512;
  625. else
  626. return -EINVAL;
  627. }
  628. return 0;
  629. }
  630. #endif
  631. #if defined(NO_GALOIS_TABLE_IN_ROM)
  632. static uint16_t *pmecc_galois_table;
  633. static inline int deg(unsigned int poly)
  634. {
  635. /* polynomial degree is the most-significant bit index */
  636. return fls(poly) - 1;
  637. }
  638. static int build_gf_tables(int mm, unsigned int poly,
  639. int16_t *index_of, int16_t *alpha_to)
  640. {
  641. unsigned int i, x = 1;
  642. const unsigned int k = 1 << deg(poly);
  643. unsigned int nn = (1 << mm) - 1;
  644. /* primitive polynomial must be of degree m */
  645. if (k != (1u << mm))
  646. return -EINVAL;
  647. for (i = 0; i < nn; i++) {
  648. alpha_to[i] = x;
  649. index_of[x] = i;
  650. if (i && (x == 1))
  651. /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
  652. return -EINVAL;
  653. x <<= 1;
  654. if (x & k)
  655. x ^= poly;
  656. }
  657. alpha_to[nn] = 1;
  658. index_of[0] = 0;
  659. return 0;
  660. }
  661. static uint16_t *create_lookup_table(int sector_size)
  662. {
  663. int degree = (sector_size == 512) ?
  664. PMECC_GF_DIMENSION_13 :
  665. PMECC_GF_DIMENSION_14;
  666. unsigned int poly = (sector_size == 512) ?
  667. PMECC_GF_13_PRIMITIVE_POLY :
  668. PMECC_GF_14_PRIMITIVE_POLY;
  669. int table_size = (sector_size == 512) ?
  670. PMECC_INDEX_TABLE_SIZE_512 :
  671. PMECC_INDEX_TABLE_SIZE_1024;
  672. int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
  673. if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
  674. return NULL;
  675. return (uint16_t *)addr;
  676. }
  677. #endif
  678. static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
  679. struct mtd_info *mtd)
  680. {
  681. struct atmel_nand_host *host;
  682. int cap, sector_size;
  683. host = &pmecc_host;
  684. nand_set_controller_data(nand, host);
  685. nand->ecc.mode = NAND_ECC_HW;
  686. nand->ecc.calculate = NULL;
  687. nand->ecc.correct = NULL;
  688. nand->ecc.hwctl = NULL;
  689. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  690. host->pmecc_corr_cap = host->pmecc_sector_size = 0;
  691. #ifdef CONFIG_PMECC_CAP
  692. host->pmecc_corr_cap = CONFIG_PMECC_CAP;
  693. #endif
  694. #ifdef CONFIG_PMECC_SECTOR_SIZE
  695. host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
  696. #endif
  697. /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
  698. * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
  699. * from ONFI.
  700. */
  701. if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
  702. dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
  703. cap, sector_size);
  704. return -EINVAL;
  705. }
  706. if (cap > host->pmecc_corr_cap)
  707. dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
  708. host->pmecc_corr_cap, cap);
  709. if (sector_size < host->pmecc_sector_size)
  710. dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
  711. host->pmecc_sector_size, sector_size);
  712. #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
  713. host->pmecc_corr_cap = CONFIG_PMECC_CAP;
  714. host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
  715. #endif
  716. cap = host->pmecc_corr_cap;
  717. sector_size = host->pmecc_sector_size;
  718. /* TODO: need check whether cap & sector_size is validate */
  719. #if defined(NO_GALOIS_TABLE_IN_ROM)
  720. /*
  721. * As pmecc_rom_base is the begin of the gallois field table, So the
  722. * index offset just set as 0.
  723. */
  724. host->pmecc_index_table_offset = 0;
  725. #else
  726. if (host->pmecc_sector_size == 512)
  727. host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
  728. else
  729. host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
  730. #endif
  731. pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
  732. cap, sector_size);
  733. host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
  734. host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
  735. ATMEL_BASE_PMERRLOC;
  736. #if defined(NO_GALOIS_TABLE_IN_ROM)
  737. pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
  738. if (!pmecc_galois_table) {
  739. dev_err(host->dev, "out of memory\n");
  740. return -ENOMEM;
  741. }
  742. host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
  743. #else
  744. host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
  745. #endif
  746. /* ECC is calculated for the whole page (1 step) */
  747. nand->ecc.size = mtd->writesize;
  748. /* set ECC page size and oob layout */
  749. switch (mtd->writesize) {
  750. case 2048:
  751. case 4096:
  752. case 8192:
  753. host->pmecc_degree = (sector_size == 512) ?
  754. PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
  755. host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
  756. host->pmecc_sector_number = mtd->writesize / sector_size;
  757. host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
  758. cap, sector_size);
  759. host->pmecc_alpha_to = pmecc_get_alpha_to(host);
  760. host->pmecc_index_of = host->pmecc_rom_base +
  761. host->pmecc_index_table_offset;
  762. nand->ecc.steps = 1;
  763. nand->ecc.bytes = host->pmecc_bytes_per_sector *
  764. host->pmecc_sector_number;
  765. if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
  766. dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
  767. MTD_MAX_ECCPOS_ENTRIES_LARGE);
  768. return -EINVAL;
  769. }
  770. if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
  771. dev_err(host->dev, "No room for ECC bytes\n");
  772. return -EINVAL;
  773. }
  774. pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
  775. mtd->oobsize,
  776. nand->ecc.bytes);
  777. nand->ecc.layout = &atmel_pmecc_oobinfo;
  778. break;
  779. case 512:
  780. case 1024:
  781. /* TODO */
  782. dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
  783. default:
  784. /* page size not handled by HW ECC */
  785. /* switching back to soft ECC */
  786. nand->ecc.mode = NAND_ECC_SOFT;
  787. nand->ecc.read_page = NULL;
  788. nand->ecc.postpad = 0;
  789. nand->ecc.prepad = 0;
  790. nand->ecc.bytes = 0;
  791. return 0;
  792. }
  793. /* Allocate data for PMECC computation */
  794. if (pmecc_data_alloc(host)) {
  795. dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
  796. return -ENOMEM;
  797. }
  798. nand->options |= NAND_NO_SUBPAGE_WRITE;
  799. nand->ecc.read_page = atmel_nand_pmecc_read_page;
  800. nand->ecc.write_page = atmel_nand_pmecc_write_page;
  801. nand->ecc.strength = cap;
  802. /* Check the PMECC ip version */
  803. host->pmecc_version = pmecc_readl(host->pmerrloc, version);
  804. dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
  805. atmel_pmecc_core_init(mtd);
  806. return 0;
  807. }
  808. #else
  809. /* oob layout for large page size
  810. * bad block info is on bytes 0 and 1
  811. * the bytes have to be consecutives to avoid
  812. * several NAND_CMD_RNDOUT during read
  813. */
  814. static struct nand_ecclayout atmel_oobinfo_large = {
  815. .eccbytes = 4,
  816. .eccpos = {60, 61, 62, 63},
  817. .oobfree = {
  818. {2, 58}
  819. },
  820. };
  821. /* oob layout for small page size
  822. * bad block info is on bytes 4 and 5
  823. * the bytes have to be consecutives to avoid
  824. * several NAND_CMD_RNDOUT during read
  825. */
  826. static struct nand_ecclayout atmel_oobinfo_small = {
  827. .eccbytes = 4,
  828. .eccpos = {0, 1, 2, 3},
  829. .oobfree = {
  830. {6, 10}
  831. },
  832. };
  833. /*
  834. * Calculate HW ECC
  835. *
  836. * function called after a write
  837. *
  838. * mtd: MTD block structure
  839. * dat: raw data (unused)
  840. * ecc_code: buffer for ECC
  841. */
  842. static int atmel_nand_calculate(struct mtd_info *mtd,
  843. const u_char *dat, unsigned char *ecc_code)
  844. {
  845. unsigned int ecc_value;
  846. /* get the first 2 ECC bytes */
  847. ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
  848. ecc_code[0] = ecc_value & 0xFF;
  849. ecc_code[1] = (ecc_value >> 8) & 0xFF;
  850. /* get the last 2 ECC bytes */
  851. ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
  852. ecc_code[2] = ecc_value & 0xFF;
  853. ecc_code[3] = (ecc_value >> 8) & 0xFF;
  854. return 0;
  855. }
  856. /*
  857. * HW ECC read page function
  858. *
  859. * mtd: mtd info structure
  860. * chip: nand chip info structure
  861. * buf: buffer to store read data
  862. * oob_required: caller expects OOB data read to chip->oob_poi
  863. */
  864. static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  865. uint8_t *buf, int oob_required, int page)
  866. {
  867. int eccsize = chip->ecc.size;
  868. int eccbytes = chip->ecc.bytes;
  869. uint32_t *eccpos = chip->ecc.layout->eccpos;
  870. uint8_t *p = buf;
  871. uint8_t *oob = chip->oob_poi;
  872. uint8_t *ecc_pos;
  873. int stat;
  874. /* read the page */
  875. chip->read_buf(mtd, p, eccsize);
  876. /* move to ECC position if needed */
  877. if (eccpos[0] != 0) {
  878. /* This only works on large pages
  879. * because the ECC controller waits for
  880. * NAND_CMD_RNDOUTSTART after the
  881. * NAND_CMD_RNDOUT.
  882. * anyway, for small pages, the eccpos[0] == 0
  883. */
  884. chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
  885. mtd->writesize + eccpos[0], -1);
  886. }
  887. /* the ECC controller needs to read the ECC just after the data */
  888. ecc_pos = oob + eccpos[0];
  889. chip->read_buf(mtd, ecc_pos, eccbytes);
  890. /* check if there's an error */
  891. stat = chip->ecc.correct(mtd, p, oob, NULL);
  892. if (stat < 0)
  893. mtd->ecc_stats.failed++;
  894. else
  895. mtd->ecc_stats.corrected += stat;
  896. /* get back to oob start (end of page) */
  897. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
  898. /* read the oob */
  899. chip->read_buf(mtd, oob, mtd->oobsize);
  900. return 0;
  901. }
  902. /*
  903. * HW ECC Correction
  904. *
  905. * function called after a read
  906. *
  907. * mtd: MTD block structure
  908. * dat: raw data read from the chip
  909. * read_ecc: ECC from the chip (unused)
  910. * isnull: unused
  911. *
  912. * Detect and correct a 1 bit error for a page
  913. */
  914. static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
  915. u_char *read_ecc, u_char *isnull)
  916. {
  917. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  918. unsigned int ecc_status;
  919. unsigned int ecc_word, ecc_bit;
  920. /* get the status from the Status Register */
  921. ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
  922. /* if there's no error */
  923. if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
  924. return 0;
  925. /* get error bit offset (4 bits) */
  926. ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
  927. /* get word address (12 bits) */
  928. ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
  929. ecc_word >>= 4;
  930. /* if there are multiple errors */
  931. if (ecc_status & ATMEL_ECC_MULERR) {
  932. /* check if it is a freshly erased block
  933. * (filled with 0xff) */
  934. if ((ecc_bit == ATMEL_ECC_BITADDR)
  935. && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
  936. /* the block has just been erased, return OK */
  937. return 0;
  938. }
  939. /* it doesn't seems to be a freshly
  940. * erased block.
  941. * We can't correct so many errors */
  942. dev_warn(host->dev, "atmel_nand : multiple errors detected."
  943. " Unable to correct.\n");
  944. return -EBADMSG;
  945. }
  946. /* if there's a single bit error : we can correct it */
  947. if (ecc_status & ATMEL_ECC_ECCERR) {
  948. /* there's nothing much to do here.
  949. * the bit error is on the ECC itself.
  950. */
  951. dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
  952. " Nothing to correct\n");
  953. return 0;
  954. }
  955. dev_warn(host->dev, "atmel_nand : one bit error on data."
  956. " (word offset in the page :"
  957. " 0x%x bit offset : 0x%x)\n",
  958. ecc_word, ecc_bit);
  959. /* correct the error */
  960. if (nand_chip->options & NAND_BUSWIDTH_16) {
  961. /* 16 bits words */
  962. ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
  963. } else {
  964. /* 8 bits words */
  965. dat[ecc_word] ^= (1 << ecc_bit);
  966. }
  967. dev_warn(host->dev, "atmel_nand : error corrected\n");
  968. return 1;
  969. }
  970. /*
  971. * Enable HW ECC : unused on most chips
  972. */
  973. static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
  974. {
  975. }
  976. int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
  977. {
  978. nand->ecc.mode = NAND_ECC_HW;
  979. nand->ecc.calculate = atmel_nand_calculate;
  980. nand->ecc.correct = atmel_nand_correct;
  981. nand->ecc.hwctl = atmel_nand_hwctl;
  982. nand->ecc.read_page = atmel_nand_read_page;
  983. nand->ecc.bytes = 4;
  984. nand->ecc.strength = 4;
  985. if (nand->ecc.mode == NAND_ECC_HW) {
  986. /* ECC is calculated for the whole page (1 step) */
  987. nand->ecc.size = mtd->writesize;
  988. /* set ECC page size and oob layout */
  989. switch (mtd->writesize) {
  990. case 512:
  991. nand->ecc.layout = &atmel_oobinfo_small;
  992. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  993. ATMEL_ECC_PAGESIZE_528);
  994. break;
  995. case 1024:
  996. nand->ecc.layout = &atmel_oobinfo_large;
  997. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  998. ATMEL_ECC_PAGESIZE_1056);
  999. break;
  1000. case 2048:
  1001. nand->ecc.layout = &atmel_oobinfo_large;
  1002. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1003. ATMEL_ECC_PAGESIZE_2112);
  1004. break;
  1005. case 4096:
  1006. nand->ecc.layout = &atmel_oobinfo_large;
  1007. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1008. ATMEL_ECC_PAGESIZE_4224);
  1009. break;
  1010. default:
  1011. /* page size not handled by HW ECC */
  1012. /* switching back to soft ECC */
  1013. nand->ecc.mode = NAND_ECC_SOFT;
  1014. nand->ecc.calculate = NULL;
  1015. nand->ecc.correct = NULL;
  1016. nand->ecc.hwctl = NULL;
  1017. nand->ecc.read_page = NULL;
  1018. nand->ecc.postpad = 0;
  1019. nand->ecc.prepad = 0;
  1020. nand->ecc.bytes = 0;
  1021. break;
  1022. }
  1023. }
  1024. return 0;
  1025. }
  1026. #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
  1027. #endif /* CONFIG_ATMEL_NAND_HWECC */
  1028. static void at91_nand_hwcontrol(struct mtd_info *mtd,
  1029. int cmd, unsigned int ctrl)
  1030. {
  1031. struct nand_chip *this = mtd_to_nand(mtd);
  1032. if (ctrl & NAND_CTRL_CHANGE) {
  1033. ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  1034. IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
  1035. | CONFIG_SYS_NAND_MASK_CLE);
  1036. if (ctrl & NAND_CLE)
  1037. IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
  1038. if (ctrl & NAND_ALE)
  1039. IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
  1040. #ifdef CONFIG_SYS_NAND_ENABLE_PIN
  1041. at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
  1042. !(ctrl & NAND_NCE));
  1043. #endif
  1044. this->IO_ADDR_W = (void *) IO_ADDR_W;
  1045. }
  1046. if (cmd != NAND_CMD_NONE)
  1047. writeb(cmd, this->IO_ADDR_W);
  1048. }
  1049. #ifdef CONFIG_SYS_NAND_READY_PIN
  1050. static int at91_nand_ready(struct mtd_info *mtd)
  1051. {
  1052. return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
  1053. }
  1054. #endif
  1055. #ifdef CONFIG_SPL_BUILD
  1056. /* The following code is for SPL */
  1057. static struct mtd_info *mtd;
  1058. static struct nand_chip nand_chip;
  1059. static int nand_command(int block, int page, uint32_t offs, u8 cmd)
  1060. {
  1061. struct nand_chip *this = mtd_to_nand(mtd);
  1062. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1063. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1064. unsigned int ctrl) = this->cmd_ctrl;
  1065. while (!this->dev_ready(mtd))
  1066. ;
  1067. if (cmd == NAND_CMD_READOOB) {
  1068. offs += CONFIG_SYS_NAND_PAGE_SIZE;
  1069. cmd = NAND_CMD_READ0;
  1070. }
  1071. hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1072. if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
  1073. offs >>= 1;
  1074. hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1075. hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
  1076. hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
  1077. hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
  1078. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1079. hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
  1080. #endif
  1081. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1082. hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1083. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1084. while (!this->dev_ready(mtd))
  1085. ;
  1086. return 0;
  1087. }
  1088. static int nand_is_bad_block(int block)
  1089. {
  1090. struct nand_chip *this = mtd_to_nand(mtd);
  1091. nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
  1092. if (this->options & NAND_BUSWIDTH_16) {
  1093. if (readw(this->IO_ADDR_R) != 0xffff)
  1094. return 1;
  1095. } else {
  1096. if (readb(this->IO_ADDR_R) != 0xff)
  1097. return 1;
  1098. }
  1099. return 0;
  1100. }
  1101. #ifdef CONFIG_SPL_NAND_ECC
  1102. static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  1103. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  1104. CONFIG_SYS_NAND_ECCSIZE)
  1105. #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  1106. static int nand_read_page(int block, int page, void *dst)
  1107. {
  1108. struct nand_chip *this = mtd_to_nand(mtd);
  1109. u_char ecc_calc[ECCTOTAL];
  1110. u_char ecc_code[ECCTOTAL];
  1111. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  1112. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  1113. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  1114. int eccsteps = ECCSTEPS;
  1115. int i;
  1116. uint8_t *p = dst;
  1117. nand_command(block, page, 0, NAND_CMD_READ0);
  1118. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1119. if (this->ecc.mode != NAND_ECC_SOFT)
  1120. this->ecc.hwctl(mtd, NAND_ECC_READ);
  1121. this->read_buf(mtd, p, eccsize);
  1122. this->ecc.calculate(mtd, p, &ecc_calc[i]);
  1123. }
  1124. this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  1125. for (i = 0; i < ECCTOTAL; i++)
  1126. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  1127. eccsteps = ECCSTEPS;
  1128. p = dst;
  1129. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1130. this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1131. return 0;
  1132. }
  1133. int spl_nand_erase_one(int block, int page)
  1134. {
  1135. struct nand_chip *this = mtd_to_nand(mtd);
  1136. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1137. unsigned int ctrl) = this->cmd_ctrl;
  1138. int page_addr;
  1139. if (nand_chip.select_chip)
  1140. nand_chip.select_chip(mtd, 0);
  1141. page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1142. hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1143. /* Row address */
  1144. hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1145. hwctrl(mtd, ((page_addr >> 8) & 0xff),
  1146. NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1147. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1148. /* One more address cycle for devices > 128MiB */
  1149. hwctrl(mtd, (page_addr >> 16) & 0x0f,
  1150. NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1151. #endif
  1152. hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1153. while (!this->dev_ready(mtd))
  1154. ;
  1155. nand_deselect();
  1156. return 0;
  1157. }
  1158. #else
  1159. static int nand_read_page(int block, int page, void *dst)
  1160. {
  1161. struct nand_chip *this = mtd_to_nand(mtd);
  1162. nand_command(block, page, 0, NAND_CMD_READ0);
  1163. atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
  1164. return 0;
  1165. }
  1166. #endif /* CONFIG_SPL_NAND_ECC */
  1167. int at91_nand_wait_ready(struct mtd_info *mtd)
  1168. {
  1169. struct nand_chip *this = mtd_to_nand(mtd);
  1170. udelay(this->chip_delay);
  1171. return 1;
  1172. }
  1173. int board_nand_init(struct nand_chip *nand)
  1174. {
  1175. int ret = 0;
  1176. nand->ecc.mode = NAND_ECC_SOFT;
  1177. #ifdef CONFIG_SYS_NAND_DBW_16
  1178. nand->options = NAND_BUSWIDTH_16;
  1179. nand->read_buf = nand_read_buf16;
  1180. #else
  1181. nand->read_buf = nand_read_buf;
  1182. #endif
  1183. nand->cmd_ctrl = at91_nand_hwcontrol;
  1184. #ifdef CONFIG_SYS_NAND_READY_PIN
  1185. nand->dev_ready = at91_nand_ready;
  1186. #else
  1187. nand->dev_ready = at91_nand_wait_ready;
  1188. #endif
  1189. nand->chip_delay = 20;
  1190. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1191. nand->bbt_options |= NAND_BBT_USE_FLASH;
  1192. #endif
  1193. #ifdef CONFIG_ATMEL_NAND_HWECC
  1194. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1195. ret = atmel_pmecc_nand_init_params(nand, mtd);
  1196. #endif
  1197. #endif
  1198. return ret;
  1199. }
  1200. void nand_init(void)
  1201. {
  1202. mtd = nand_to_mtd(&nand_chip);
  1203. mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
  1204. mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
  1205. nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1206. nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1207. board_nand_init(&nand_chip);
  1208. #ifdef CONFIG_SPL_NAND_ECC
  1209. if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
  1210. nand_chip.ecc.calculate = nand_calculate_ecc;
  1211. nand_chip.ecc.correct = nand_correct_data;
  1212. }
  1213. #endif
  1214. if (nand_chip.select_chip)
  1215. nand_chip.select_chip(mtd, 0);
  1216. }
  1217. void nand_deselect(void)
  1218. {
  1219. if (nand_chip.select_chip)
  1220. nand_chip.select_chip(mtd, -1);
  1221. }
  1222. #include "nand_spl_loaders.c"
  1223. #else
  1224. #ifndef CONFIG_SYS_NAND_BASE_LIST
  1225. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  1226. #endif
  1227. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  1228. static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
  1229. int atmel_nand_chip_init(int devnum, ulong base_addr)
  1230. {
  1231. int ret;
  1232. struct nand_chip *nand = &nand_chip[devnum];
  1233. struct mtd_info *mtd = nand_to_mtd(nand);
  1234. nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
  1235. #ifdef CONFIG_NAND_ECC_BCH
  1236. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  1237. #else
  1238. nand->ecc.mode = NAND_ECC_SOFT;
  1239. #endif
  1240. #ifdef CONFIG_SYS_NAND_DBW_16
  1241. nand->options = NAND_BUSWIDTH_16;
  1242. #endif
  1243. nand->cmd_ctrl = at91_nand_hwcontrol;
  1244. #ifdef CONFIG_SYS_NAND_READY_PIN
  1245. nand->dev_ready = at91_nand_ready;
  1246. #endif
  1247. nand->chip_delay = 75;
  1248. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1249. nand->bbt_options |= NAND_BBT_USE_FLASH;
  1250. #endif
  1251. ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  1252. if (ret)
  1253. return ret;
  1254. #ifdef CONFIG_ATMEL_NAND_HWECC
  1255. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1256. ret = atmel_pmecc_nand_init_params(nand, mtd);
  1257. #else
  1258. ret = atmel_hwecc_nand_init_param(nand, mtd);
  1259. #endif
  1260. if (ret)
  1261. return ret;
  1262. #endif
  1263. ret = nand_scan_tail(mtd);
  1264. if (!ret)
  1265. nand_register(devnum, mtd);
  1266. return ret;
  1267. }
  1268. void board_nand_init(void)
  1269. {
  1270. int i;
  1271. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  1272. if (atmel_nand_chip_init(i, base_addr[i]))
  1273. dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
  1274. i);
  1275. }
  1276. #endif /* CONFIG_SPL_BUILD */