spl.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2021 Linumiz
  4. * Author: Navin Sankar Velliangiri <navin@linumiz.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <spl.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/mx6-ddr.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <fsl_esdhc_imx.h>
  16. /* Configuration for Micron MT41K256M16TW-107 32M x 16 x 8 -> 512MiB */
  17. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  18. .grp_addds = 0x00000030,
  19. .grp_ddrmode_ctl = 0x00020000,
  20. .grp_b0ds = 0x00000030,
  21. .grp_ctlds = 0x00000030,
  22. .grp_b1ds = 0x00000030,
  23. .grp_ddrpke = 0x00000000,
  24. .grp_ddrmode = 0x00020000,
  25. .grp_ddr_type = 0x000c0000,
  26. };
  27. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  28. .dram_dqm0 = 0x00000030,
  29. .dram_dqm1 = 0x00000030,
  30. .dram_ras = 0x00000030,
  31. .dram_cas = 0x00000030,
  32. .dram_odt0 = 0x00000030,
  33. .dram_odt1 = 0x00000030,
  34. .dram_sdba2 = 0x00000000,
  35. .dram_sdclk_0 = 0x00000030,
  36. .dram_sdqs0 = 0x00000030,
  37. .dram_sdqs1 = 0x00000030,
  38. .dram_reset = 0x00000030,
  39. };
  40. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  41. .p0_mpwldectrl0 = 0x00000000,
  42. .p0_mpdgctrl0 = 0x41480148,
  43. .p0_mprddlctl = 0x40403E42,
  44. .p0_mpwrdlctl = 0x40405852,
  45. };
  46. struct mx6_ddr_sysinfo ddr_sysinfo = {
  47. .dsize = 0, /* Bus size = 16bit */
  48. .cs_density = 32,
  49. .ncs = 1,
  50. .cs1_mirror = 0,
  51. .rtt_wr = 1,
  52. .rtt_nom = 1,
  53. .walat = 1, /* Write additional latency */
  54. .ralat = 5, /* Read additional latency */
  55. .mif3_mode = 3, /* Command prediction working mode */
  56. .bi_on = 1, /* Bank interleaving enabled */
  57. .pd_fast_exit = 1,
  58. .sde_to_rst = 0x10,
  59. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  60. .ddr_type = DDR_TYPE_DDR3,
  61. .refsel = 1, /* Refresh cycles at 32KHz */
  62. .refr = 7, /* 8 refresh commands per refresh cycle */
  63. };
  64. static struct mx6_ddr3_cfg mem_ddr = {
  65. .mem_speed = 1600,
  66. .density = 4,
  67. .width = 16,
  68. .banks = 8,
  69. .rowaddr = 15,
  70. .coladdr = 10,
  71. .pagesz = 2,
  72. .trcd = 1375,
  73. .trcmin = 4875,
  74. .trasmin = 3500,
  75. };
  76. static void ccgr_init(void)
  77. {
  78. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  79. writel(0xFFFFFFFF, &ccm->CCGR0);
  80. writel(0xFFFFFFFF, &ccm->CCGR1);
  81. writel(0xFFFFFFFF, &ccm->CCGR2);
  82. writel(0xFFFFFFFF, &ccm->CCGR3);
  83. writel(0xFFFFFFFF, &ccm->CCGR4);
  84. writel(0xFFFFFFFF, &ccm->CCGR5);
  85. writel(0xFFFFFFFF, &ccm->CCGR6);
  86. }
  87. static void spl_dram_init(void)
  88. {
  89. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  90. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  91. }
  92. #ifdef CONFIG_FSL_ESDHC_IMX
  93. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  94. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  95. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  96. PAD_CTL_HYS)
  97. static iomux_v3_cfg_t const usdhc1_pads[] = {
  98. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104. MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105. };
  106. #ifndef CONFIG_NAND_MXS
  107. static iomux_v3_cfg_t const usdhc2_pads[] = {
  108. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. };
  119. #endif
  120. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  121. {
  122. .esdhc_base = USDHC1_BASE_ADDR,
  123. .max_bus_width = 4,
  124. },
  125. #ifndef CONFIG_NAND_MXS
  126. {
  127. .esdhc_base = USDHC2_BASE_ADDR,
  128. .max_bus_width = 8,
  129. },
  130. #endif
  131. };
  132. int board_mmc_getcd(struct mmc *mmc)
  133. {
  134. return 1;
  135. }
  136. int board_mmc_init(struct bd_info *bis)
  137. {
  138. int i, ret;
  139. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  140. switch (i) {
  141. case 0:
  142. SETUP_IOMUX_PADS(usdhc1_pads);
  143. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  144. break;
  145. #ifndef CONFIG_NAND_MXS
  146. case 1:
  147. SETUP_IOMUX_PADS(usdhc2_pads);
  148. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  149. break;
  150. #endif
  151. default:
  152. printf("Warning - USDHC%d controller not supporting\n",
  153. i + 1);
  154. return 0;
  155. }
  156. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  157. if (ret) {
  158. printf("Warning: failed to initialize mmc dev %d\n", i);
  159. return ret;
  160. }
  161. }
  162. return 0;
  163. }
  164. #endif /* CONFIG_FSL_ESDHC_IMX */
  165. void board_init_f(ulong dummy)
  166. {
  167. ccgr_init();
  168. /* Setup AIPS and disable watchdog */
  169. arch_cpu_init();
  170. /* Setup iomux and fec */
  171. board_early_init_f();
  172. /* Setup GP timer */
  173. timer_init();
  174. /* UART clocks enabled and gd valid - init serial console */
  175. preloader_console_init();
  176. /* DDR initialization */
  177. spl_dram_init();
  178. }