npi_imx6ull.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2021 Linumiz
  4. * Author: Navin Sankar Velliangiri <navin@linumiz.com>
  5. */
  6. #include <init.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/mach-imx/mxc_i2c.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <linux/bitops.h>
  16. #include <miiphy.h>
  17. #include <net.h>
  18. #include <netdev.h>
  19. #include <usb.h>
  20. #include <usb/ehci-ci.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int dram_init(void)
  23. {
  24. gd->ram_size = imx_ddr_size();
  25. return 0;
  26. }
  27. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  28. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
  30. PAD_CTL_HYS)
  31. static iomux_v3_cfg_t const uart1_pads[] = {
  32. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  33. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. };
  35. static void setup_iomux_uart(void)
  36. {
  37. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  38. }
  39. int board_early_init_f(void)
  40. {
  41. setup_iomux_uart();
  42. return 0;
  43. }
  44. #ifdef CONFIG_FEC_MXC
  45. static int setup_fec(int fec_id)
  46. {
  47. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  48. int ret;
  49. if (fec_id == 0) {
  50. /*
  51. * Use 50MHz anatop loopback REF_CLK1 for ENET1,
  52. * clear gpr1[13], set gpr1[17].
  53. */
  54. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  55. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  56. } else {
  57. /*
  58. * Use 50MHz anatop loopbak REF_CLK2 for ENET2,
  59. * clear gpr1[14], set gpr1[18].
  60. */
  61. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  62. IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  63. }
  64. ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  65. if (ret)
  66. return ret;
  67. enable_enet_clk(1);
  68. return 0;
  69. }
  70. int board_phy_config(struct phy_device *phydev)
  71. {
  72. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  73. if (phydev->drv->config)
  74. phydev->drv->config(phydev);
  75. return 0;
  76. }
  77. #endif
  78. int board_init(void)
  79. {
  80. /* Address of boot parameters */
  81. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  82. #ifdef CONFIG_FEC_MXC
  83. setup_fec(CONFIG_FEC_ENET_DEV);
  84. #endif
  85. return 0;
  86. }
  87. int checkboard(void)
  88. {
  89. printf("Board: Seeed NPi i.MX6ULL Dev Board\n");
  90. return 0;
  91. }