imx6ull-seeed-npi-imx6ull.dtsi 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2021 Linumiz
  4. * Author: Navin Sankar Velliangiri <navin@linumiz.com>
  5. */
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/pwm/pwm.h>
  9. / {
  10. model = "Seeed NPi-iMX6ULL Dev Board";
  11. compatible = "fsl,imx6ull";
  12. chosen {
  13. stdout-path = &uart1;
  14. };
  15. leds {
  16. compatible = "gpio-leds";
  17. user-led {
  18. label = "User";
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&pinctrl_gpios>;
  21. gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
  22. linux,default-trigger = "heartbeat";
  23. };
  24. };
  25. };
  26. &gpmi {
  27. pinctrl-names = "default";
  28. pinctrl-0 = <&pinctrl_gpmi_nand>;
  29. nand-on-flash-bbt;
  30. status = "disabled";
  31. };
  32. &uart1 {
  33. pinctrl-name = "default";
  34. pinctrl-0 = <&pinctrl_uart1>;
  35. status = "okay";
  36. };
  37. &usdhc1 {
  38. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  39. pinctrl-0 = <&pinctrl_usdhc1>;
  40. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  41. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  42. cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  43. no-1-8-v;
  44. keep-power-in-suspend;
  45. wakeup-source;
  46. status = "okay";
  47. };
  48. &usdhc2 {
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&pinctrl_usdhc2>;
  51. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  52. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  53. bus-width = <8>;
  54. non-removable;
  55. keep-power-in-suspend;
  56. };
  57. &fec1 {
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_enet1>;
  60. phy-mode = "rmii";
  61. phy-handle = <&ethphy0>;
  62. status = "okay";
  63. };
  64. &fec2 {
  65. pinctrl-names = "default";
  66. pinctrl-0 = <&pinctrl_enet2>;
  67. phy-mode = "rmii";
  68. phy-handle = <&ethphy1>;
  69. status = "okay";
  70. mdio {
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. ethphy0: ethernet-phy@2 {
  74. compatible = "ethernet-phy-ieee802.3-c22";
  75. reg = <2>;
  76. micrel,led-mode = <1>;
  77. clocks = <&clks IMX6UL_CLK_ENET_REF>;
  78. clock-names = "rmii-ref";
  79. };
  80. ethphy1: ethernet-phy@1 {
  81. compatible = "ethernet-phy-ieee802.3-c22";
  82. reg = <1>;
  83. micrel,led-mode = <1>;
  84. clocks = <&clks IMX6UL_CLK_ENET2_REF>;
  85. clock-names = "rmii-ref";
  86. };
  87. };
  88. };
  89. &usbotg1 {
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&pinctrl_usb_otg1_id>;
  92. dr_mode = "otg";
  93. srp-disable;
  94. hnp-disable;
  95. adp-disable;
  96. status = "okay";
  97. };
  98. &usbotg2 {
  99. dr_mode = "host";
  100. disable-over-current;
  101. status = "okay";
  102. };
  103. &iomuxc {
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&pinctrl_gpios>;
  106. pinctrl_uart1: uart1grp {
  107. fsl,pin = <
  108. MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  109. MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  110. >;
  111. };
  112. pinctrl_usb_otg1_id: usbotg1idgrp {
  113. fsl,pin = <
  114. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  115. >;
  116. };
  117. pinctrl_gpmi_nand: gpminandgrp {
  118. fsl,pins = <
  119. MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
  120. MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
  121. MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
  122. MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
  123. MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
  124. MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
  125. MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
  126. MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
  127. MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
  128. MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
  129. MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
  130. MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
  131. MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
  132. MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
  133. MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
  134. MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
  135. MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
  136. >;
  137. };
  138. pinctrl_usdhc1: usdhc1grp {
  139. fsl,pins = <
  140. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
  141. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
  142. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
  143. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
  144. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
  145. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
  146. MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
  147. >;
  148. };
  149. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  150. fsl,pins = <
  151. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
  152. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
  153. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
  154. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
  155. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
  156. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
  157. >;
  158. };
  159. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  160. fsl,pins = <
  161. MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
  162. MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
  163. MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
  164. MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
  165. MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
  166. MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
  167. >;
  168. };
  169. pinctrl_usdhc2: usdhc2grp {
  170. fsl,pins = <
  171. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
  172. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  173. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  174. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  175. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  176. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  177. MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
  178. MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
  179. MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
  180. MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
  181. >;
  182. };
  183. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  184. fsl,pins = <
  185. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
  186. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
  187. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
  188. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
  189. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
  190. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
  191. MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
  192. MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
  193. MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
  194. MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
  195. >;
  196. };
  197. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  198. fsl,pins = <
  199. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
  200. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
  201. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
  202. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
  203. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
  204. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
  205. MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
  206. MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
  207. MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
  208. MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
  209. >;
  210. };
  211. pinctrl_enet1: enet1grp {
  212. fsl,pins = <
  213. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  214. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  215. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  216. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  217. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  218. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  219. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  220. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
  221. >;
  222. };
  223. pinctrl_enet2: enet2grp {
  224. fsl,pins = <
  225. MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
  226. MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
  227. MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
  228. MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
  229. MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
  230. MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
  231. MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
  232. MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
  233. MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
  234. MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
  235. >;
  236. };
  237. pinctrl_gpios: gpiosgrp {
  238. fsl,pins = <
  239. MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
  240. >;
  241. };
  242. };