soc.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/hab.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/syscounter.h>
  19. #include <asm/ptrace.h>
  20. #include <asm/armv8/mmu.h>
  21. #include <dm/uclass.h>
  22. #include <efi_loader.h>
  23. #include <env.h>
  24. #include <env_internal.h>
  25. #include <errno.h>
  26. #include <fdt_support.h>
  27. #include <fsl_wdog.h>
  28. #include <imx_sip.h>
  29. #include <linux/arm-smccc.h>
  30. #include <linux/bitops.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #if defined(CONFIG_IMX_HAB)
  33. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  34. .bank = 1,
  35. .word = 3,
  36. };
  37. #endif
  38. int timer_init(void)
  39. {
  40. #ifdef CONFIG_SPL_BUILD
  41. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  42. unsigned long freq = readl(&sctr->cntfid0);
  43. /* Update with accurate clock frequency */
  44. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  45. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  46. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  47. #endif
  48. gd->arch.tbl = 0;
  49. gd->arch.tbu = 0;
  50. return 0;
  51. }
  52. void enable_tzc380(void)
  53. {
  54. struct iomuxc_gpr_base_regs *gpr =
  55. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  56. /* Enable TZASC and lock setting */
  57. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  58. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  59. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  60. setbits_le32(&gpr->gpr[10], BIT(1));
  61. /*
  62. * set Region 0 attribute to allow secure and non-secure
  63. * read/write permission. Found some masters like usb dwc3
  64. * controllers can't work with secure memory.
  65. */
  66. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  67. }
  68. void set_wdog_reset(struct wdog_regs *wdog)
  69. {
  70. /*
  71. * Output WDOG_B signal to reset external pmic or POR_B decided by
  72. * the board design. Without external reset, the peripherals/DDR/
  73. * PMIC are not reset, that may cause system working abnormal.
  74. * WDZST bit is write-once only bit. Align this bit in kernel,
  75. * otherwise kernel code will have no chance to set this bit.
  76. */
  77. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  78. }
  79. static struct mm_region imx8m_mem_map[] = {
  80. {
  81. /* ROM */
  82. .virt = 0x0UL,
  83. .phys = 0x0UL,
  84. .size = 0x100000UL,
  85. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  86. PTE_BLOCK_OUTER_SHARE
  87. }, {
  88. /* CAAM */
  89. .virt = 0x100000UL,
  90. .phys = 0x100000UL,
  91. .size = 0x8000UL,
  92. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  93. PTE_BLOCK_NON_SHARE |
  94. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  95. }, {
  96. /* OCRAM_S */
  97. .virt = 0x180000UL,
  98. .phys = 0x180000UL,
  99. .size = 0x8000UL,
  100. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  101. PTE_BLOCK_OUTER_SHARE
  102. }, {
  103. /* TCM */
  104. .virt = 0x7C0000UL,
  105. .phys = 0x7C0000UL,
  106. .size = 0x80000UL,
  107. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  108. PTE_BLOCK_NON_SHARE |
  109. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  110. }, {
  111. /* OCRAM */
  112. .virt = 0x900000UL,
  113. .phys = 0x900000UL,
  114. .size = 0x200000UL,
  115. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  116. PTE_BLOCK_OUTER_SHARE
  117. }, {
  118. /* AIPS */
  119. .virt = 0xB00000UL,
  120. .phys = 0xB00000UL,
  121. .size = 0x3f500000UL,
  122. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  123. PTE_BLOCK_NON_SHARE |
  124. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  125. }, {
  126. /* DRAM1 */
  127. .virt = 0x40000000UL,
  128. .phys = 0x40000000UL,
  129. .size = PHYS_SDRAM_SIZE,
  130. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  131. PTE_BLOCK_OUTER_SHARE
  132. #ifdef PHYS_SDRAM_2_SIZE
  133. }, {
  134. /* DRAM2 */
  135. .virt = 0x100000000UL,
  136. .phys = 0x100000000UL,
  137. .size = PHYS_SDRAM_2_SIZE,
  138. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  139. PTE_BLOCK_OUTER_SHARE
  140. #endif
  141. }, {
  142. /* empty entrie to split table entry 5 if needed when TEEs are used */
  143. 0,
  144. }, {
  145. /* List terminator */
  146. 0,
  147. }
  148. };
  149. struct mm_region *mem_map = imx8m_mem_map;
  150. static unsigned int imx8m_find_dram_entry_in_mem_map(void)
  151. {
  152. int i;
  153. for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
  154. if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
  155. return i;
  156. hang(); /* Entry not found, this must never happen. */
  157. }
  158. void enable_caches(void)
  159. {
  160. /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
  161. if (rom_pointer[1]) {
  162. /*
  163. * TEE are loaded, So the ddr bank structures
  164. * have been modified update mmu table accordingly
  165. */
  166. int i = 0;
  167. /*
  168. * please make sure that entry initial value matches
  169. * imx8m_mem_map for DRAM1
  170. */
  171. int entry = imx8m_find_dram_entry_in_mem_map();
  172. u64 attrs = imx8m_mem_map[entry].attrs;
  173. while (i < CONFIG_NR_DRAM_BANKS &&
  174. entry < ARRAY_SIZE(imx8m_mem_map)) {
  175. if (gd->bd->bi_dram[i].start == 0)
  176. break;
  177. imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
  178. imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
  179. imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
  180. imx8m_mem_map[entry].attrs = attrs;
  181. debug("Added memory mapping (%d): %llx %llx\n", entry,
  182. imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
  183. i++; entry++;
  184. }
  185. }
  186. icache_enable();
  187. dcache_enable();
  188. }
  189. __weak int board_phys_sdram_size(phys_size_t *size)
  190. {
  191. if (!size)
  192. return -EINVAL;
  193. *size = PHYS_SDRAM_SIZE;
  194. return 0;
  195. }
  196. int dram_init(void)
  197. {
  198. unsigned int entry = imx8m_find_dram_entry_in_mem_map();
  199. phys_size_t sdram_size;
  200. int ret;
  201. ret = board_phys_sdram_size(&sdram_size);
  202. if (ret)
  203. return ret;
  204. /* rom_pointer[1] contains the size of TEE occupies */
  205. if (rom_pointer[1])
  206. gd->ram_size = sdram_size - rom_pointer[1];
  207. else
  208. gd->ram_size = sdram_size;
  209. /* also update the SDRAM size in the mem_map used externally */
  210. imx8m_mem_map[entry].size = sdram_size;
  211. #ifdef PHYS_SDRAM_2_SIZE
  212. gd->ram_size += PHYS_SDRAM_2_SIZE;
  213. #endif
  214. return 0;
  215. }
  216. int dram_init_banksize(void)
  217. {
  218. int bank = 0;
  219. int ret;
  220. phys_size_t sdram_size;
  221. ret = board_phys_sdram_size(&sdram_size);
  222. if (ret)
  223. return ret;
  224. gd->bd->bi_dram[bank].start = PHYS_SDRAM;
  225. if (rom_pointer[1]) {
  226. phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
  227. phys_size_t optee_size = (size_t)rom_pointer[1];
  228. gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
  229. if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
  230. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  231. puts("CONFIG_NR_DRAM_BANKS is not enough\n");
  232. return -1;
  233. }
  234. gd->bd->bi_dram[bank].start = optee_start + optee_size;
  235. gd->bd->bi_dram[bank].size = PHYS_SDRAM +
  236. sdram_size - gd->bd->bi_dram[bank].start;
  237. }
  238. } else {
  239. gd->bd->bi_dram[bank].size = sdram_size;
  240. }
  241. #ifdef PHYS_SDRAM_2_SIZE
  242. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  243. puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
  244. return -1;
  245. }
  246. gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
  247. gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
  248. #endif
  249. return 0;
  250. }
  251. phys_size_t get_effective_memsize(void)
  252. {
  253. /* return the first bank as effective memory */
  254. if (rom_pointer[1])
  255. return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
  256. #ifdef PHYS_SDRAM_2_SIZE
  257. return gd->ram_size - PHYS_SDRAM_2_SIZE;
  258. #else
  259. return gd->ram_size;
  260. #endif
  261. }
  262. static u32 get_cpu_variant_type(u32 type)
  263. {
  264. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  265. struct fuse_bank *bank = &ocotp->bank[1];
  266. struct fuse_bank1_regs *fuse =
  267. (struct fuse_bank1_regs *)bank->fuse_regs;
  268. u32 value = readl(&fuse->tester4);
  269. if (type == MXC_CPU_IMX8MQ) {
  270. if ((value & 0x3) == 0x2)
  271. return MXC_CPU_IMX8MD;
  272. else if (value & 0x200000)
  273. return MXC_CPU_IMX8MQL;
  274. } else if (type == MXC_CPU_IMX8MM) {
  275. switch (value & 0x3) {
  276. case 2:
  277. if (value & 0x1c0000)
  278. return MXC_CPU_IMX8MMDL;
  279. else
  280. return MXC_CPU_IMX8MMD;
  281. case 3:
  282. if (value & 0x1c0000)
  283. return MXC_CPU_IMX8MMSL;
  284. else
  285. return MXC_CPU_IMX8MMS;
  286. default:
  287. if (value & 0x1c0000)
  288. return MXC_CPU_IMX8MML;
  289. break;
  290. }
  291. } else if (type == MXC_CPU_IMX8MN) {
  292. switch (value & 0x3) {
  293. case 2:
  294. if (value & 0x1000000) {
  295. if (value & 0x10000000) /* MIPI DSI */
  296. return MXC_CPU_IMX8MNUD;
  297. else
  298. return MXC_CPU_IMX8MNDL;
  299. } else {
  300. return MXC_CPU_IMX8MND;
  301. }
  302. case 3:
  303. if (value & 0x1000000) {
  304. if (value & 0x10000000) /* MIPI DSI */
  305. return MXC_CPU_IMX8MNUS;
  306. else
  307. return MXC_CPU_IMX8MNSL;
  308. } else {
  309. return MXC_CPU_IMX8MNS;
  310. }
  311. default:
  312. if (value & 0x1000000) {
  313. if (value & 0x10000000) /* MIPI DSI */
  314. return MXC_CPU_IMX8MNUQ;
  315. else
  316. return MXC_CPU_IMX8MNL;
  317. }
  318. break;
  319. }
  320. } else if (type == MXC_CPU_IMX8MP) {
  321. u32 value0 = readl(&fuse->tester3);
  322. u32 flag = 0;
  323. if ((value0 & 0xc0000) == 0x80000)
  324. return MXC_CPU_IMX8MPD;
  325. /* vpu disabled */
  326. if ((value0 & 0x43000000) == 0x43000000)
  327. flag = 1;
  328. /* npu disabled*/
  329. if ((value & 0x8) == 0x8)
  330. flag |= (1 << 1);
  331. /* isp disabled */
  332. if ((value & 0x3) == 0x3)
  333. flag |= (1 << 2);
  334. switch (flag) {
  335. case 7:
  336. return MXC_CPU_IMX8MPL;
  337. case 2:
  338. return MXC_CPU_IMX8MP6;
  339. default:
  340. break;
  341. }
  342. }
  343. return type;
  344. }
  345. u32 get_cpu_rev(void)
  346. {
  347. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  348. u32 reg = readl(&ana_pll->digprog);
  349. u32 type = (reg >> 16) & 0xff;
  350. u32 major_low = (reg >> 8) & 0xff;
  351. u32 rom_version;
  352. reg &= 0xff;
  353. /* iMX8MP */
  354. if (major_low == 0x43) {
  355. type = get_cpu_variant_type(MXC_CPU_IMX8MP);
  356. } else if (major_low == 0x42) {
  357. /* iMX8MN */
  358. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  359. } else if (major_low == 0x41) {
  360. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  361. } else {
  362. if (reg == CHIP_REV_1_0) {
  363. /*
  364. * For B0 chip, the DIGPROG is not updated,
  365. * it is still TO1.0. we have to check ROM
  366. * version or OCOTP_READ_FUSE_DATA.
  367. * 0xff0055aa is magic number for B1.
  368. */
  369. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  370. /*
  371. * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
  372. * so have to check ROM to distinguish them
  373. */
  374. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  375. rom_version &= 0xff;
  376. if (rom_version == CHIP_REV_2_2)
  377. reg = CHIP_REV_2_2;
  378. else
  379. reg = CHIP_REV_2_1;
  380. } else {
  381. rom_version =
  382. readl((void __iomem *)ROM_VERSION_A0);
  383. if (rom_version != CHIP_REV_1_0) {
  384. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  385. rom_version &= 0xff;
  386. if (rom_version == CHIP_REV_2_0)
  387. reg = CHIP_REV_2_0;
  388. }
  389. }
  390. }
  391. type = get_cpu_variant_type(type);
  392. }
  393. return (type << 12) | reg;
  394. }
  395. static void imx_set_wdog_powerdown(bool enable)
  396. {
  397. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  398. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  399. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  400. /* Write to the PDE (Power Down Enable) bit */
  401. writew(enable, &wdog1->wmcr);
  402. writew(enable, &wdog2->wmcr);
  403. writew(enable, &wdog3->wmcr);
  404. }
  405. int arch_cpu_init_dm(void)
  406. {
  407. struct udevice *dev;
  408. int ret;
  409. if (CONFIG_IS_ENABLED(CLK)) {
  410. ret = uclass_get_device_by_name(UCLASS_CLK,
  411. "clock-controller@30380000",
  412. &dev);
  413. if (ret < 0) {
  414. printf("Failed to find clock node. Check device tree\n");
  415. return ret;
  416. }
  417. }
  418. return 0;
  419. }
  420. int arch_cpu_init(void)
  421. {
  422. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  423. /*
  424. * ROM might disable clock for SCTR,
  425. * enable the clock before timer_init.
  426. */
  427. if (IS_ENABLED(CONFIG_SPL_BUILD))
  428. clock_enable(CCGR_SCTR, 1);
  429. /*
  430. * Init timer at very early state, because sscg pll setting
  431. * will use it
  432. */
  433. timer_init();
  434. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  435. clock_init();
  436. imx_set_wdog_powerdown(false);
  437. if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
  438. is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
  439. is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
  440. /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
  441. struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
  442. struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
  443. struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
  444. struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
  445. writel(0x1, &pgc_core2->pgcr);
  446. writel(0x1, &pgc_core3->pgcr);
  447. if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
  448. writel(0x1, &pgc_core1->pgcr);
  449. writel(0xE, &gpc->cpu_pgc_dn_trg);
  450. } else {
  451. writel(0xC, &gpc->cpu_pgc_dn_trg);
  452. }
  453. }
  454. }
  455. if (is_imx8mq()) {
  456. clock_enable(CCGR_OCOTP, 1);
  457. if (readl(&ocotp->ctrl) & 0x200)
  458. writel(0x200, &ocotp->ctrl_clr);
  459. }
  460. return 0;
  461. }
  462. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  463. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  464. enum boot_device get_boot_device(void)
  465. {
  466. volatile gd_t *pgd = gd;
  467. int ret;
  468. u32 boot;
  469. u16 boot_type;
  470. u8 boot_instance;
  471. enum boot_device boot_dev = SD1_BOOT;
  472. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  473. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  474. gd = pgd;
  475. if (ret != ROM_API_OKAY) {
  476. puts("ROMAPI: failure at query_boot_info\n");
  477. return -1;
  478. }
  479. boot_type = boot >> 16;
  480. boot_instance = (boot >> 8) & 0xff;
  481. switch (boot_type) {
  482. case BT_DEV_TYPE_SD:
  483. boot_dev = boot_instance + SD1_BOOT;
  484. break;
  485. case BT_DEV_TYPE_MMC:
  486. boot_dev = boot_instance + MMC1_BOOT;
  487. break;
  488. case BT_DEV_TYPE_NAND:
  489. boot_dev = NAND_BOOT;
  490. break;
  491. case BT_DEV_TYPE_FLEXSPINOR:
  492. boot_dev = QSPI_BOOT;
  493. break;
  494. case BT_DEV_TYPE_USB:
  495. boot_dev = USB_BOOT;
  496. break;
  497. default:
  498. break;
  499. }
  500. return boot_dev;
  501. }
  502. #endif
  503. bool is_usb_boot(void)
  504. {
  505. return get_boot_device() == USB_BOOT;
  506. }
  507. #ifdef CONFIG_OF_SYSTEM_SETUP
  508. bool check_fdt_new_path(void *blob)
  509. {
  510. const char *soc_path = "/soc@0";
  511. int nodeoff;
  512. nodeoff = fdt_path_offset(blob, soc_path);
  513. if (nodeoff < 0)
  514. return false;
  515. return true;
  516. }
  517. static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
  518. {
  519. int i = 0;
  520. int rc;
  521. int nodeoff;
  522. const char *status = "disabled";
  523. for (i = 0; i < size_array; i++) {
  524. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  525. if (nodeoff < 0)
  526. continue; /* Not found, skip it */
  527. printf("Found %s node\n", nodes_path[i]);
  528. add_status:
  529. rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
  530. if (rc) {
  531. if (rc == -FDT_ERR_NOSPACE) {
  532. rc = fdt_increase_size(blob, 512);
  533. if (!rc)
  534. goto add_status;
  535. }
  536. printf("Unable to update property %s:%s, err=%s\n",
  537. nodes_path[i], "status", fdt_strerror(rc));
  538. } else {
  539. printf("Modify %s:%s disabled\n",
  540. nodes_path[i], "status");
  541. }
  542. }
  543. return 0;
  544. }
  545. #ifdef CONFIG_IMX8MQ
  546. bool check_dcss_fused(void)
  547. {
  548. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  549. struct fuse_bank *bank = &ocotp->bank[1];
  550. struct fuse_bank1_regs *fuse =
  551. (struct fuse_bank1_regs *)bank->fuse_regs;
  552. u32 value = readl(&fuse->tester4);
  553. if (value & 0x4000000)
  554. return true;
  555. return false;
  556. }
  557. static int disable_mipi_dsi_nodes(void *blob)
  558. {
  559. static const char * const nodes_path[] = {
  560. "/mipi_dsi@30A00000",
  561. "/mipi_dsi_bridge@30A00000",
  562. "/dsi_phy@30A00300",
  563. "/soc@0/bus@30800000/mipi_dsi@30a00000",
  564. "/soc@0/bus@30800000/dphy@30a00300",
  565. "/soc@0/bus@30800000/mipi-dsi@30a00000",
  566. };
  567. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  568. }
  569. static int disable_dcss_nodes(void *blob)
  570. {
  571. static const char * const nodes_path[] = {
  572. "/dcss@0x32e00000",
  573. "/dcss@32e00000",
  574. "/hdmi@32c00000",
  575. "/hdmi_cec@32c33800",
  576. "/hdmi_drm@32c00000",
  577. "/display-subsystem",
  578. "/sound-hdmi",
  579. "/sound-hdmi-arc",
  580. "/soc@0/bus@32c00000/display-controller@32e00000",
  581. "/soc@0/bus@32c00000/hdmi@32c00000",
  582. };
  583. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  584. }
  585. static int check_mipi_dsi_nodes(void *blob)
  586. {
  587. static const char * const lcdif_path[] = {
  588. "/lcdif@30320000",
  589. "/soc@0/bus@30000000/lcdif@30320000",
  590. "/soc@0/bus@30000000/lcd-controller@30320000"
  591. };
  592. static const char * const mipi_dsi_path[] = {
  593. "/mipi_dsi@30A00000",
  594. "/soc@0/bus@30800000/mipi_dsi@30a00000"
  595. };
  596. static const char * const lcdif_ep_path[] = {
  597. "/lcdif@30320000/port@0/mipi-dsi-endpoint",
  598. "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
  599. "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
  600. };
  601. static const char * const mipi_dsi_ep_path[] = {
  602. "/mipi_dsi@30A00000/port@1/endpoint",
  603. "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
  604. "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
  605. };
  606. int lookup_node;
  607. int nodeoff;
  608. bool new_path = check_fdt_new_path(blob);
  609. int i = new_path ? 1 : 0;
  610. nodeoff = fdt_path_offset(blob, lcdif_path[i]);
  611. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
  612. /*
  613. * If can't find lcdif node or lcdif node is disabled,
  614. * then disable all mipi dsi, since they only can input
  615. * from DCSS
  616. */
  617. return disable_mipi_dsi_nodes(blob);
  618. }
  619. nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
  620. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
  621. return 0;
  622. nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
  623. if (nodeoff < 0) {
  624. /*
  625. * If can't find lcdif endpoint, then disable all mipi dsi,
  626. * since they only can input from DCSS
  627. */
  628. return disable_mipi_dsi_nodes(blob);
  629. }
  630. lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
  631. nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
  632. if (nodeoff > 0 && nodeoff == lookup_node)
  633. return 0;
  634. return disable_mipi_dsi_nodes(blob);
  635. }
  636. #endif
  637. int disable_vpu_nodes(void *blob)
  638. {
  639. static const char * const nodes_path_8mq[] = {
  640. "/vpu@38300000",
  641. "/soc@0/vpu@38300000"
  642. };
  643. static const char * const nodes_path_8mm[] = {
  644. "/vpu_g1@38300000",
  645. "/vpu_g2@38310000",
  646. "/vpu_h1@38320000"
  647. };
  648. static const char * const nodes_path_8mp[] = {
  649. "/vpu_g1@38300000",
  650. "/vpu_g2@38310000",
  651. "/vpu_vc8000e@38320000"
  652. };
  653. if (is_imx8mq())
  654. return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
  655. else if (is_imx8mm())
  656. return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
  657. else if (is_imx8mp())
  658. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  659. else
  660. return -EPERM;
  661. }
  662. #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
  663. static int low_drive_gpu_freq(void *blob)
  664. {
  665. static const char *nodes_path_8mn[] = {
  666. "/gpu@38000000",
  667. "/soc@0/gpu@38000000"
  668. };
  669. int nodeoff, cnt, i;
  670. u32 assignedclks[7];
  671. nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
  672. if (nodeoff < 0)
  673. return nodeoff;
  674. cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
  675. if (cnt < 0)
  676. return cnt;
  677. if (cnt != 7)
  678. printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
  679. assignedclks[cnt - 1] = 200000000;
  680. assignedclks[cnt - 2] = 200000000;
  681. for (i = 0; i < cnt; i++) {
  682. debug("<%u>, ", assignedclks[i]);
  683. assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
  684. }
  685. debug("\n");
  686. return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
  687. }
  688. #endif
  689. int disable_gpu_nodes(void *blob)
  690. {
  691. static const char * const nodes_path_8mn[] = {
  692. "/gpu@38000000",
  693. "/soc@/gpu@38000000"
  694. };
  695. return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
  696. }
  697. int disable_npu_nodes(void *blob)
  698. {
  699. static const char * const nodes_path_8mp[] = {
  700. "/vipsi@38500000"
  701. };
  702. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  703. }
  704. int disable_isp_nodes(void *blob)
  705. {
  706. static const char * const nodes_path_8mp[] = {
  707. "/soc@0/bus@32c00000/camera/isp@32e10000",
  708. "/soc@0/bus@32c00000/camera/isp@32e20000"
  709. };
  710. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  711. }
  712. int disable_dsp_nodes(void *blob)
  713. {
  714. static const char * const nodes_path_8mp[] = {
  715. "/dsp@3b6e8000"
  716. };
  717. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  718. }
  719. static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
  720. {
  721. static const char * const thermal_path[] = {
  722. "/thermal-zones/cpu-thermal/cooling-maps/map0"
  723. };
  724. int nodeoff, cnt, i, ret, j;
  725. u32 cooling_dev[12];
  726. for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
  727. nodeoff = fdt_path_offset(blob, thermal_path[i]);
  728. if (nodeoff < 0)
  729. continue; /* Not found, skip it */
  730. cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
  731. if (cnt < 0)
  732. continue;
  733. if (cnt != 12)
  734. printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
  735. for (j = 0; j < cnt; j++)
  736. cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
  737. ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
  738. sizeof(u32) * (12 - disabled_cores * 3));
  739. if (ret < 0) {
  740. printf("Warning: %s, cooling-device setprop failed %d\n",
  741. thermal_path[i], ret);
  742. continue;
  743. }
  744. printf("Update node %s, cooling-device prop\n", thermal_path[i]);
  745. }
  746. }
  747. static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
  748. {
  749. static const char * const pmu_path[] = {
  750. "/pmu"
  751. };
  752. int nodeoff, cnt, i, ret, j;
  753. u32 irq_affinity[4];
  754. for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
  755. nodeoff = fdt_path_offset(blob, pmu_path[i]);
  756. if (nodeoff < 0)
  757. continue; /* Not found, skip it */
  758. cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
  759. irq_affinity, 4);
  760. if (cnt < 0)
  761. continue;
  762. if (cnt != 4)
  763. printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
  764. for (j = 0; j < cnt; j++)
  765. irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
  766. ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
  767. sizeof(u32) * (4 - disabled_cores));
  768. if (ret < 0) {
  769. printf("Warning: %s, interrupt-affinity setprop failed %d\n",
  770. pmu_path[i], ret);
  771. continue;
  772. }
  773. printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
  774. }
  775. }
  776. static int disable_cpu_nodes(void *blob, u32 disabled_cores)
  777. {
  778. static const char * const nodes_path[] = {
  779. "/cpus/cpu@1",
  780. "/cpus/cpu@2",
  781. "/cpus/cpu@3",
  782. };
  783. u32 i = 0;
  784. int rc;
  785. int nodeoff;
  786. if (disabled_cores > 3)
  787. return -EINVAL;
  788. i = 3 - disabled_cores;
  789. for (; i < 3; i++) {
  790. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  791. if (nodeoff < 0)
  792. continue; /* Not found, skip it */
  793. debug("Found %s node\n", nodes_path[i]);
  794. rc = fdt_del_node(blob, nodeoff);
  795. if (rc < 0) {
  796. printf("Unable to delete node %s, err=%s\n",
  797. nodes_path[i], fdt_strerror(rc));
  798. } else {
  799. printf("Delete node %s\n", nodes_path[i]);
  800. }
  801. }
  802. disable_thermal_cpu_nodes(blob, disabled_cores);
  803. disable_pmu_cpu_nodes(blob, disabled_cores);
  804. return 0;
  805. }
  806. int ft_system_setup(void *blob, struct bd_info *bd)
  807. {
  808. #ifdef CONFIG_IMX8MQ
  809. int i = 0;
  810. int rc;
  811. int nodeoff;
  812. if (get_boot_device() == USB_BOOT) {
  813. disable_dcss_nodes(blob);
  814. bool new_path = check_fdt_new_path(blob);
  815. int v = new_path ? 1 : 0;
  816. static const char * const usb_dwc3_path[] = {
  817. "/usb@38100000/dwc3",
  818. "/soc@0/usb@38100000"
  819. };
  820. nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
  821. if (nodeoff >= 0) {
  822. const char *speed = "high-speed";
  823. printf("Found %s node\n", usb_dwc3_path[v]);
  824. usb_modify_speed:
  825. rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
  826. if (rc) {
  827. if (rc == -FDT_ERR_NOSPACE) {
  828. rc = fdt_increase_size(blob, 512);
  829. if (!rc)
  830. goto usb_modify_speed;
  831. }
  832. printf("Unable to set property %s:%s, err=%s\n",
  833. usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
  834. } else {
  835. printf("Modify %s:%s = %s\n",
  836. usb_dwc3_path[v], "maximum-speed", speed);
  837. }
  838. } else {
  839. printf("Can't found %s node\n", usb_dwc3_path[v]);
  840. }
  841. }
  842. /* Disable the CPU idle for A0 chip since the HW does not support it */
  843. if (is_soc_rev(CHIP_REV_1_0)) {
  844. static const char * const nodes_path[] = {
  845. "/cpus/cpu@0",
  846. "/cpus/cpu@1",
  847. "/cpus/cpu@2",
  848. "/cpus/cpu@3",
  849. };
  850. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  851. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  852. if (nodeoff < 0)
  853. continue; /* Not found, skip it */
  854. debug("Found %s node\n", nodes_path[i]);
  855. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  856. if (rc == -FDT_ERR_NOTFOUND)
  857. continue;
  858. if (rc) {
  859. printf("Unable to update property %s:%s, err=%s\n",
  860. nodes_path[i], "status", fdt_strerror(rc));
  861. return rc;
  862. }
  863. debug("Remove %s:%s\n", nodes_path[i],
  864. "cpu-idle-states");
  865. }
  866. }
  867. if (is_imx8mql()) {
  868. disable_vpu_nodes(blob);
  869. if (check_dcss_fused()) {
  870. printf("DCSS is fused\n");
  871. disable_dcss_nodes(blob);
  872. check_mipi_dsi_nodes(blob);
  873. }
  874. }
  875. if (is_imx8md())
  876. disable_cpu_nodes(blob, 2);
  877. #elif defined(CONFIG_IMX8MM)
  878. if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
  879. disable_vpu_nodes(blob);
  880. if (is_imx8mmd() || is_imx8mmdl())
  881. disable_cpu_nodes(blob, 2);
  882. else if (is_imx8mms() || is_imx8mmsl())
  883. disable_cpu_nodes(blob, 3);
  884. #elif defined(CONFIG_IMX8MN)
  885. if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
  886. disable_gpu_nodes(blob);
  887. #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
  888. else {
  889. int ldm_gpu = low_drive_gpu_freq(blob);
  890. if (ldm_gpu < 0)
  891. printf("Update GPU node assigned-clock-rates failed\n");
  892. else
  893. printf("Update GPU node assigned-clock-rates ok\n");
  894. }
  895. #endif
  896. if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
  897. disable_cpu_nodes(blob, 2);
  898. else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
  899. disable_cpu_nodes(blob, 3);
  900. #elif defined(CONFIG_IMX8MP)
  901. if (is_imx8mpl())
  902. disable_vpu_nodes(blob);
  903. if (is_imx8mpl() || is_imx8mp6())
  904. disable_npu_nodes(blob);
  905. if (is_imx8mpl())
  906. disable_isp_nodes(blob);
  907. if (is_imx8mpl() || is_imx8mp6())
  908. disable_dsp_nodes(blob);
  909. if (is_imx8mpd())
  910. disable_cpu_nodes(blob, 2);
  911. #endif
  912. return 0;
  913. }
  914. #endif
  915. #if !CONFIG_IS_ENABLED(SYSRESET)
  916. void reset_cpu(void)
  917. {
  918. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  919. /* Clear WDA to trigger WDOG_B immediately */
  920. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  921. while (1) {
  922. /*
  923. * spin for .5 seconds before reset
  924. */
  925. }
  926. }
  927. #endif
  928. #if defined(CONFIG_ARCH_MISC_INIT)
  929. static void acquire_buildinfo(void)
  930. {
  931. u64 atf_commit = 0;
  932. struct arm_smccc_res res;
  933. /* Get ARM Trusted Firmware commit id */
  934. arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
  935. 0, 0, 0, 0, 0, 0, &res);
  936. atf_commit = res.a0;
  937. if (atf_commit == 0xffffffff) {
  938. debug("ATF does not support build info\n");
  939. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  940. }
  941. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  942. }
  943. int arch_misc_init(void)
  944. {
  945. acquire_buildinfo();
  946. return 0;
  947. }
  948. #endif
  949. void imx_tmu_arch_init(void *reg_base)
  950. {
  951. if (is_imx8mm() || is_imx8mn()) {
  952. /* Load TCALIV and TASR from fuses */
  953. struct ocotp_regs *ocotp =
  954. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  955. struct fuse_bank *bank = &ocotp->bank[3];
  956. struct fuse_bank3_regs *fuse =
  957. (struct fuse_bank3_regs *)bank->fuse_regs;
  958. u32 tca_rt, tca_hr, tca_en;
  959. u32 buf_vref, buf_slope;
  960. tca_rt = fuse->ana0 & 0xFF;
  961. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  962. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  963. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  964. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  965. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  966. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  967. (ulong)reg_base + 0x30);
  968. }
  969. #ifdef CONFIG_IMX8MP
  970. /* Load TCALIV0/1/m40 and TRIM from fuses */
  971. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  972. struct fuse_bank *bank = &ocotp->bank[38];
  973. struct fuse_bank38_regs *fuse =
  974. (struct fuse_bank38_regs *)bank->fuse_regs;
  975. struct fuse_bank *bank2 = &ocotp->bank[39];
  976. struct fuse_bank39_regs *fuse2 =
  977. (struct fuse_bank39_regs *)bank2->fuse_regs;
  978. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  979. u32 reg;
  980. u32 tca40[2], tca25[2], tca105[2];
  981. /* For blank sample */
  982. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  983. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  984. /* Use a default 25C binary codes */
  985. tca25[0] = 1596;
  986. tca25[1] = 1596;
  987. writel(tca25[0], (ulong)reg_base + 0x30);
  988. writel(tca25[1], (ulong)reg_base + 0x34);
  989. return;
  990. }
  991. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  992. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  993. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  994. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  995. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  996. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  997. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  998. writel(reg, (ulong)reg_base + 0x3c);
  999. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  1000. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  1001. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  1002. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  1003. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  1004. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  1005. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  1006. /* use 25c for 1p calibration */
  1007. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  1008. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  1009. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  1010. #endif
  1011. }
  1012. #if defined(CONFIG_SPL_BUILD)
  1013. #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
  1014. bool serror_need_skip = true;
  1015. void do_error(struct pt_regs *pt_regs, unsigned int esr)
  1016. {
  1017. /*
  1018. * If stack is still in ROM reserved OCRAM not switch to SPL,
  1019. * it is the ROM SError
  1020. */
  1021. ulong sp;
  1022. asm volatile("mov %0, sp" : "=r"(sp) : );
  1023. if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
  1024. /* Check for ERR050342, imx8mq HDCP enabled parts */
  1025. if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
  1026. serror_need_skip = false;
  1027. return; /* Do nothing skip the SError in ROM */
  1028. }
  1029. /* Check for ERR050350, field return mode for imx8mq, mm and mn */
  1030. if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
  1031. serror_need_skip = false;
  1032. return; /* Do nothing skip the SError in ROM */
  1033. }
  1034. }
  1035. efi_restore_gd();
  1036. printf("\"Error\" handler, esr 0x%08x\n", esr);
  1037. show_regs(pt_regs);
  1038. panic("Resetting CPU ...\n");
  1039. }
  1040. #endif
  1041. #endif
  1042. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  1043. enum env_location env_get_location(enum env_operation op, int prio)
  1044. {
  1045. enum boot_device dev = get_boot_device();
  1046. enum env_location env_loc = ENVL_UNKNOWN;
  1047. if (prio)
  1048. return env_loc;
  1049. switch (dev) {
  1050. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  1051. case QSPI_BOOT:
  1052. env_loc = ENVL_SPI_FLASH;
  1053. break;
  1054. #endif
  1055. #ifdef CONFIG_ENV_IS_IN_NAND
  1056. case NAND_BOOT:
  1057. env_loc = ENVL_NAND;
  1058. break;
  1059. #endif
  1060. #ifdef CONFIG_ENV_IS_IN_MMC
  1061. case SD1_BOOT:
  1062. case SD2_BOOT:
  1063. case SD3_BOOT:
  1064. case MMC1_BOOT:
  1065. case MMC2_BOOT:
  1066. case MMC3_BOOT:
  1067. env_loc = ENVL_MMC;
  1068. break;
  1069. #endif
  1070. default:
  1071. #if defined(CONFIG_ENV_IS_NOWHERE)
  1072. env_loc = ENVL_NOWHERE;
  1073. #endif
  1074. break;
  1075. }
  1076. return env_loc;
  1077. }
  1078. #ifndef ENV_IS_EMBEDDED
  1079. long long env_get_offset(long long defautl_offset)
  1080. {
  1081. enum boot_device dev = get_boot_device();
  1082. switch (dev) {
  1083. case NAND_BOOT:
  1084. return (60 << 20); /* 60MB offset for NAND */
  1085. default:
  1086. break;
  1087. }
  1088. return defautl_offset;
  1089. }
  1090. #endif
  1091. #endif