cpu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <bootm.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <linux/errno.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <imx_thermal.h>
  23. #include <ipu_pixfmt.h>
  24. #include <thermal.h>
  25. #include <sata.h>
  26. #include <dm/device-internal.h>
  27. #include <dm/uclass-internal.h>
  28. #ifdef CONFIG_FSL_ESDHC_IMX
  29. #include <fsl_esdhc_imx.h>
  30. #endif
  31. static u32 reset_cause = -1;
  32. u32 get_imx_reset_cause(void)
  33. {
  34. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  35. if (reset_cause == -1) {
  36. reset_cause = readl(&src_regs->srsr);
  37. /* preserve the value for U-Boot proper */
  38. #if !defined(CONFIG_SPL_BUILD)
  39. writel(reset_cause, &src_regs->srsr);
  40. #endif
  41. }
  42. return reset_cause;
  43. }
  44. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  45. static char *get_reset_cause(void)
  46. {
  47. switch (get_imx_reset_cause()) {
  48. case 0x00001:
  49. case 0x00011:
  50. return "POR";
  51. case 0x00004:
  52. return "CSU";
  53. case 0x00008:
  54. return "IPP USER";
  55. case 0x00010:
  56. #ifdef CONFIG_MX7
  57. return "WDOG1";
  58. #else
  59. return "WDOG";
  60. #endif
  61. case 0x00020:
  62. return "JTAG HIGH-Z";
  63. case 0x00040:
  64. return "JTAG SW";
  65. case 0x00080:
  66. return "WDOG3";
  67. #ifdef CONFIG_MX7
  68. case 0x00100:
  69. return "WDOG4";
  70. case 0x00200:
  71. return "TEMPSENSE";
  72. #elif defined(CONFIG_IMX8M)
  73. case 0x00100:
  74. return "WDOG2";
  75. case 0x00200:
  76. return "TEMPSENSE";
  77. #else
  78. case 0x00100:
  79. return "TEMPSENSE";
  80. case 0x10000:
  81. return "WARM BOOT";
  82. #endif
  83. default:
  84. return "unknown reset";
  85. }
  86. }
  87. #endif
  88. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  89. const char *get_imx_type(u32 imxtype)
  90. {
  91. switch (imxtype) {
  92. case MXC_CPU_IMX8MP:
  93. return "8MP[8]"; /* Quad-core version of the imx8mp */
  94. case MXC_CPU_IMX8MPD:
  95. return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
  96. case MXC_CPU_IMX8MPL:
  97. return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
  98. case MXC_CPU_IMX8MP6:
  99. return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
  100. case MXC_CPU_IMX8MN:
  101. return "8MNano Quad"; /* Quad-core version */
  102. case MXC_CPU_IMX8MND:
  103. return "8MNano Dual"; /* Dual-core version */
  104. case MXC_CPU_IMX8MNS:
  105. return "8MNano Solo"; /* Single-core version */
  106. case MXC_CPU_IMX8MNL:
  107. return "8MNano QuadLite"; /* Quad-core Lite version */
  108. case MXC_CPU_IMX8MNDL:
  109. return "8MNano DualLite"; /* Dual-core Lite version */
  110. case MXC_CPU_IMX8MNSL:
  111. return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
  112. case MXC_CPU_IMX8MNUQ:
  113. return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
  114. case MXC_CPU_IMX8MNUD:
  115. return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
  116. case MXC_CPU_IMX8MNUS:
  117. return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
  118. case MXC_CPU_IMX8MM:
  119. return "8MMQ"; /* Quad-core version of the imx8mm */
  120. case MXC_CPU_IMX8MML:
  121. return "8MMQL"; /* Quad-core Lite version of the imx8mm */
  122. case MXC_CPU_IMX8MMD:
  123. return "8MMD"; /* Dual-core version of the imx8mm */
  124. case MXC_CPU_IMX8MMDL:
  125. return "8MMDL"; /* Dual-core Lite version of the imx8mm */
  126. case MXC_CPU_IMX8MMS:
  127. return "8MMS"; /* Single-core version of the imx8mm */
  128. case MXC_CPU_IMX8MMSL:
  129. return "8MMSL"; /* Single-core Lite version of the imx8mm */
  130. case MXC_CPU_IMX8MQ:
  131. return "8MQ"; /* Quad-core version of the imx8mq */
  132. case MXC_CPU_IMX8MQL:
  133. return "8MQLite"; /* Quad-core Lite version of the imx8mq */
  134. case MXC_CPU_IMX8MD:
  135. return "8MD"; /* Dual-core version of the imx8mq */
  136. case MXC_CPU_MX7S:
  137. return "7S"; /* Single-core version of the mx7 */
  138. case MXC_CPU_MX7D:
  139. return "7D"; /* Dual-core version of the mx7 */
  140. case MXC_CPU_MX6QP:
  141. return "6QP"; /* Quad-Plus version of the mx6 */
  142. case MXC_CPU_MX6DP:
  143. return "6DP"; /* Dual-Plus version of the mx6 */
  144. case MXC_CPU_MX6Q:
  145. return "6Q"; /* Quad-core version of the mx6 */
  146. case MXC_CPU_MX6D:
  147. return "6D"; /* Dual-core version of the mx6 */
  148. case MXC_CPU_MX6DL:
  149. return "6DL"; /* Dual Lite version of the mx6 */
  150. case MXC_CPU_MX6SOLO:
  151. return "6SOLO"; /* Solo version of the mx6 */
  152. case MXC_CPU_MX6SL:
  153. return "6SL"; /* Solo-Lite version of the mx6 */
  154. case MXC_CPU_MX6SLL:
  155. return "6SLL"; /* SLL version of the mx6 */
  156. case MXC_CPU_MX6SX:
  157. return "6SX"; /* SoloX version of the mx6 */
  158. case MXC_CPU_MX6UL:
  159. return "6UL"; /* Ultra-Lite version of the mx6 */
  160. case MXC_CPU_MX6ULL:
  161. return "6ULL"; /* ULL version of the mx6 */
  162. case MXC_CPU_MX6ULZ:
  163. return "6ULZ"; /* ULZ version of the mx6 */
  164. case MXC_CPU_MX51:
  165. return "51";
  166. case MXC_CPU_MX53:
  167. return "53";
  168. default:
  169. return "??";
  170. }
  171. }
  172. int print_cpuinfo(void)
  173. {
  174. u32 cpurev;
  175. __maybe_unused u32 max_freq;
  176. cpurev = get_cpu_rev();
  177. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  178. struct udevice *thermal_dev;
  179. int cpu_tmp, minc, maxc, ret;
  180. printf("CPU: Freescale i.MX%s rev%d.%d",
  181. get_imx_type((cpurev & 0x1FF000) >> 12),
  182. (cpurev & 0x000F0) >> 4,
  183. (cpurev & 0x0000F) >> 0);
  184. max_freq = get_cpu_speed_grade_hz();
  185. if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
  186. printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  187. } else {
  188. printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
  189. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  190. }
  191. #else
  192. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  193. get_imx_type((cpurev & 0x1FF000) >> 12),
  194. (cpurev & 0x000F0) >> 4,
  195. (cpurev & 0x0000F) >> 0,
  196. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  197. #endif
  198. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  199. puts("CPU: ");
  200. switch (get_cpu_temp_grade(&minc, &maxc)) {
  201. case TEMP_AUTOMOTIVE:
  202. puts("Automotive temperature grade ");
  203. break;
  204. case TEMP_INDUSTRIAL:
  205. puts("Industrial temperature grade ");
  206. break;
  207. case TEMP_EXTCOMMERCIAL:
  208. puts("Extended Commercial temperature grade ");
  209. break;
  210. default:
  211. puts("Commercial temperature grade ");
  212. break;
  213. }
  214. printf("(%dC to %dC)", minc, maxc);
  215. ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  216. if (!ret) {
  217. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  218. if (!ret)
  219. printf(" at %dC", cpu_tmp);
  220. else
  221. debug(" - invalid sensor data\n");
  222. } else {
  223. debug(" - invalid sensor device\n");
  224. }
  225. puts("\n");
  226. #endif
  227. printf("Reset cause: %s\n", get_reset_cause());
  228. return 0;
  229. }
  230. #endif
  231. int cpu_eth_init(struct bd_info *bis)
  232. {
  233. int rc = -ENODEV;
  234. #if defined(CONFIG_FEC_MXC)
  235. rc = fecmxc_initialize(bis);
  236. #endif
  237. return rc;
  238. }
  239. #ifdef CONFIG_FSL_ESDHC_IMX
  240. /*
  241. * Initializes on-chip MMC controllers.
  242. * to override, implement board_mmc_init()
  243. */
  244. int cpu_mmc_init(struct bd_info *bis)
  245. {
  246. return fsl_esdhc_mmc_init(bis);
  247. }
  248. #endif
  249. #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
  250. u32 get_ahb_clk(void)
  251. {
  252. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  253. u32 reg, ahb_podf;
  254. reg = __raw_readl(&imx_ccm->cbcdr);
  255. reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
  256. ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
  257. return get_periph_clk() / (ahb_podf + 1);
  258. }
  259. #endif
  260. void arch_preboot_os(void)
  261. {
  262. #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
  263. imx_pcie_remove();
  264. #endif
  265. #if defined(CONFIG_IMX_AHCI)
  266. struct udevice *dev;
  267. int rc;
  268. rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
  269. if (!rc && dev) {
  270. rc = device_remove(dev, DM_REMOVE_NORMAL);
  271. if (rc)
  272. printf("Cannot remove SATA device '%s' (err=%d)\n",
  273. dev->name, rc);
  274. }
  275. #endif
  276. #if defined(CONFIG_SATA)
  277. if (!is_mx6sdl()) {
  278. sata_remove(0);
  279. #if defined(CONFIG_MX6)
  280. disable_sata_clock();
  281. #endif
  282. }
  283. #endif
  284. #if defined(CONFIG_VIDEO_IPUV3)
  285. /* disable video before launching O/S */
  286. ipuv3_fb_shutdown();
  287. #endif
  288. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  289. lcdif_power_down();
  290. #endif
  291. }
  292. #ifndef CONFIG_IMX8M
  293. void set_chipselect_size(int const cs_size)
  294. {
  295. unsigned int reg;
  296. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  297. reg = readl(&iomuxc_regs->gpr[1]);
  298. switch (cs_size) {
  299. case CS0_128:
  300. reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  301. reg |= 0x5;
  302. break;
  303. case CS0_64M_CS1_64M:
  304. reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  305. reg |= 0x1B;
  306. break;
  307. case CS0_64M_CS1_32M_CS2_32M:
  308. reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  309. reg |= 0x4B;
  310. break;
  311. case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  312. reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  313. reg |= 0x249;
  314. break;
  315. default:
  316. printf("Unknown chip select size: %d\n", cs_size);
  317. break;
  318. }
  319. writel(reg, &iomuxc_regs->gpr[1]);
  320. }
  321. #endif
  322. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
  323. /*
  324. * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  325. * defines a 2-bit SPEED_GRADING
  326. */
  327. #define OCOTP_TESTER3_SPEED_SHIFT 8
  328. enum cpu_speed {
  329. OCOTP_TESTER3_SPEED_GRADE0,
  330. OCOTP_TESTER3_SPEED_GRADE1,
  331. OCOTP_TESTER3_SPEED_GRADE2,
  332. OCOTP_TESTER3_SPEED_GRADE3,
  333. OCOTP_TESTER3_SPEED_GRADE4,
  334. };
  335. u32 get_cpu_speed_grade_hz(void)
  336. {
  337. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  338. struct fuse_bank *bank = &ocotp->bank[1];
  339. struct fuse_bank1_regs *fuse =
  340. (struct fuse_bank1_regs *)bank->fuse_regs;
  341. uint32_t val;
  342. val = readl(&fuse->tester3);
  343. val >>= OCOTP_TESTER3_SPEED_SHIFT;
  344. if (is_imx8mn() || is_imx8mp()) {
  345. val &= 0xf;
  346. return 2300000000 - val * 100000000;
  347. }
  348. if (is_imx8mm())
  349. val &= 0x7;
  350. else
  351. val &= 0x3;
  352. switch(val) {
  353. case OCOTP_TESTER3_SPEED_GRADE0:
  354. return 800000000;
  355. case OCOTP_TESTER3_SPEED_GRADE1:
  356. return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
  357. case OCOTP_TESTER3_SPEED_GRADE2:
  358. return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
  359. case OCOTP_TESTER3_SPEED_GRADE3:
  360. return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
  361. case OCOTP_TESTER3_SPEED_GRADE4:
  362. return 2000000000;
  363. }
  364. return 0;
  365. }
  366. /*
  367. * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
  368. * defines a 2-bit SPEED_GRADING
  369. */
  370. #define OCOTP_TESTER3_TEMP_SHIFT 6
  371. /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
  372. #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
  373. u32 get_cpu_temp_grade(int *minc, int *maxc)
  374. {
  375. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  376. struct fuse_bank *bank = &ocotp->bank[1];
  377. struct fuse_bank1_regs *fuse =
  378. (struct fuse_bank1_regs *)bank->fuse_regs;
  379. uint32_t val;
  380. val = readl(&fuse->tester3);
  381. if (is_imx8mp())
  382. val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
  383. else
  384. val >>= OCOTP_TESTER3_TEMP_SHIFT;
  385. val &= 0x3;
  386. if (minc && maxc) {
  387. if (val == TEMP_AUTOMOTIVE) {
  388. *minc = -40;
  389. *maxc = 125;
  390. } else if (val == TEMP_INDUSTRIAL) {
  391. *minc = -40;
  392. *maxc = 105;
  393. } else if (val == TEMP_EXTCOMMERCIAL) {
  394. *minc = -20;
  395. *maxc = 105;
  396. } else {
  397. *minc = 0;
  398. *maxc = 95;
  399. }
  400. }
  401. return val;
  402. }
  403. #endif
  404. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
  405. enum boot_device get_boot_device(void)
  406. {
  407. struct bootrom_sw_info **p =
  408. (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
  409. enum boot_device boot_dev = SD1_BOOT;
  410. u8 boot_type = (*p)->boot_dev_type;
  411. u8 boot_instance = (*p)->boot_dev_instance;
  412. switch (boot_type) {
  413. case BOOT_TYPE_SD:
  414. boot_dev = boot_instance + SD1_BOOT;
  415. break;
  416. case BOOT_TYPE_MMC:
  417. boot_dev = boot_instance + MMC1_BOOT;
  418. break;
  419. case BOOT_TYPE_NAND:
  420. boot_dev = NAND_BOOT;
  421. break;
  422. case BOOT_TYPE_QSPI:
  423. boot_dev = QSPI_BOOT;
  424. break;
  425. case BOOT_TYPE_WEIM:
  426. boot_dev = WEIM_NOR_BOOT;
  427. break;
  428. case BOOT_TYPE_SPINOR:
  429. boot_dev = SPI_NOR_BOOT;
  430. break;
  431. case BOOT_TYPE_USB:
  432. boot_dev = USB_BOOT;
  433. break;
  434. default:
  435. #ifdef CONFIG_IMX8M
  436. if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
  437. boot_dev = QSPI_BOOT;
  438. #endif
  439. break;
  440. }
  441. return boot_dev;
  442. }
  443. #endif
  444. #ifdef CONFIG_NXP_BOARD_REVISION
  445. int nxp_board_rev(void)
  446. {
  447. /*
  448. * Get Board ID information from OCOTP_GP1[15:8]
  449. * RevA: 0x1
  450. * RevB: 0x2
  451. * RevC: 0x3
  452. */
  453. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  454. struct fuse_bank *bank = &ocotp->bank[4];
  455. struct fuse_bank4_regs *fuse =
  456. (struct fuse_bank4_regs *)bank->fuse_regs;
  457. return (readl(&fuse->gp1) >> 8 & 0x0F);
  458. }
  459. char nxp_board_rev_string(void)
  460. {
  461. const char *rev = "A";
  462. return (*rev + nxp_board_rev() - 1);
  463. }
  464. #endif