sys_proto.h 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009
  4. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  5. */
  6. #ifndef _SYS_PROTO_H_
  7. #define _SYS_PROTO_H_
  8. #include <asm/io.h>
  9. #include <asm/mach-imx/regs-common.h>
  10. #include <asm/mach-imx/module_fuse.h>
  11. #include <linux/bitops.h>
  12. #include "../arch-imx/cpu.h"
  13. struct bd_info;
  14. #define soc_rev() (get_cpu_rev() & 0xFF)
  15. #define is_soc_rev(rev) (soc_rev() == rev)
  16. /* returns MXC_CPU_ value */
  17. #define cpu_type(rev) (((rev) >> 12) & 0x1ff)
  18. #define soc_type(rev) (((rev) >> 12) & 0xf0)
  19. /* both macros return/take MXC_CPU_ constants */
  20. #define get_cpu_type() (cpu_type(get_cpu_rev()))
  21. #define get_soc_type() (soc_type(get_cpu_rev()))
  22. #define is_cpu_type(cpu) (get_cpu_type() == cpu)
  23. #define is_soc_type(soc) (get_soc_type() == soc)
  24. #define is_mx6() (is_soc_type(MXC_SOC_MX6))
  25. #define is_mx7() (is_soc_type(MXC_SOC_MX7))
  26. #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
  27. #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
  28. #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
  29. #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
  30. #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
  31. #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
  32. #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
  33. #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
  34. #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
  35. #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
  36. #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ))
  37. #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
  38. #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
  39. #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
  40. #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL))
  41. #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD))
  42. #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL))
  43. #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
  44. #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
  45. is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
  46. is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
  47. #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
  48. #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
  49. #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
  50. #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
  51. #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
  52. #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \
  53. is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \
  54. is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \
  55. is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ))
  56. #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND))
  57. #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS))
  58. #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL))
  59. #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
  60. #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
  61. #define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ))
  62. #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
  63. #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
  64. #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
  65. is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
  66. #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
  67. #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
  68. #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
  69. #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
  70. #ifdef CONFIG_MX6
  71. #define IMX6_SRC_GPR10_BMODE BIT(28)
  72. #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
  73. #define IMX6_BMODE_MASK GENMASK(7, 0)
  74. #define IMX6_BMODE_SHIFT 4
  75. #define IMX6_BMODE_EMI_MASK BIT(3)
  76. #define IMX6_BMODE_EMI_SHIFT 3
  77. #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
  78. #define IMX6_BMODE_SERIAL_ROM_SHIFT 24
  79. enum imx6_bmode_serial_rom {
  80. IMX6_BMODE_ECSPI1,
  81. IMX6_BMODE_ECSPI2,
  82. IMX6_BMODE_ECSPI3,
  83. IMX6_BMODE_ECSPI4,
  84. IMX6_BMODE_ECSPI5,
  85. IMX6_BMODE_I2C1,
  86. IMX6_BMODE_I2C2,
  87. IMX6_BMODE_I2C3,
  88. };
  89. enum imx6_bmode_emi {
  90. IMX6_BMODE_NOR,
  91. IMX6_BMODE_ONENAND,
  92. };
  93. enum imx6_bmode {
  94. IMX6_BMODE_EMI,
  95. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  96. IMX6_BMODE_QSPI,
  97. IMX6_BMODE_RESERVED,
  98. #else
  99. IMX6_BMODE_RESERVED,
  100. IMX6_BMODE_SATA,
  101. #endif
  102. IMX6_BMODE_SERIAL_ROM,
  103. IMX6_BMODE_SD,
  104. IMX6_BMODE_ESD,
  105. IMX6_BMODE_MMC,
  106. IMX6_BMODE_EMMC,
  107. IMX6_BMODE_NAND_MIN,
  108. IMX6_BMODE_NAND_MAX = 0xf,
  109. };
  110. u32 imx6_src_get_boot_mode(void);
  111. void gpr_init(void);
  112. #endif /* CONFIG_MX6 */
  113. #ifdef CONFIG_MX7
  114. #define IMX7_SRC_GPR10_BMODE BIT(28)
  115. #define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
  116. #endif
  117. /* address translation table */
  118. struct rproc_att {
  119. u32 da; /* device address (From Cortex M4 view) */
  120. u32 sa; /* system bus address */
  121. u32 size; /* size of reg range */
  122. };
  123. #ifdef CONFIG_IMX8M
  124. struct rom_api {
  125. u16 ver;
  126. u16 tag;
  127. u32 reserved1;
  128. u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
  129. u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
  130. };
  131. enum boot_dev_type_e {
  132. BT_DEV_TYPE_SD = 1,
  133. BT_DEV_TYPE_MMC = 2,
  134. BT_DEV_TYPE_NAND = 3,
  135. BT_DEV_TYPE_FLEXSPINOR = 4,
  136. BT_DEV_TYPE_USB = 0xE,
  137. BT_DEV_TYPE_MEM_DEV = 0xF,
  138. BT_DEV_TYPE_INVALID = 0xFF
  139. };
  140. #define QUERY_ROM_VER 1
  141. #define QUERY_BT_DEV 2
  142. #define QUERY_PAGE_SZ 3
  143. #define QUERY_IVT_OFF 4
  144. #define QUERY_BT_STAGE 5
  145. #define QUERY_IMG_OFF 6
  146. #define ROM_API_OKAY 0xF0
  147. extern struct rom_api *g_rom_api;
  148. #endif
  149. u32 get_nr_cpus(void);
  150. u32 get_cpu_rev(void);
  151. u32 get_cpu_speed_grade_hz(void);
  152. u32 get_cpu_temp_grade(int *minc, int *maxc);
  153. const char *get_imx_type(u32 imxtype);
  154. u32 imx_ddr_size(void);
  155. void sdelay(unsigned long);
  156. void set_chipselect_size(int const);
  157. void init_aips(void);
  158. void init_src(void);
  159. void init_snvs(void);
  160. void imx_wdog_disable_powerdown(void);
  161. void board_mem_get_layout(u64 *phys_sdram_1_start,
  162. u64 *phys_sdram_1_size,
  163. u64 *phys_sdram_2_start,
  164. u64 *phys_sdram_2_size);
  165. int arch_auxiliary_core_check_up(u32 core_id);
  166. int board_mmc_get_env_dev(int devno);
  167. int nxp_board_rev(void);
  168. char nxp_board_rev_string(void);
  169. /*
  170. * Initializes on-chip ethernet controllers.
  171. * to override, implement board_eth_init()
  172. */
  173. int fecmxc_initialize(struct bd_info *bis);
  174. u32 get_ahb_clk(void);
  175. u32 get_periph_clk(void);
  176. void lcdif_power_down(void);
  177. int mxs_reset_block(struct mxs_register_32 *reg);
  178. int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
  179. int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
  180. unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
  181. unsigned long reg1, unsigned long reg2,
  182. unsigned long reg3);
  183. unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
  184. unsigned long *reg1, unsigned long reg2,
  185. unsigned long reg3);
  186. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
  187. #endif