imx-regs.h 45 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef _MX7ULP_REGS_H_
  6. #define _MX7ULP_REGS_H_
  7. #include <linux/sizes.h>
  8. #define ARCH_MXC
  9. #define ROM_SW_INFO_ADDR 0x000001E8
  10. #define CAAM_SEC_SRAM_BASE (0x26000000)
  11. #define CAAM_SEC_SRAM_SIZE (SZ_32K)
  12. #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
  13. #define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE
  14. #define OCRAM_0_BASE (0x2F000000)
  15. #define OCRAM_0_SIZE (SZ_128K)
  16. #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1)
  17. #define OCRAM_1_BASE (0x2F020000)
  18. #define OCRAM_1_SIZE (SZ_128K)
  19. #define OCRAM_1_END (OCRAM_1_BASE + OCRAM_1_SIZE - 1)
  20. #define TCML_BASE (0x1FFD0000)
  21. #define TCMU_BASE (0x20000000)
  22. #define AIPS3_BASE (0x40800000UL)
  23. #define AIPS3_SLOT_SIZE (SZ_64K)
  24. #define AIPS2_BASE (0x40000000UL)
  25. #define AIPS2_SLOT_SIZE (SZ_64K)
  26. #define AIPS1_BASE (0x41080000UL)
  27. #define AIPS1_SLOT_SIZE (SZ_4K)
  28. #define AIPS0_BASE (0x41000000UL)
  29. #define AIPS0_SLOT_SIZE (SZ_4K)
  30. #define IOMUXC0_AIPS0_SLOT (61)
  31. #define WDG0_AIPS0_SLOT (37)
  32. #define WDG1_AIPS2_SLOT (61)
  33. #define WDG2_AIPS2_SLOT (67)
  34. #define WDG0_PCC0_SLOT (37)
  35. #define IOMUXC1_AIPS3_SLOT (44)
  36. #define CMC0_AIPS1_SLOT (36)
  37. #define CMC1_AIPS2_SLOT (65)
  38. #define SCG0_AIPS0_SLOT (39)
  39. #define PCC0_AIPS0_SLOT (38)
  40. #define PCC1_AIPS1_SLOT (50)
  41. #define PCC2_AIPS2_SLOT (63)
  42. #define PCC3_AIPS3_SLOT (51)
  43. #define SCG1_AIPS2_SLOT (62)
  44. #define SIM0_AIPS1_SLOT (35)
  45. #define SIM1_AIPS1_SLOT (48)
  46. #define USBOTG0_AIPS2_SLOT (51)
  47. #define USBOTG1_AIPS2_SLOT (52)
  48. #define USBPHY_AIPS2_SLOT (53)
  49. #define USDHC0_AIPS2_SLOT (55)
  50. #define USDHC1_AIPS2_SLOT (56)
  51. #define RGPIO2P0_AIPS0_SLOT (15)
  52. #define RGPIO2P1_AIPS2_SLOT (15)
  53. #define SNVS_AIPS2_SLOT (35)
  54. #define IOMUXC0_AIPS0_SLOT (61)
  55. #define OCOTP_CTRL_AIPS1_SLOT (38)
  56. #define OCOTP_CTRL_PCC1_SLOT (38)
  57. #define SIM1_PCC1_SLOT (48)
  58. #define MMDC0_AIPS3_SLOT (43)
  59. #define IOMUXC_DDR_AIPS3_SLOT (45)
  60. #define LPI2C0_AIPS0_SLOT (51)
  61. #define LPI2C1_AIPS0_SLOT (52)
  62. #define LPI2C2_AIPS0_SLOT (53)
  63. #define LPI2C3_AIPS0_SLOT (54)
  64. #define LPI2C4_AIPS2_SLOT (43)
  65. #define LPI2C5_AIPS2_SLOT (44)
  66. #define LPI2C6_AIPS3_SLOT (36)
  67. #define LPI2C7_AIPS3_SLOT (37)
  68. #define LPUART0_PCC0_SLOT (58)
  69. #define LPUART1_PCC0_SLOT (59)
  70. #define LPUART2_PCC1_SLOT (43)
  71. #define LPUART3_PCC1_SLOT (44)
  72. #define LPUART0_AIPS0_SLOT (58)
  73. #define LPUART1_AIPS0_SLOT (59)
  74. #define LPUART2_AIPS1_SLOT (43)
  75. #define LPUART3_AIPS1_SLOT (44)
  76. #define LPUART4_AIPS2_SLOT (45)
  77. #define LPUART5_AIPS2_SLOT (46)
  78. #define LPUART6_AIPS3_SLOT (38)
  79. #define LPUART7_AIPS3_SLOT (39)
  80. #define CORE_B_ROM_SIZE (SZ_32K + SZ_64K)
  81. #define CORE_B_ROM_BASE (0x00000000)
  82. #define ROMCP_ARB_BASE_ADDR CORE_B_ROM_BASE
  83. #define ROMCP_ARB_END_ADDR CORE_B_ROM_SIZE
  84. #define IRAM_BASE_ADDR OCRAM_0_BASE
  85. #define IRAM_SIZE (SZ_128K + SZ_128K)
  86. #define IOMUXC_PCR_MUX_ALT0 (0<<8)
  87. #define IOMUXC_PCR_MUX_ALT1 (1<<8)
  88. #define IOMUXC_PCR_MUX_ALT2 (2<<8)
  89. #define IOMUXC_PCR_MUX_ALT3 (3<<8)
  90. #define IOMUXC_PCR_MUX_ALT4 (4<<8)
  91. #define IOMUXC_PCR_MUX_ALT5 (5<<8)
  92. #define IOMUXC_PCR_MUX_ALT6 (6<<8)
  93. #define IOMUXC_PCR_MUX_ALT7 (7<<8)
  94. #define IOMUXC_PCR_MUX_ALT8 (8<<8)
  95. #define IOMUXC_PCR_MUX_ALT9 (9<<8)
  96. #define IOMUXC_PCR_MUX_ALT10 (10<<8)
  97. #define IOMUXC_PCR_MUX_ALT11 (11<<8)
  98. #define IOMUXC_PCR_MUX_ALT12 (12<<8)
  99. #define IOMUXC_PCR_MUX_ALT13 (13<<8)
  100. #define IOMUXC_PCR_MUX_ALT14 (14<<8)
  101. #define IOMUXC_PCR_MUX_ALT15 (15<<8)
  102. #define IOMUXC_PSMI_IMUX_ALT0 (0x0)
  103. #define IOMUXC_PSMI_IMUX_ALT1 (0x1)
  104. #define IOMUXC_PSMI_IMUX_ALT2 (0x2)
  105. #define IOMUXC_PSMI_IMUX_ALT3 (0x3)
  106. #define IOMUXC_PSMI_IMUX_ALT4 (0x4)
  107. #define IOMUXC_PSMI_IMUX_ALT5 (0x5)
  108. #define IOMUXC_PSMI_IMUX_ALT6 (0x6)
  109. #define IOMUXC_PSMI_IMUX_ALT7 (0x7)
  110. #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8)
  111. #define SIM_SOPT1_PMIC_STBY_REQ (1<<2)
  112. #define SIM_SOPT1_A7_SW_RESET (1<<0)
  113. #define IOMUXC_PCR_MUX_ALT_SHIFT (8)
  114. #define IOMUXC_PCR_MUX_ALT_MASK (0xF00)
  115. #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
  116. #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
  117. #define IOMUXC1_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT)))
  118. #define WDG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT)))
  119. #define WDG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT)))
  120. #define WDG2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT)))
  121. #define SCG0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT)))
  122. #define SCG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT)))
  123. #define PCC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT)))
  124. #define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT)))
  125. #define PCC2_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT)))
  126. #define PCC3_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT)))
  127. #define IOMUXC0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
  128. #define PSMI0_RBASE ((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */
  129. #define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT)))
  130. #define CMC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT)))
  131. #define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT)))
  132. #define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT)))
  133. #define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT)))
  134. #define MMDC0_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT)))
  135. #define USBOTG0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT)))
  136. #define USBOTG1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT)))
  137. #define USBPHY_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT)))
  138. #define USB_PHY0_BASE_ADDR USBPHY_RBASE
  139. #define USB_BASE_ADDR USBOTG0_RBASE
  140. #define LPI2C1_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT)))
  141. #define LPI2C2_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT)))
  142. #define LPI2C3_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT)))
  143. #define LPI2C4_BASE_ADDR ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT)))
  144. #define LPI2C5_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT)))
  145. #define LPI2C6_BASE_ADDR ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT)))
  146. #define LPI2C7_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT)))
  147. #define LPI2C8_BASE_ADDR ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT)))
  148. #define LPUART0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT)))
  149. #define LPUART1_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT)))
  150. #define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT)))
  151. #define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT)))
  152. #define LPUART4_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT)))
  153. #define LPUART5_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT)))
  154. #define LPUART6_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT)))
  155. #define LPUART7_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT)))
  156. #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
  157. #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
  158. #define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
  159. #define SNVS_LP_LPCR (SNVS_BASE + 0x38)
  160. #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
  161. #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
  162. #define WDG0_PCC_REG (PCC0_RBASE + (4 * WDG0_PCC0_SLOT))
  163. #define WDG1_PCC_REG (PCC2_RBASE + (4 * WDG1_PCC2_SLOT))
  164. #define CMC0_SRS (CMC0_RBASE + 0x20)
  165. #define CMC0_SSRS (CMC0_RBASE + 0x28)
  166. #define CMC1_SRS (CMC1_RBASE + 0x20)
  167. #define CMC1_SSRS (CMC1_RBASE + 0x28)
  168. #define IOMUXC0_PCR0 (IOMUXC0_RBASE + (4 * 0))
  169. #define IOMUXC0_PCR1 (IOMUXC0_RBASE + (4 * 1))
  170. #define IOMUXC0_PCR2 (IOMUXC0_RBASE + (4 * 2))
  171. #define IOMUXC0_PCR3 (IOMUXC0_RBASE + (4 * 3))
  172. #define IOMUXC0_PSMI62 (PSMI0_RBASE + (4 * 62))
  173. #define IOMUXC0_PSMI63 (PSMI0_RBASE + (4 * 63))
  174. #define IOMUXC0_PSMI64 (PSMI0_RBASE + (4 * 64))
  175. #define SCG_CSR (SCG0_RBASE + 0x010)
  176. #define SCG_RCCR (SCG0_RBASE + 0x014)
  177. #define SCG_VCCR (SCG0_RBASE + 0x018)
  178. #define SCG_HCCR (SCG0_RBASE + 0x01c)
  179. #define LPUART0_PCC_REG (PCC0_RBASE + (4 * LPUART0_PCC0_SLOT))
  180. #define LPUART1_PCC_REG (PCC0_RBASE + (4 * LPUART1_PCC0_SLOT))
  181. #define LPUART2_PCC_REG (PCC1_RBASE + (4 * LPUART2_PCC1_SLOT))
  182. #define LPUART3_PCC_REG (PCC1_RBASE + (4 * LPUART3_PCC1_SLOT))
  183. #define LPUART4_PCC_REG (PCC2_RBASE + (4 * LPUART4_PCC2_SLOT))
  184. #define LPUART5_PCC_REG (PCC2_RBASE + (4 * LPUART5_PCC2_SLOT))
  185. #define LPUART6_PCC_REG (PCC3_RBASE + (4 * LPUART6_PCC3_SLOT))
  186. #define LPUART7_PCC_REG (PCC3_RBASE + (4 * LPUART7_PCC3_SLOT))
  187. #define USDHC0_PCC_REG (PCC2_RBASE + (4 * USDHC0_PCC2_SLOT))
  188. #define USDHC1_PCC_REG (PCC2_RBASE + (4 * USDHC1_PCC2_SLOT))
  189. #define SIM1_PCC_REG (PCC1_RBASE + (4 * SIM1_PCC1_SLOT))
  190. #define SCG1_PCC_REG (PCC2_RBASE + (4 * SCG1_PCC2_SLOT))
  191. #define OCOTP_CTRL_PCC_REG (PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT))
  192. #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT)))
  193. #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT))
  194. #define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
  195. #define CONFIG_SYS_FSL_SEC_OFFSET 0
  196. #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
  197. CONFIG_SYS_FSL_SEC_OFFSET)
  198. #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
  199. #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
  200. CONFIG_SYS_FSL_JR0_OFFSET)
  201. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  202. #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
  203. #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
  204. #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34)))
  205. #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35)))
  206. #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0)))
  207. #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1)))
  208. #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2)))
  209. #define IOMUXC_DPCR_DDR_DQ3 ((IOMUXC_DDR_RBASE + (4 * 3)))
  210. #define IOMUXC_DPCR_DDR_DQ4 ((IOMUXC_DDR_RBASE + (4 * 4)))
  211. #define IOMUXC_DPCR_DDR_DQ5 ((IOMUXC_DDR_RBASE + (4 * 5)))
  212. #define IOMUXC_DPCR_DDR_DQ6 ((IOMUXC_DDR_RBASE + (4 * 6)))
  213. #define IOMUXC_DPCR_DDR_DQ7 ((IOMUXC_DDR_RBASE + (4 * 7)))
  214. #define IOMUXC_DPCR_DDR_DQ8 ((IOMUXC_DDR_RBASE + (4 * 8)))
  215. #define IOMUXC_DPCR_DDR_DQ9 ((IOMUXC_DDR_RBASE + (4 * 9)))
  216. #define IOMUXC_DPCR_DDR_DQ10 ((IOMUXC_DDR_RBASE + (4 * 10)))
  217. #define IOMUXC_DPCR_DDR_DQ11 ((IOMUXC_DDR_RBASE + (4 * 11)))
  218. #define IOMUXC_DPCR_DDR_DQ12 ((IOMUXC_DDR_RBASE + (4 * 12)))
  219. #define IOMUXC_DPCR_DDR_DQ13 ((IOMUXC_DDR_RBASE + (4 * 13)))
  220. #define IOMUXC_DPCR_DDR_DQ14 ((IOMUXC_DDR_RBASE + (4 * 14)))
  221. #define IOMUXC_DPCR_DDR_DQ15 ((IOMUXC_DDR_RBASE + (4 * 15)))
  222. #define IOMUXC_DPCR_DDR_DQ16 ((IOMUXC_DDR_RBASE + (4 * 16)))
  223. #define IOMUXC_DPCR_DDR_DQ17 ((IOMUXC_DDR_RBASE + (4 * 17)))
  224. #define IOMUXC_DPCR_DDR_DQ18 ((IOMUXC_DDR_RBASE + (4 * 18)))
  225. #define IOMUXC_DPCR_DDR_DQ19 ((IOMUXC_DDR_RBASE + (4 * 19)))
  226. #define IOMUXC_DPCR_DDR_DQ20 ((IOMUXC_DDR_RBASE + (4 * 20)))
  227. #define IOMUXC_DPCR_DDR_DQ21 ((IOMUXC_DDR_RBASE + (4 * 21)))
  228. #define IOMUXC_DPCR_DDR_DQ22 ((IOMUXC_DDR_RBASE + (4 * 22)))
  229. #define IOMUXC_DPCR_DDR_DQ23 ((IOMUXC_DDR_RBASE + (4 * 23)))
  230. #define IOMUXC_DPCR_DDR_DQ24 ((IOMUXC_DDR_RBASE + (4 * 24)))
  231. #define IOMUXC_DPCR_DDR_DQ25 ((IOMUXC_DDR_RBASE + (4 * 25)))
  232. #define IOMUXC_DPCR_DDR_DQ26 ((IOMUXC_DDR_RBASE + (4 * 26)))
  233. #define IOMUXC_DPCR_DDR_DQ27 ((IOMUXC_DDR_RBASE + (4 * 27)))
  234. #define IOMUXC_DPCR_DDR_DQ28 ((IOMUXC_DDR_RBASE + (4 * 28)))
  235. #define IOMUXC_DPCR_DDR_DQ29 ((IOMUXC_DDR_RBASE + (4 * 29)))
  236. #define IOMUXC_DPCR_DDR_DQ30 ((IOMUXC_DDR_RBASE + (4 * 30)))
  237. #define IOMUXC_DPCR_DDR_DQ31 ((IOMUXC_DDR_RBASE + (4 * 31)))
  238. /* Remap the rgpio2p registers addr to driver's addr */
  239. #define RGPIO2P_GPIO1_BASE_ADDR RGPIO2P0_RBASE
  240. #define RGPIO2P_GPIO2_BASE_ADDR (RGPIO2P0_RBASE + 0x40)
  241. #define RGPIO2P_GPIO3_BASE_ADDR (RGPIO2P1_RBASE)
  242. #define RGPIO2P_GPIO4_BASE_ADDR (RGPIO2P1_RBASE + 0x40)
  243. #define RGPIO2P_GPIO5_BASE_ADDR (RGPIO2P1_RBASE + 0x80)
  244. #define RGPIO2P_GPIO6_BASE_ADDR (RGPIO2P1_RBASE + 0xc0)
  245. /* MMDC registers addresses */
  246. #define MMDC_MDCTL_OFFSET (0x000)
  247. #define MMDC_MDPDC_OFFSET (0x004)
  248. #define MMDC_MDOTC_OFFSET (0x008)
  249. #define MMDC_MDCFG0_OFFSET (0x00C)
  250. #define MMDC_MDCFG1_OFFSET (0x010)
  251. #define MMDC_MDCFG2_OFFSET (0x014)
  252. #define MMDC_MDMISC_OFFSET (0x018)
  253. #define MMDC_MDSCR_OFFSET (0x01C)
  254. #define MMDC_MDREF_OFFSET (0x020)
  255. #define MMDC_MDRWD_OFFSET (0x02C)
  256. #define MMDC_MDOR_OFFSET (0x030)
  257. #define MMDC_MDMRR_OFFSET (0x034)
  258. #define MMDC_MDCFG3LP_OFFSET (0x038)
  259. #define MMDC_MDMR4_OFFSET (0x03C)
  260. #define MMDC_MDASP_OFFSET (0x040)
  261. #define MMDC_MAARCR_OFFSET (0x400)
  262. #define MMDC_MAPSR_OFFSET (0x404)
  263. #define MMDC_MAEXIDR0_OFFSET (0x408)
  264. #define MMDC_MAEXIDR1_OFFSET (0x40C)
  265. #define MMDC_MADPCR0_OFFSET (0x410)
  266. #define MMDC_MADPCR1_OFFSET (0x414)
  267. #define MMDC_MADPSR0_OFFSET (0x418)
  268. #define MMDC_MADPSR1_OFFSET (0x41C)
  269. #define MMDC_MADPSR2_OFFSET (0x420)
  270. #define MMDC_MADPSR3_OFFSET (0x424)
  271. #define MMDC_MADPSR4_OFFSET (0x428)
  272. #define MMDC_MADPSR5_OFFSET (0x42C)
  273. #define MMDC_MASBS0_OFFSET (0x430)
  274. #define MMDC_MASBS1_OFFSET (0x434)
  275. #define MMDC_MAGENP_OFFSET (0x440)
  276. #define MMDC_MPZQHWCTRL_OFFSET (0x800)
  277. #define MMDC_MPZQSWCTRL_OFFSET (0x804)
  278. #define MMDC_MPWLGCR_OFFSET (0x808)
  279. #define MMDC_MPWLDECTRL0_OFFSET (0x80C)
  280. #define MMDC_MPWLDECTRL1_OFFSET (0x810)
  281. #define MMDC_MPWLDLST_OFFSET (0x814)
  282. #define MMDC_MPODTCTRL_OFFSET (0x818)
  283. #define MMDC_MPREDQBY0DL_OFFSET (0x81C)
  284. #define MMDC_MPREDQBY1DL_OFFSET (0x820)
  285. #define MMDC_MPREDQBY2DL_OFFSET (0x824)
  286. #define MMDC_MPREDQBY3DL_OFFSET (0x828)
  287. #define MMDC_MPWRDQBY0DL_OFFSET (0x82C)
  288. #define MMDC_MPWRDQBY1DL_OFFSET (0x830)
  289. #define MMDC_MPWRDQBY2DL_OFFSET (0x834)
  290. #define MMDC_MPWRDQBY3DL_OFFSET (0x838)
  291. #define MMDC_MPDGCTRL0_OFFSET (0x83C)
  292. #define MMDC_MPDGCTRL1_OFFSET (0x840)
  293. #define MMDC_MPDGDLST_OFFSET (0x844)
  294. #define MMDC_MPRDDLCTL_OFFSET (0x848)
  295. #define MMDC_MPRDDLST_OFFSET (0x84C)
  296. #define MMDC_MPWRDLCTL_OFFSET (0x850)
  297. #define MMDC_MPWRDLST_OFFSET (0x854)
  298. #define MMDC_MPSDCTRL_OFFSET (0x858)
  299. #define MMDC_MPZQLP2CTL_OFFSET (0x85C)
  300. #define MMDC_MPRDDLHWCTL_OFFSET (0x860)
  301. #define MMDC_MPWRDLHWCTL_OFFSET (0x864)
  302. #define MMDC_MPRDDLHWST0_OFFSET (0x868)
  303. #define MMDC_MPRDDLHWST1_OFFSET (0x86C)
  304. #define MMDC_MPWRDLHWST0_OFFSET (0x870)
  305. #define MMDC_MPWRDLHWST1_OFFSET (0x874)
  306. #define MMDC_MPWLHWERR_OFFSET (0x878)
  307. #define MMDC_MPDGHWST0_OFFSET (0x87C)
  308. #define MMDC_MPDGHWST1_OFFSET (0x880)
  309. #define MMDC_MPDGHWST2_OFFSET (0x884)
  310. #define MMDC_MPDGHWST3_OFFSET (0x888)
  311. #define MMDC_MPPDCMPR1_OFFSET (0x88C)
  312. #define MMDC_MPPDCMPR2_OFFSET (0x890)
  313. #define MMDC_MPSWDAR_OFFSET (0x894)
  314. #define MMDC_MPSWDRDR0_OFFSET (0x898)
  315. #define MMDC_MPSWDRDR1_OFFSET (0x89C)
  316. #define MMDC_MPSWDRDR2_OFFSET (0x8A0)
  317. #define MMDC_MPSWDRDR3_OFFSET (0x8A4)
  318. #define MMDC_MPSWDRDR4_OFFSET (0x8A8)
  319. #define MMDC_MPSWDRDR5_OFFSET (0x8AC)
  320. #define MMDC_MPSWDRDR6_OFFSET (0x8B0)
  321. #define MMDC_MPSWDRDR7_OFFSET (0x8B4)
  322. #define MMDC_MPMUR_OFFSET (0x8B8)
  323. #define MMDC_MPWRCADL_OFFSET (0x8BC)
  324. #define MMDC_MPDCCR_OFFSET (0x8C0)
  325. #define MMDC_MPBC_OFFSET (0x8C4)
  326. #define MMDC_MPSWDRAR_OFFSET (0x8C8)
  327. /* First MMDC invalid IPS address */
  328. #define MMDC_IPS_ILL_ADDR_START_OFFSET (0x8CC)
  329. #define MMDC_REGS_BASE MMDC0_RBASE
  330. #define MMDC_MDCTL ((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET))
  331. #define MMDC_MDPDC ((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET))
  332. #define MMDC_MDOTC ((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET))
  333. #define MMDC_MDCFG0 ((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET))
  334. #define MMDC_MDCFG1 ((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET))
  335. #define MMDC_MDCFG2 ((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET))
  336. #define MMDC_MDMISC ((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET))
  337. #define MMDC_MDSCR ((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET))
  338. #define MMDC_MDREF ((MMDC_REGS_BASE + MMDC_MDREF_OFFSET))
  339. #define MMDC_MDRWD ((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET))
  340. #define MMDC_MDOR ((MMDC_REGS_BASE + MMDC_MDOR_OFFSET))
  341. #define MMDC_MDMRR ((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET))
  342. #define MMDC_MDCFG3LP ((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET))
  343. #define MMDC_MDMR4 ((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET))
  344. #define MMDC_MDASP ((MMDC_REGS_BASE + MMDC_MDASP_OFFSET))
  345. #define MMDC_MAARCR ((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET))
  346. #define MMDC_MAPSR ((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET))
  347. #define MMDC_MAEXIDR0 ((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET))
  348. #define MMDC_MAEXIDR1 ((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET))
  349. #define MMDC_MADPCR0 ((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET))
  350. #define MMDC_MADPCR1 ((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET))
  351. #define MMDC_MADPSR0 ((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET))
  352. #define MMDC_MADPSR1 ((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET))
  353. #define MMDC_MADPSR2 ((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET))
  354. #define MMDC_MADPSR3 ((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET))
  355. #define MMDC_MADPSR4 ((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET))
  356. #define MMDC_MADPSR5 ((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET))
  357. #define MMDC_MASBS0 ((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET))
  358. #define MMDC_MASBS1 ((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET))
  359. #define MMDC_MAGENP ((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET))
  360. #define MMDC_MPZQHWCTRL ((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET))
  361. #define MMDC_MPZQSWCTRL ((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET))
  362. #define MMDC_MPWLGCR ((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET))
  363. #define MMDC_MPWLDECTRL0 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET))
  364. #define MMDC_MPWLDECTRL1 ((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET))
  365. #define MMDC_MPWLDLST ((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET))
  366. #define MMDC_MPODTCTRL ((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET))
  367. #define MMDC_MPREDQBY0DL ((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET))
  368. #define MMDC_MPREDQBY1DL ((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET))
  369. #define MMDC_MPREDQBY2DL ((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET))
  370. #define MMDC_MPREDQBY3DL ((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET))
  371. #define MMDC_MPWRDQBY0DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET))
  372. #define MMDC_MPWRDQBY1DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET))
  373. #define MMDC_MPWRDQBY2DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET))
  374. #define MMDC_MPWRDQBY3DL ((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET))
  375. #define MMDC_MPDGCTRL0 ((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET))
  376. #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET))
  377. #define MMDC_MPDGDLST ((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET))
  378. #define MMDC_MPRDDLCTL ((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET))
  379. #define MMDC_MPRDDLST ((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET))
  380. #define MMDC_MPWRDLCTL ((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET))
  381. #define MMDC_MPWRDLST ((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET))
  382. #define MMDC_MPSDCTRL ((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET))
  383. #define MMDC_MPZQLP2CTL ((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET))
  384. #define MMDC_MPRDDLHWCTL ((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET))
  385. #define MMDC_MPWRDLHWCTL ((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET))
  386. #define MMDC_MPRDDLHWST0 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET))
  387. #define MMDC_MPRDDLHWST1 ((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET))
  388. #define MMDC_MPWRDLHWST0 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET))
  389. #define MMDC_MPWRDLHWST1 ((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET))
  390. #define MMDC_MPWLHWERR ((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET))
  391. #define MMDC_MPDGHWST0 ((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET))
  392. #define MMDC_MPDGHWST1 ((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET))
  393. #define MMDC_MPDGHWST2 ((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET))
  394. #define MMDC_MPDGHWST3 ((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET))
  395. #define MMDC_MPPDCMPR1 ((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET))
  396. #define MMDC_MPPDCMPR2 ((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET))
  397. #define MMDC_MPSWDAR ((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET))
  398. #define MMDC_MPSWDRDR0 ((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET))
  399. #define MMDC_MPSWDRDR1 ((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET))
  400. #define MMDC_MPSWDRDR2 ((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET))
  401. #define MMDC_MPSWDRDR3 ((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET))
  402. #define MMDC_MPSWDRDR4 ((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET))
  403. #define MMDC_MPSWDRDR5 ((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET))
  404. #define MMDC_MPSWDRDR6 ((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET))
  405. #define MMDC_MPSWDRDR7 ((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET))
  406. #define MMDC_MPMUR ((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET))
  407. #define MMDC_MPWRCADL ((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET))
  408. #define MMDC_MPDCCR ((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET))
  409. #define MMDC_MPBC ((MMDC_REGS_BASE + MMDC_MPBC_OFFSET))
  410. #define MMDC_MPSWDRAR ((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET))
  411. /* MMDC registers bit defines */
  412. #define MMDC_MDCTL_SDE_0 (31)
  413. #define MMDC_MDCTL_SDE_1 (30)
  414. #define MMDC_MDCTL_ROW (24)
  415. #define MMDC_MDCTL_COL (20)
  416. #define MMDC_MDCTL_BL (19)
  417. #define MMDC_MDCTL_DSIZ (16)
  418. /* MDMISC */
  419. #define MMDC_MDMISC_CS0_RDY (31)
  420. #define MMDC_MDMISC_CS1_RDY (30)
  421. #define MMDC_MDMISC_CK1_DEL (22)
  422. #define MMDC_MDMISC_CK1_GATING (21)
  423. #define MMDC_MDMISC_CALIB_PER_CS (20)
  424. #define MMDC_MDMISC_ADDR_MIRROR (19)
  425. #define MMDC_MDMISC_LHD (18)
  426. #define MMDC_MDMISC_WALAT (16)
  427. #define MMDC_MDMISC_BI (12)
  428. #define MMDC_MDMISC_LPDDR2_S (11)
  429. #define MMDC_MDMISC_MIF3_MODE (9)
  430. #define MMDC_MDMISC_RALAT (6)
  431. #define MMDC_MDMISC_DDR_4_BANK (5)
  432. #define MMDC_MDMISC_DDR_TYPE (3)
  433. #define MMDC_MDMISC_RST (1)
  434. /* MPWLGCR */
  435. #define MMDC_MPWLGCR_WL_HW_ERR (8)
  436. /* MDSCR */
  437. #define MMDC_MDSCR_CMD_ADDR_MSB (24)
  438. #define MMDC_MDSCR_MR_OP (24)
  439. #define MMDC_MDSCR_CMD_ADDR_LSB (16)
  440. #define MMDC_MDSCR_MR_ADDR (16)
  441. #define MMDC_MDSCR_CON_REQ (15)
  442. #define MMDC_MDSCR_CON_ACK (14)
  443. #define MMDC_MDSCR_MRR_READ_DATA_VALID (10)
  444. #define MMDC_MDSCR_WL_EN (9)
  445. #define MMDC_MDSCR_CMD (4)
  446. #define MMDC_MDSCR_CMD_CS (3)
  447. #define MMDC_MDSCR_CMD_BA (0)
  448. /* MPZQHWCTRL */
  449. #define MMDC_MPZQHWCTRL_ZQ_HW_FOR (16)
  450. #define MMDC_MPZQHWCTRL_ZQ_MODE (0)
  451. /* MPZQSWCTRL */
  452. #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP (16)
  453. #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL (13)
  454. #define MMDC_MPZQSWCTRL_ZQ_SW_PD (12)
  455. #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL (7)
  456. #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL (2)
  457. #define MMDC_MPZQSWCTRL_ZQ_SW_RES (1)
  458. #define MMDC_MPZQSWCTRL_ZQ_SW_FOR (0)
  459. /* MPDGCTRL0 */
  460. #define MMDC_MPDGCTRL0_RST_RD_FIFO (31)
  461. #define MMDC_MPDGCTRL0_DG_CMP_CYC (30)
  462. #define MMDC_MPDGCTRL0_DG_DIS (29)
  463. #define MMDC_MPDGCTRL0_HW_DG_EN (28)
  464. #define MMDC_MPDGCTRL0_HW_DG_ERR (12)
  465. /* MPRDDLHWCTL */
  466. #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC (5)
  467. #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN (4)
  468. #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR (0)
  469. /* MPWRDLHWCTL */
  470. #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC (5)
  471. #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN (4)
  472. #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR (0)
  473. /* MPSWDAR */
  474. #define MMDC_MPSWDAR_TEST_DUMMY_EN (6)
  475. #define MMDC_MPSWDAR_SW_DUM_CMP3 (5)
  476. #define MMDC_MPSWDAR_SW_DUM_CMP2 (4)
  477. #define MMDC_MPSWDAR_SW_DUM_CMP1 (3)
  478. #define MMDC_MPSWDAR_SW_DUM_CMP0 (2)
  479. #define MMDC_MPSWDAR_SW_DUMMY_RD (1)
  480. #define MMDC_MPSWDAR_SW_DUMMY_WR (0)
  481. /* MADPCR0 */
  482. #define MMDC_MADPCR0_SBS (9)
  483. #define MMDC_MADPCR0_SBS_EN (8)
  484. /* MASBS1 */
  485. #define MMDC_MASBS1_SBS_VLD (0)
  486. #define MMDC_MASBS1_SBS_TYPE (1)
  487. /* MDREF */
  488. #define MMDC_MDREF_REF_CNT (16)
  489. #define MMDC_MDREF_REF_SEL (14)
  490. #define MMDC_MDREF_REFR (11)
  491. #define MMDC_MDREF_START_REF (0)
  492. /* MPWLGCR */
  493. #define MMDC_MPWLGCR_HW_WL_EN (0)
  494. /* MPBC */
  495. #define MMDC_MPBC_BIST_DM_LP_EN (0)
  496. #define MMDC_MPBC_BIST_CA0_LP_EN (1)
  497. #define MMDC_MPBC_BIST_DQ0_LP_EN (3)
  498. #define MMDC_MPBC_BIST_DQ1_LP_EN (4)
  499. #define MMDC_MPBC_BIST_DQ2_LP_EN (5)
  500. #define MMDC_MPBC_BIST_DQ3_LP_EN (6)
  501. /* MPMUR */
  502. #define MMDC_MPMUR_FRC_MSR (11)
  503. /* MPODTCTRL */
  504. #define MMDC_MPODTCTRL_ODT_RD_ACT_EN (3)
  505. #define MMDC_MPODTCTRL_ODT_RD_PAS_EN (2)
  506. #define MMDC_MPODTCTRL_ODT_WR_ACT_EN (1)
  507. #define MMDC_MPODTCTRL_ODT_WR_PAS_EN (0)
  508. /* MAPSR */
  509. #define MMDC_MAPSR_DVACK (25)
  510. #define MMDC_MAPSR_LPACK (24)
  511. #define MMDC_MAPSR_DVFS (21)
  512. #define MMDC_MAPSR_LPMD (20)
  513. /* MAARCR */
  514. #define MMDC_MAARCR_ARCR_EXC_ERR_EN (28)
  515. /* MPZQLP2CTL */
  516. #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS (24)
  517. #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL (16)
  518. #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT (0)
  519. /* MDCFG3LP */
  520. #define MMDC_MDCFG3LP_tRC_LP (16)
  521. #define MMDC_MDCFG3LP_tRCD_LP (8)
  522. #define MMDC_MDCFG3LP_tRPpb_LP (4)
  523. #define MMDC_MDCFG3LP_tRPab_LP (0)
  524. /* MDOR */
  525. #define MMDC_MDOR_tXPR (16)
  526. #define MMDC_MDOR_SDE_to_RST (8)
  527. #define MMDC_MDOR_RST_to_CKE (0)
  528. /* MDCFG0 */
  529. #define MMDC_MDCFG0_tRFC (24)
  530. #define MMDC_MDCFG0_tXS (16)
  531. #define MMDC_MDCFG0_tXP (13)
  532. #define MMDC_MDCFG0_tXPDLL (9)
  533. #define MMDC_MDCFG0_tFAW (4)
  534. #define MMDC_MDCFG0_tCL (0)
  535. /* MDCFG1 */
  536. #define MMDC_MDCFG1_tRCD (29)
  537. #define MMDC_MDCFG1_tRP (26)
  538. #define MMDC_MDCFG1_tRC (21)
  539. #define MMDC_MDCFG1_tRAS (16)
  540. #define MMDC_MDCFG1_tRPA (15)
  541. #define MMDC_MDCFG1_tWR (9)
  542. #define MMDC_MDCFG1_tMRD (5)
  543. #define MMDC_MDCFG1_tCWL (0)
  544. /* MDCFG2 */
  545. #define MMDC_MDCFG2_tDLLK (16)
  546. #define MMDC_MDCFG2_tRTP (6)
  547. #define MMDC_MDCFG2_tWTR (3)
  548. #define MMDC_MDCFG2_tRRD (0)
  549. /* MDRWD */
  550. #define MMDC_MDRWD_tDAI (16)
  551. #define MMDC_MDRWD_RTW_SAME (12)
  552. #define MMDC_MDRWD_WTR_DIFF (9)
  553. #define MMDC_MDRWD_WTW_DIFF (6)
  554. #define MMDC_MDRWD_RTW_DIFF (3)
  555. #define MMDC_MDRWD_RTR_DIFF (0)
  556. /* MDPDC */
  557. #define MMDC_MDPDC_PRCT_1 (28)
  558. #define MMDC_MDPDC_PRCT_0 (24)
  559. #define MMDC_MDPDC_tCKE (16)
  560. #define MMDC_MDPDC_PWDT_1 (12)
  561. #define MMDC_MDPDC_PWDT_0 (8)
  562. #define MMDC_MDPDC_SLOW_PD (7)
  563. #define MMDC_MDPDC_BOTH_CS_PD (6)
  564. #define MMDC_MDPDC_tCKSRX (3)
  565. #define MMDC_MDPDC_tCKSRE (0)
  566. /* MDASP */
  567. #define MMDC_MDASP_CS0_END (0)
  568. /* MAEXIDR0 */
  569. #define MMDC_MAEXIDR0_EXC_ID_MONITOR1 (16)
  570. #define MMDC_MAEXIDR0_EXC_ID_MONITOR0 (0)
  571. /* MAEXIDR1 */
  572. #define MMDC_MAEXIDR1_EXC_ID_MONITOR3 (16)
  573. #define MMDC_MAEXIDR1_EXC_ID_MONITOR2 (0)
  574. /* MPWRDLCTL */
  575. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3 (24)
  576. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2 (16)
  577. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1 (8)
  578. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0 (0)
  579. /* MPRDDLCTL */
  580. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3 (24)
  581. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2 (16)
  582. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1 (8)
  583. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0 (0)
  584. /* MPWRDQBY0DL */
  585. #define MMDC_MPWRDQBY0DL_WR_DM0_DEL (30)
  586. #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL (28)
  587. #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL (24)
  588. #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL (20)
  589. #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL (16)
  590. #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL (12)
  591. #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL (8)
  592. #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL (4)
  593. #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL (0)
  594. /* MPWRDQBY1DL */
  595. #define MMDC_MPWRDQBY1DL_WR_DM1_DEL (30)
  596. #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL (28)
  597. #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL (24)
  598. #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL (20)
  599. #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL (16)
  600. #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL (12)
  601. #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL (8)
  602. #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL (4)
  603. #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL (0)
  604. /* MPWRDQBY2DL */
  605. #define MMDC_MPWRDQBY2DL_WR_DM2_DEL (30)
  606. #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL (28)
  607. #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL (24)
  608. #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL (20)
  609. #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL (16)
  610. #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL (12)
  611. #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL (8)
  612. #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL (4)
  613. #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL (0)
  614. /* MPWRDQBY3DL */
  615. #define MMDC_MPWRDQBY3DL_WR_DM3_DEL (30)
  616. #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL (28)
  617. #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL (24)
  618. #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL (20)
  619. #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL (16)
  620. #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL (12)
  621. #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL (8)
  622. #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL (4)
  623. #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL (0)
  624. /* Fields masks */
  625. #define MMDC_MDCTL_SDE_0_MASK ((0x1 << MMDC_MDCTL_SDE_0))
  626. #define MMDC_MDCTL_SDE_1_MASK ((0x1 << MMDC_MDCTL_SDE_1))
  627. #define MMDC_MDCTL_BL_MASK ((0x1 << MMDC_MDCTL_BL))
  628. #define MMDC_MDCTL_ROW_MASK ((0x7 << MMDC_MDCTL_ROW))
  629. #define MMDC_MDCTL_COL_MASK ((0x7 << MMDC_MDCTL_COL))
  630. #define MMDC_MDCTL_DSIZ_MASK ((0x3 << MMDC_MDCTL_DSIZ))
  631. /* MDMISC */
  632. #define MMDC_MDMISC_CS0_RDY_MASK ((0x1 << MMDC_MDMISC_CS0_RDY))
  633. #define MMDC_MDMISC_CS1_RDY_MASK ((0x1 << MMDC_MDMISC_CS1_RDY))
  634. #define MMDC_MDMISC_CK1_DEL_MASK ((0x3 << MMDC_MDMISC_CK1_DEL))
  635. #define MMDC_MDMISC_CK1_GATING_MASK ((0x1 << MMDC_MDMISC_CK1_GATING))
  636. #define MMDC_MDMISC_CALIB_PER_CS_MASK ((0x1 << MMDC_MDMISC_CALIB_PER_CS))
  637. #define MMDC_MDMISC_ADDR_MIRROR_MASK ((0x1 << MMDC_MDMISC_ADDR_MIRROR))
  638. #define MMDC_MDMISC_LHD_MASK ((0x1 << MMDC_MDMISC_LHD))
  639. #define MMDC_MDMISC_WALAT_MASK ((0x3 << MMDC_MDMISC_WALAT))
  640. #define MMDC_MDMISC_BI_MASK ((0x1 << MMDC_MDMISC_BI))
  641. #define MMDC_MDMISC_LPDDR2_S_MASK ((0x1 << MMDC_MDMISC_LPDDR2_S))
  642. #define MMDC_MDMISC_MIF3_MODE_MASK ((0x3 << MMDC_MDMISC_MIF3_MODE))
  643. #define MMDC_MDMISC_RALAT_MASK ((0x7 << MMDC_MDMISC_RALAT))
  644. #define MMDC_MDMISC_DDR_4_BANK_MASK ((0x1 << MMDC_MDMISC_DDR_4_BANK))
  645. #define MMDC_MDMISC_DDR_TYPE_MASK ((0x3 << MMDC_MDMISC_DDR_TYPE))
  646. #define MMDC_MDMISC_RST_MASK ((0x1 << MMDC_MDMISC_RST))
  647. /* MPWLGCR */
  648. #define MMDC_MPWLGCR_WL_HW_ERR_MASK ((0xf << MMDC_MPWLGCR_WL_HW_ERR))
  649. /* MDSCR */
  650. #define MMDC_MDSCR_CMD_ADDR_MSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_MSB))
  651. #define MMDC_MDSCR_MR_OP_MASK ((0xff << MMDC_MDSCR_MR_OP))
  652. #define MMDC_MDSCR_CMD_ADDR_LSB_MASK ((0xff << MMDC_MDSCR_CMD_ADDR_LSB))
  653. #define MMDC_MDSCR_MR_ADDR_MASK ((0xff << MMDC_MDSCR_MR_ADDR))
  654. #define MMDC_MDSCR_CON_REQ_MASK ((0x1 << MMDC_MDSCR_CON_REQ))
  655. #define MMDC_MDSCR_CON_ACK_MASK ((0x1 << MMDC_MDSCR_CON_ACK))
  656. #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK ((0x1 << MMDC_MDSCR_MRR_READ_DATA_VALID))
  657. #define MMDC_MDSCR_WL_EN_MASK ((0x1 << MMDC_MDSCR_WL_EN))
  658. #define MMDC_MDSCR_CMD_MASK ((0x7 << MMDC_MDSCR_CMD))
  659. #define MMDC_MDSCR_CMD_CS_MASK ((0x1 << MMDC_MDSCR_CMD_CS))
  660. #define MMDC_MDSCR_CMD_BA_MASK ((0x7 << MMDC_MDSCR_CMD_BA))
  661. /* MPZQHWCTRL */
  662. #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK ((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR))
  663. #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK ((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE))
  664. /* MPZQSWCTRL */
  665. #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK ((0x3 << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP))
  666. #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK ((0x1 << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL))
  667. #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_PD))
  668. #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL))
  669. #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK ((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL))
  670. #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_RES))
  671. #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK ((0x1 << MMDC_MPZQSWCTRL_ZQ_SW_FOR))
  672. /* MPDGCTRL0 */
  673. #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK ((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO))
  674. #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK ((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC))
  675. #define MMDC_MPDGCTRL0_DG_DIS_MASK ((0x1 << MMDC_MPDGCTRL0_DG_DIS))
  676. #define MMDC_MPDGCTRL0_HW_DG_EN_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_EN))
  677. #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK ((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR))
  678. /* MPRDDLHWCTL */
  679. #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC))
  680. #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK ((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN))
  681. #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK ((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR))
  682. /* MPWRDLHWCTL */
  683. #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC))
  684. #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK ((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN))
  685. #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK ((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR))
  686. /* MPSWDAR */
  687. #define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK ((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN))
  688. #define MMDC_MPSWDAR_SW_DUM_CMP3_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3))
  689. #define MMDC_MPSWDAR_SW_DUM_CMP2_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2))
  690. #define MMDC_MPSWDAR_SW_DUM_CMP1_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1))
  691. #define MMDC_MPSWDAR_SW_DUM_CMP0_MASK ((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0))
  692. #define MMDC_MPSWDAR_SW_DUMMY_RD_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD))
  693. #define MMDC_MPSWDAR_SW_DUMMY_WR_MASK ((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR))
  694. /* MADPCR0 */
  695. #define MMDC_MADPCR0_SBS_MASK ((0x1 << MMDC_MADPCR0_SBS))
  696. #define MMDC_MADPCR0_SBS_EN_MASK ((0x1 << MMDC_MADPCR0_SBS_EN))
  697. /* MASBS1 */
  698. #define MMDC_MASBS1_SBS_VLD_MASK ((0x1 << MMDC_MASBS1_SBS_VLD))
  699. #define MMDC_MASBS1_SBS_TYPE_MASK ((0x1 << MMDC_MASBS1_SBS_TYPE))
  700. /* MDREF */
  701. #define MMDC_MDREF_REF_CNT_MASK ((0xffff << MMDC_MDREF_REF_CNT))
  702. #define MMDC_MDREF_REF_SEL_MASK ((0x3 << MMDC_MDREF_REF_SEL))
  703. #define MMDC_MDREF_REFR_MASK ((0x7 << MMDC_MDREF_REFR))
  704. #define MMDC_MDREF_START_REF_MASK ((0x1 << MMDC_MDREF_START_REF))
  705. /* MPWLGCR */
  706. #define MMDC_MPWLGCR_HW_WL_EN_MASK ((0x1 << MMDC_MPWLGCR_HW_WL_EN))
  707. /* MPBC */
  708. #define MMDC_MPBC_BIST_DM_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DM_LP_EN))
  709. #define MMDC_MPBC_BIST_CA0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_CA0_LP_EN))
  710. #define MMDC_MPBC_BIST_DQ0_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN))
  711. #define MMDC_MPBC_BIST_DQ1_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN))
  712. #define MMDC_MPBC_BIST_DQ2_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN))
  713. #define MMDC_MPBC_BIST_DQ3_LP_EN_MASK ((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN))
  714. #define MMDC_MPBC_BIST_DQ_LP_EN_MASK ((0xf << MMDC_MPBC_BIST_DQ0_LP_EN))
  715. /* MPMUR */
  716. #define MMDC_MPMUR_FRC_MSR_MASK ((0x1 << MMDC_MPMUR_FRC_MSR))
  717. /* MPODTCTRL */
  718. #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN))
  719. #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN))
  720. #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN))
  721. #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK ((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN))
  722. /* MAPSR */
  723. #define MMDC_MAPSR_DVACK_MASK ((0x1 << MMDC_MAPSR_DVACK))
  724. #define MMDC_MAPSR_LPACK_MASK ((0x1 << MMDC_MAPSR_LPACK))
  725. #define MMDC_MAPSR_DVFS_MASK ((0x1 << MMDC_MAPSR_DVFS))
  726. #define MMDC_MAPSR_LPMD_MASK ((0x1 << MMDC_MAPSR_LPMD))
  727. /* MAARCR */
  728. #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK ((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN))
  729. /* MPZQLP2CTL */
  730. #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK ((0x7f << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS))
  731. #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK ((0xff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL))
  732. #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK ((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT))
  733. /* MDCFG3LP */
  734. #define MMDC_MDCFG3LP_tRC_LP_MASK ((0x3f << MMDC_MDCFG3LP_tRC_LP))
  735. #define MMDC_MDCFG3LP_tRCD_LP_MASK ((0xf << MMDC_MDCFG3LP_tRCD_LP))
  736. #define MMDC_MDCFG3LP_tRPpb_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPpb_LP))
  737. #define MMDC_MDCFG3LP_tRPab_LP_MASK ((0xf << MMDC_MDCFG3LP_tRPab_LP))
  738. /* MDOR */
  739. #define MMDC_MDOR_tXPR_MASK ((0xff << MMDC_MDOR_tXPR))
  740. #define MMDC_MDOR_SDE_to_RST_MASK ((0x3f << MMDC_MDOR_SDE_to_RST))
  741. #define MMDC_MDOR_RST_to_CKE_MASK ((0x3f << MMDC_MDOR_RST_to_CKE))
  742. /* MDCFG0 */
  743. #define MMDC_MDCFG0_tRFC_MASK ((0xff << MMDC_MDCFG0_tRFC))
  744. #define MMDC_MDCFG0_tXS_MASK ((0xff << MMDC_MDCFG0_tXS))
  745. #define MMDC_MDCFG0_tXP_MASK ((0x7 << MMDC_MDCFG0_tXP))
  746. #define MMDC_MDCFG0_tXPDLL_MASK ((0xf << MMDC_MDCFG0_tXPDLL))
  747. #define MMDC_MDCFG0_tFAW_MASK ((0x1f << MMDC_MDCFG0_tFAW))
  748. #define MMDC_MDCFG0_tCL_MASK ((0xf << MMDC_MDCFG0_tCL))
  749. /* MDCFG1 */
  750. #define MMDC_MDCFG1_tRCD_MASK ((0x7 << MMDC_MDCFG1_tRCD))
  751. #define MMDC_MDCFG1_tRP_MASK ((0x7 << MMDC_MDCFG1_tRP))
  752. #define MMDC_MDCFG1_tRC_MASK ((0x1f << MMDC_MDCFG1_tRC))
  753. #define MMDC_MDCFG1_tRAS_MASK ((0x1f << MMDC_MDCFG1_tRAS))
  754. #define MMDC_MDCFG1_tRPA_MASK ((0x1 << MMDC_MDCFG1_tRPA))
  755. #define MMDC_MDCFG1_tWR_MASK ((0x7 << MMDC_MDCFG1_tWR))
  756. #define MMDC_MDCFG1_tMRD_MASK ((0xf << MMDC_MDCFG1_tMRD))
  757. #define MMDC_MDCFG1_tCWL_MASK ((0x7 << MMDC_MDCFG1_tCWL))
  758. /* MDCFG2 */
  759. #define MMDC_MDCFG2_tDLLK_MASK ((0x1ff << MMDC_MDCFG2_tDLLK))
  760. #define MMDC_MDCFG2_tRTP_MASK ((0x7 << MMDC_MDCFG2_tRTP))
  761. #define MMDC_MDCFG2_tWTR_MASK ((0x7 << MMDC_MDCFG2_tWTR))
  762. #define MMDC_MDCFG2_tRRD_MASK ((0x7 << MMDC_MDCFG2_tRRD))
  763. /* MDRWD */
  764. #define MMDC_MDRWD_tDAI_MASK ((0x1fff << MMDC_MDRWD_tDAI))
  765. #define MMDC_MDRWD_RTW_SAME_MASK ((0x7 << MMDC_MDRWD_RTW_SAME))
  766. #define MMDC_MDRWD_WTR_DIFF_MASK ((0x7 << MMDC_MDRWD_WTR_DIFF))
  767. #define MMDC_MDRWD_WTW_DIFF_MASK ((0x7 << MMDC_MDRWD_WTW_DIFF))
  768. #define MMDC_MDRWD_RTW_DIFF_MASK ((0x7 << MMDC_MDRWD_RTW_DIFF))
  769. #define MMDC_MDRWD_RTR_DIFF_MASK ((0x7 << MMDC_MDRWD_RTR_DIFF))
  770. /* MDPDC */
  771. #define MMDC_MDPDC_PRCT_1_MASK ((0x7 << MMDC_MDPDC_PRCT_1))
  772. #define MMDC_MDPDC_PRCT_0_MASK ((0x7 << MMDC_MDPDC_PRCT_0))
  773. #define MMDC_MDPDC_tCKE_MASK ((0x7 << MMDC_MDPDC_tCKE))
  774. #define MMDC_MDPDC_PWDT_1_MASK ((0xf << MMDC_MDPDC_PWDT_1))
  775. #define MMDC_MDPDC_PWDT_0_MASK ((0xf << MMDC_MDPDC_PWDT_0))
  776. #define MMDC_MDPDC_SLOW_PD_MASK ((0x1 << MMDC_MDPDC_SLOW_PD))
  777. #define MMDC_MDPDC_BOTH_CS_PD_MASK ((0x1 << MMDC_MDPDC_BOTH_CS_PD))
  778. #define MMDC_MDPDC_tCKSRX_MASK ((0x7 << MMDC_MDPDC_tCKSRX))
  779. #define MMDC_MDPDC_tCKSRE_MASK ((0x7 << MMDC_MDPDC_tCKSRE))
  780. /* MDASP */
  781. #define MMDC_MDASP_CS0_END_MASK ((0x7f << MMDC_MDASP_CS0_END))
  782. /* MAEXIDR0 */
  783. #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1))
  784. #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK ((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0))
  785. /* MAEXIDR1 */
  786. #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3))
  787. #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK ((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2))
  788. /* MPWRDLCTL */
  789. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3))
  790. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2))
  791. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1))
  792. #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0))
  793. /* MPRDDLCTL */
  794. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3))
  795. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2))
  796. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1))
  797. #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK ((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0))
  798. /* MPWRDQBY0DL */
  799. #define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DM0_DEL))
  800. #define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ7_DEL))
  801. #define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ6_DEL))
  802. #define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ5_DEL))
  803. #define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ4_DEL))
  804. #define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ3_DEL))
  805. #define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ2_DEL))
  806. #define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ1_DEL))
  807. #define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK ((0x3f << MMDC_MPWRDQBY0DL_WR_DQ0_DEL))
  808. /* MPWRDQBY1DL */
  809. #define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DM1_DEL))
  810. #define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ15_DEL))
  811. #define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ14_DEL))
  812. #define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ13_DEL))
  813. #define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ12_DEL))
  814. #define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ11_DEL))
  815. #define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ10_DEL))
  816. #define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ9_DEL))
  817. #define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK ((0x3f << MMDC_MPWRDQBY1DL_WR_DQ8_DEL))
  818. /* MPWRDQBY2DL */
  819. #define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DM2_DEL))
  820. #define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ23_DEL))
  821. #define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ22_DEL))
  822. #define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ21_DEL))
  823. #define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ20_DEL))
  824. #define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ19_DEL))
  825. #define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ18_DEL))
  826. #define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ17_DEL))
  827. #define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK ((0x3f << MMDC_MPWRDQBY2DL_WR_DQ16_DEL))
  828. /* MPWRDQBY3DL */
  829. #define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DM3_DEL))
  830. #define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ31_DEL))
  831. #define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ30_DEL))
  832. #define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ29_DEL))
  833. #define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ28_DEL))
  834. #define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ27_DEL))
  835. #define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ26_DEL))
  836. #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
  837. #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
  838. #define SNVS_LPCR_DPEN (0x20)
  839. #define SNVS_LPCR_SRTC_ENV (0x1)
  840. #define SRC_BASE_ADDR CMC1_RBASE
  841. #define IRAM_BASE_ADDR OCRAM_0_BASE
  842. #define IOMUXC_BASE_ADDR IOMUXC1_RBASE
  843. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  844. #include <asm/types.h>
  845. struct fuse_word {
  846. u32 fuse;
  847. u32 rsvd[3];
  848. };
  849. struct ocotp_regs {
  850. u32 ctrl;
  851. u32 ctrl_set;
  852. u32 ctrl_clr;
  853. u32 ctrl_tog;
  854. u32 pdn;
  855. u32 rsvd0[3];
  856. u32 data;
  857. u32 rsvd1[3];
  858. u32 read_ctrl;
  859. u32 rsvd2[3];
  860. u32 read_fuse_data;
  861. u32 rsvd3[3];
  862. u32 sw_sticky;
  863. u32 rsvd4[3];
  864. u32 scs;
  865. u32 scs_set;
  866. u32 scs_clr;
  867. u32 scs_tog;
  868. u32 out_status;
  869. u32 out_status_set;
  870. u32 out_status_clr;
  871. u32 out_status_tog;
  872. u32 startword;
  873. u32 rsvd5[3];
  874. u32 version;
  875. u32 rsvd6[19];
  876. struct fuse_word mem_repair[8];
  877. u32 rsvd7[0xa8];
  878. /* fuse banks */
  879. struct fuse_bank {
  880. u32 fuse_regs[0x20];
  881. } bank[0];
  882. };
  883. struct fuse_bank1_regs {
  884. u32 lock0;
  885. u32 rsvd0[3];
  886. u32 lock1;
  887. u32 rsvd1[3];
  888. u32 lock2;
  889. u32 rsvd2[3];
  890. u32 cfg0;
  891. u32 rsvd3[3];
  892. u32 cfg1;
  893. u32 rsvd4[3];
  894. u32 cfg2;
  895. u32 rsvd5[3];
  896. u32 cfg3;
  897. u32 rsvd6[3];
  898. u32 cfg4;
  899. u32 rsvd7[3];
  900. };
  901. struct fuse_bank2_regs {
  902. struct fuse_word boot[8];
  903. };
  904. struct fuse_bank3_regs {
  905. u32 mem0;
  906. u32 rsvd0[3];
  907. u32 mem1;
  908. u32 rsvd1[3];
  909. u32 mem2;
  910. u32 rsvd2[3];
  911. u32 mem3;
  912. u32 rsvd3[3];
  913. u32 ana0;
  914. u32 rsvd4[3];
  915. u32 ana1;
  916. u32 rsvd5[3];
  917. u32 ana2;
  918. u32 rsvd6[3];
  919. u32 ana3;
  920. u32 rsvd7[3];
  921. };
  922. struct fuse_bank7_regs {
  923. u32 sjc_resp0;
  924. u32 rsvd0[3];
  925. u32 sjc_resp1;
  926. u32 rsvd1[3];
  927. u32 gp0;
  928. u32 rsvd2[3];
  929. u32 gp1;
  930. u32 rsvd3[3];
  931. u32 gp2;
  932. u32 rsvd4[3];
  933. u32 gp3;
  934. u32 rsvd5[3];
  935. u32 gp4;
  936. u32 rsvd6[3];
  937. u32 gp5;
  938. u32 rsvd7[3];
  939. };
  940. struct usbphy_regs {
  941. u32 usbphy_pwd; /* 0x000 */
  942. u32 usbphy_pwd_set; /* 0x004 */
  943. u32 usbphy_pwd_clr; /* 0x008 */
  944. u32 usbphy_pwd_tog; /* 0x00c */
  945. u32 usbphy_tx; /* 0x010 */
  946. u32 usbphy_tx_set; /* 0x014 */
  947. u32 usbphy_tx_clr; /* 0x018 */
  948. u32 usbphy_tx_tog; /* 0x01c */
  949. u32 usbphy_rx; /* 0x020 */
  950. u32 usbphy_rx_set; /* 0x024 */
  951. u32 usbphy_rx_clr; /* 0x028 */
  952. u32 usbphy_rx_tog; /* 0x02c */
  953. u32 usbphy_ctrl; /* 0x030 */
  954. u32 usbphy_ctrl_set; /* 0x034 */
  955. u32 usbphy_ctrl_clr; /* 0x038 */
  956. u32 usbphy_ctrl_tog; /* 0x03c */
  957. u32 usbphy_status; /* 0x040 */
  958. u32 reserved0[3];
  959. u32 usbphy_debug0; /* 0x050 */
  960. u32 usbphy_debug0_set; /* 0x054 */
  961. u32 usbphy_debug0_clr; /* 0x058 */
  962. u32 usbphy_debug0_tog; /* 0x05c */
  963. u32 reserved1[4];
  964. u32 usbphy_debug1; /* 0x070 */
  965. u32 usbphy_debug1_set; /* 0x074 */
  966. u32 usbphy_debug1_clr; /* 0x078 */
  967. u32 usbphy_debug1_tog; /* 0x07c */
  968. u32 usbphy_version; /* 0x080 */
  969. u32 reserved2[7];
  970. u32 usb1_pll_480_ctrl; /* 0x0a0 */
  971. u32 usb1_pll_480_ctrl_set; /* 0x0a4 */
  972. u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */
  973. u32 usb1_pll_480_ctrl_tog; /* 0x0ac */
  974. u32 reserved3[4];
  975. u32 usb1_vbus_detect; /* 0xc0 */
  976. u32 usb1_vbus_detect_set; /* 0xc4 */
  977. u32 usb1_vbus_detect_clr; /* 0xc8 */
  978. u32 usb1_vbus_detect_tog; /* 0xcc */
  979. u32 usb1_vbus_det_stat; /* 0xd0 */
  980. u32 reserved4[3];
  981. u32 usb1_chrg_detect; /* 0xe0 */
  982. u32 usb1_chrg_detect_set; /* 0xe4 */
  983. u32 usb1_chrg_detect_clr; /* 0xe8 */
  984. u32 usb1_chrg_detect_tog; /* 0xec */
  985. u32 usb1_chrg_det_stat; /* 0xf0 */
  986. u32 reserved5[3];
  987. u32 usbphy_anactrl; /* 0x100 */
  988. u32 usbphy_anactrl_set; /* 0x104 */
  989. u32 usbphy_anactrl_clr; /* 0x108 */
  990. u32 usbphy_anactrl_tog; /* 0x10c */
  991. u32 usb1_loopback; /* 0x110 */
  992. u32 usb1_loopback_set; /* 0x114 */
  993. u32 usb1_loopback_clr; /* 0x118 */
  994. u32 usb1_loopback_tog; /* 0x11c */
  995. u32 usb1_loopback_hsfscnt; /* 0x120 */
  996. u32 usb1_loopback_hsfscnt_set; /* 0x124 */
  997. u32 usb1_loopback_hsfscnt_clr; /* 0x128 */
  998. u32 usb1_loopback_hsfscnt_tog; /* 0x12c */
  999. u32 usphy_trim_override_en; /* 0x130 */
  1000. u32 usphy_trim_override_en_set; /* 0x134 */
  1001. u32 usphy_trim_override_en_clr; /* 0x138 */
  1002. u32 usphy_trim_override_en_tog; /* 0x13c */
  1003. u32 usb1_pfda_ctrl1; /* 0x140 */
  1004. u32 usb1_pfda_ctrl1_set; /* 0x144 */
  1005. u32 usb1_pfda_ctrl1_clr; /* 0x148 */
  1006. u32 usb1_pfda_ctrl1_tog; /* 0x14c */
  1007. };
  1008. struct bootrom_sw_info {
  1009. u8 reserved_1;
  1010. u8 boot_dev_instance;
  1011. u8 boot_dev_type;
  1012. u8 reserved_2;
  1013. u32 core_freq;
  1014. u32 axi_freq;
  1015. u32 ddr_freq;
  1016. u32 rom_tick_freq;
  1017. u32 reserved_3[3];
  1018. };
  1019. #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
  1020. #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140)
  1021. #endif
  1022. #endif /* _MX7ULP_REGS_H_*/