imx-regs.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. #ifndef __ASM_ARCH_IMX8M_REGS_H__
  6. #define __ASM_ARCH_IMX8M_REGS_H__
  7. #define ARCH_MXC
  8. #include <asm/mach-imx/regs-lcdif.h>
  9. #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
  10. #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
  11. #define M4_BOOTROM_BASE_ADDR 0x007E0000
  12. #define GPIO1_BASE_ADDR 0X30200000
  13. #define GPIO2_BASE_ADDR 0x30210000
  14. #define GPIO3_BASE_ADDR 0x30220000
  15. #define GPIO4_BASE_ADDR 0x30230000
  16. #define GPIO5_BASE_ADDR 0x30240000
  17. #define WDOG1_BASE_ADDR 0x30280000
  18. #define WDOG2_BASE_ADDR 0x30290000
  19. #define WDOG3_BASE_ADDR 0x302A0000
  20. #define IOMUXC_BASE_ADDR 0x30330000
  21. #define IOMUXC_GPR_BASE_ADDR 0x30340000
  22. #define OCOTP_BASE_ADDR 0x30350000
  23. #define ANATOP_BASE_ADDR 0x30360000
  24. #define CCM_BASE_ADDR 0x30380000
  25. #define SRC_BASE_ADDR 0x30390000
  26. #define GPC_BASE_ADDR 0x303A0000
  27. #define SYSCNT_RD_BASE_ADDR 0x306A0000
  28. #define SYSCNT_CMP_BASE_ADDR 0x306B0000
  29. #define SYSCNT_CTRL_BASE_ADDR 0x306C0000
  30. #define UART1_BASE_ADDR 0x30860000
  31. #define UART3_BASE_ADDR 0x30880000
  32. #define UART2_BASE_ADDR 0x30890000
  33. #define I2C1_BASE_ADDR 0x30A20000
  34. #define I2C2_BASE_ADDR 0x30A30000
  35. #define I2C3_BASE_ADDR 0x30A40000
  36. #define I2C4_BASE_ADDR 0x30A50000
  37. #define UART4_BASE_ADDR 0x30A60000
  38. #define USDHC1_BASE_ADDR 0x30B40000
  39. #define USDHC2_BASE_ADDR 0x30B50000
  40. #ifdef CONFIG_IMX8MM
  41. #define USDHC3_BASE_ADDR 0x30B60000
  42. #endif
  43. #define TZASC_BASE_ADDR 0x32F80000
  44. #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
  45. 0x30320000 : 0x32e00000
  46. #define SRC_IPS_BASE_ADDR 0x30390000
  47. #define SRC_DDRC_RCR_ADDR 0x30391000
  48. #define SRC_DDRC2_RCR_ADDR 0x30391004
  49. #define DDRC_DDR_SS_GPR0 0x3d000000
  50. #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
  51. #define DDR_CSD1_BASE_ADDR 0x40000000
  52. #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
  53. #define FEC_QUIRK_ENET_MAC
  54. #define CAAM_ARB_BASE_ADDR (0x00100000)
  55. #define CAAM_ARB_END_ADDR (0x00107FFF)
  56. #define CAAM_IPS_BASE_ADDR (0x30900000)
  57. #define CONFIG_SYS_FSL_SEC_OFFSET (0)
  58. #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
  59. CONFIG_SYS_FSL_SEC_OFFSET)
  60. #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
  61. #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
  62. CONFIG_SYS_FSL_JR0_OFFSET)
  63. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  64. #if !defined(__ASSEMBLY__)
  65. #include <asm/types.h>
  66. #include <linux/bitops.h>
  67. #include <stdbool.h>
  68. #define GPR_TZASC_EN BIT(0)
  69. #define GPR_TZASC_EN_LOCK BIT(16)
  70. #define SRC_SCR_M4_ENABLE_OFFSET 3
  71. #define SRC_SCR_M4_ENABLE_MASK BIT(3)
  72. #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
  73. #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
  74. #define SRC_DDR1_ENABLE_MASK 0x8F000000UL
  75. #define SRC_DDR2_ENABLE_MASK 0x8F000000UL
  76. #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
  77. #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
  78. #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
  79. #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
  80. struct iomuxc_gpr_base_regs {
  81. u32 gpr[47];
  82. };
  83. struct ocotp_regs {
  84. u32 ctrl;
  85. u32 ctrl_set;
  86. u32 ctrl_clr;
  87. u32 ctrl_tog;
  88. u32 timing;
  89. u32 rsvd0[3];
  90. u32 data;
  91. u32 rsvd1[3];
  92. u32 read_ctrl;
  93. u32 rsvd2[3];
  94. u32 read_fuse_data;
  95. u32 rsvd3[3];
  96. u32 sw_sticky;
  97. u32 rsvd4[3];
  98. u32 scs;
  99. u32 scs_set;
  100. u32 scs_clr;
  101. u32 scs_tog;
  102. u32 crc_addr;
  103. u32 rsvd5[3];
  104. u32 crc_value;
  105. u32 rsvd6[3];
  106. u32 version;
  107. u32 rsvd7[0xdb];
  108. /* fuse banks */
  109. struct fuse_bank {
  110. u32 fuse_regs[0x10];
  111. } bank[0];
  112. };
  113. #ifdef CONFIG_IMX8MP
  114. struct fuse_bank0_regs {
  115. u32 lock;
  116. u32 rsvd0[7];
  117. u32 uid_low;
  118. u32 rsvd1[3];
  119. u32 uid_high;
  120. u32 rsvd2[3];
  121. };
  122. #else
  123. struct fuse_bank0_regs {
  124. u32 lock;
  125. u32 rsvd0[3];
  126. u32 uid_low;
  127. u32 rsvd1[3];
  128. u32 uid_high;
  129. u32 rsvd2[7];
  130. };
  131. #endif
  132. struct fuse_bank1_regs {
  133. u32 tester3;
  134. u32 rsvd0[3];
  135. u32 tester4;
  136. u32 rsvd1[3];
  137. u32 tester5;
  138. u32 rsvd2[3];
  139. u32 cfg0;
  140. u32 rsvd3[3];
  141. };
  142. struct fuse_bank3_regs {
  143. u32 mem_trim0;
  144. u32 rsvd0[3];
  145. u32 mem_trim1;
  146. u32 rsvd1[3];
  147. u32 mem_trim2;
  148. u32 rsvd2[3];
  149. u32 ana0;
  150. u32 rsvd3[3];
  151. };
  152. struct fuse_bank9_regs {
  153. u32 mac_addr0;
  154. u32 rsvd0[3];
  155. u32 mac_addr1;
  156. u32 rsvd1[11];
  157. };
  158. struct fuse_bank38_regs {
  159. u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
  160. u32 rsvd0[3];
  161. u32 ana_trim2;
  162. u32 rsvd1[3];
  163. u32 ana_trim3;
  164. u32 rsvd2[3];
  165. u32 ana_trim4;
  166. u32 rsvd3[3];
  167. };
  168. struct fuse_bank39_regs {
  169. u32 ana_trim5;
  170. u32 rsvd[15];
  171. };
  172. #ifdef CONFIG_IMX8MQ
  173. struct anamix_pll {
  174. u32 audio_pll1_cfg0;
  175. u32 audio_pll1_cfg1;
  176. u32 audio_pll2_cfg0;
  177. u32 audio_pll2_cfg1;
  178. u32 video_pll_cfg0;
  179. u32 video_pll_cfg1;
  180. u32 gpu_pll_cfg0;
  181. u32 gpu_pll_cfg1;
  182. u32 vpu_pll_cfg0;
  183. u32 vpu_pll_cfg1;
  184. u32 arm_pll_cfg0;
  185. u32 arm_pll_cfg1;
  186. u32 sys_pll1_cfg0;
  187. u32 sys_pll1_cfg1;
  188. u32 sys_pll1_cfg2;
  189. u32 sys_pll2_cfg0;
  190. u32 sys_pll2_cfg1;
  191. u32 sys_pll2_cfg2;
  192. u32 sys_pll3_cfg0;
  193. u32 sys_pll3_cfg1;
  194. u32 sys_pll3_cfg2;
  195. u32 video_pll2_cfg0;
  196. u32 video_pll2_cfg1;
  197. u32 video_pll2_cfg2;
  198. u32 dram_pll_cfg0;
  199. u32 dram_pll_cfg1;
  200. u32 dram_pll_cfg2;
  201. u32 digprog;
  202. u32 osc_misc_cfg;
  203. u32 pllout_monitor_cfg;
  204. u32 frac_pllout_div_cfg;
  205. u32 sscg_pllout_div_cfg;
  206. };
  207. #else
  208. struct anamix_pll {
  209. u32 audio_pll1_gnrl_ctl;
  210. u32 audio_pll1_fdiv_ctl0;
  211. u32 audio_pll1_fdiv_ctl1;
  212. u32 audio_pll1_sscg_ctl;
  213. u32 audio_pll1_mnit_ctl;
  214. u32 audio_pll2_gnrl_ctl;
  215. u32 audio_pll2_fdiv_ctl0;
  216. u32 audio_pll2_fdiv_ctl1;
  217. u32 audio_pll2_sscg_ctl;
  218. u32 audio_pll2_mnit_ctl;
  219. u32 video_pll1_gnrl_ctl;
  220. u32 video_pll1_fdiv_ctl0;
  221. u32 video_pll1_fdiv_ctl1;
  222. u32 video_pll1_sscg_ctl;
  223. u32 video_pll1_mnit_ctl;
  224. u32 reserved[5];
  225. u32 dram_pll_gnrl_ctl;
  226. u32 dram_pll_fdiv_ctl0;
  227. u32 dram_pll_fdiv_ctl1;
  228. u32 dram_pll_sscg_ctl;
  229. u32 dram_pll_mnit_ctl;
  230. u32 gpu_pll_gnrl_ctl;
  231. u32 gpu_pll_div_ctl;
  232. u32 gpu_pll_locked_ctl1;
  233. u32 gpu_pll_mnit_ctl;
  234. u32 vpu_pll_gnrl_ctl;
  235. u32 vpu_pll_div_ctl;
  236. u32 vpu_pll_locked_ctl1;
  237. u32 vpu_pll_mnit_ctl;
  238. u32 arm_pll_gnrl_ctl;
  239. u32 arm_pll_div_ctl;
  240. u32 arm_pll_locked_ctl1;
  241. u32 arm_pll_mnit_ctl;
  242. u32 sys_pll1_gnrl_ctl;
  243. u32 sys_pll1_div_ctl;
  244. u32 sys_pll1_locked_ctl1;
  245. u32 reserved2[24];
  246. u32 sys_pll1_mnit_ctl;
  247. u32 sys_pll2_gnrl_ctl;
  248. u32 sys_pll2_div_ctl;
  249. u32 sys_pll2_locked_ctl1;
  250. u32 sys_pll2_mnit_ctl;
  251. u32 sys_pll3_gnrl_ctl;
  252. u32 sys_pll3_div_ctl;
  253. u32 sys_pll3_locked_ctl1;
  254. u32 sys_pll3_mnit_ctl;
  255. u32 anamix_misc_ctl;
  256. u32 anamix_clk_mnit_ctl;
  257. u32 reserved3[437];
  258. u32 digprog;
  259. };
  260. #endif
  261. /* System Reset Controller (SRC) */
  262. struct src {
  263. u32 scr;
  264. u32 a53rcr;
  265. u32 a53rcr1;
  266. u32 m4rcr;
  267. u32 reserved1[4];
  268. u32 usbophy1_rcr;
  269. u32 usbophy2_rcr;
  270. u32 mipiphy_rcr;
  271. u32 pciephy_rcr;
  272. u32 hdmi_rcr;
  273. u32 disp_rcr;
  274. u32 reserved2[2];
  275. u32 gpu_rcr;
  276. u32 vpu_rcr;
  277. u32 pcie2_rcr;
  278. u32 mipiphy1_rcr;
  279. u32 mipiphy2_rcr;
  280. u32 reserved3;
  281. u32 sbmr1;
  282. u32 srsr;
  283. u32 reserved4[2];
  284. u32 sisr;
  285. u32 simr;
  286. u32 sbmr2;
  287. u32 gpr1;
  288. u32 gpr2;
  289. u32 gpr3;
  290. u32 gpr4;
  291. u32 gpr5;
  292. u32 gpr6;
  293. u32 gpr7;
  294. u32 gpr8;
  295. u32 gpr9;
  296. u32 gpr10;
  297. u32 reserved5[985];
  298. u32 ddr1_rcr;
  299. u32 ddr2_rcr;
  300. };
  301. #define WDOG_WDT_MASK BIT(3)
  302. #define WDOG_WDZST_MASK BIT(0)
  303. struct wdog_regs {
  304. u16 wcr; /* Control */
  305. u16 wsr; /* Service */
  306. u16 wrsr; /* Reset Status */
  307. u16 wicr; /* Interrupt Control */
  308. u16 wmcr; /* Miscellaneous Control */
  309. };
  310. struct bootrom_sw_info {
  311. u8 reserved_1;
  312. u8 boot_dev_instance;
  313. u8 boot_dev_type;
  314. u8 reserved_2;
  315. u32 core_freq;
  316. u32 axi_freq;
  317. u32 ddr_freq;
  318. u32 tick_freq;
  319. u32 reserved_3[3];
  320. };
  321. #define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
  322. 0x000009e8)
  323. #define ROM_SW_INFO_ADDR_A0 0x000009e8
  324. #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
  325. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
  326. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
  327. struct gpc_reg {
  328. u32 lpcr_bsc;
  329. u32 lpcr_ad;
  330. u32 lpcr_cpu1;
  331. u32 lpcr_cpu2;
  332. u32 lpcr_cpu3;
  333. u32 slpcr;
  334. u32 mst_cpu_mapping;
  335. u32 mmdc_cpu_mapping;
  336. u32 mlpcr;
  337. u32 pgc_ack_sel;
  338. u32 pgc_ack_sel_m4;
  339. u32 gpc_misc;
  340. u32 imr1_core0;
  341. u32 imr2_core0;
  342. u32 imr3_core0;
  343. u32 imr4_core0;
  344. u32 imr1_core1;
  345. u32 imr2_core1;
  346. u32 imr3_core1;
  347. u32 imr4_core1;
  348. u32 imr1_cpu1;
  349. u32 imr2_cpu1;
  350. u32 imr3_cpu1;
  351. u32 imr4_cpu1;
  352. u32 imr1_cpu3;
  353. u32 imr2_cpu3;
  354. u32 imr3_cpu3;
  355. u32 imr4_cpu3;
  356. u32 isr1_cpu0;
  357. u32 isr2_cpu0;
  358. u32 isr3_cpu0;
  359. u32 isr4_cpu0;
  360. u32 isr1_cpu1;
  361. u32 isr2_cpu1;
  362. u32 isr3_cpu1;
  363. u32 isr4_cpu1;
  364. u32 isr1_cpu2;
  365. u32 isr2_cpu2;
  366. u32 isr3_cpu2;
  367. u32 isr4_cpu2;
  368. u32 isr1_cpu3;
  369. u32 isr2_cpu3;
  370. u32 isr3_cpu3;
  371. u32 isr4_cpu3;
  372. u32 slt0_cfg;
  373. u32 slt1_cfg;
  374. u32 slt2_cfg;
  375. u32 slt3_cfg;
  376. u32 slt4_cfg;
  377. u32 slt5_cfg;
  378. u32 slt6_cfg;
  379. u32 slt7_cfg;
  380. u32 slt8_cfg;
  381. u32 slt9_cfg;
  382. u32 slt10_cfg;
  383. u32 slt11_cfg;
  384. u32 slt12_cfg;
  385. u32 slt13_cfg;
  386. u32 slt14_cfg;
  387. u32 pgc_cpu_0_1_mapping;
  388. u32 cpu_pgc_up_trg;
  389. u32 mix_pgc_up_trg;
  390. u32 pu_pgc_up_trg;
  391. u32 cpu_pgc_dn_trg;
  392. u32 mix_pgc_dn_trg;
  393. u32 pu_pgc_dn_trg;
  394. u32 lpcr_bsc2;
  395. u32 pgc_cpu_2_3_mapping;
  396. u32 lps_cpu0;
  397. u32 lps_cpu1;
  398. u32 lps_cpu2;
  399. u32 lps_cpu3;
  400. u32 gpc_gpr;
  401. u32 gtor;
  402. u32 debug_addr1;
  403. u32 debug_addr2;
  404. u32 cpu_pgc_up_status1;
  405. u32 mix_pgc_up_status0;
  406. u32 mix_pgc_up_status1;
  407. u32 mix_pgc_up_status2;
  408. u32 m4_mix_pgc_up_status0;
  409. u32 m4_mix_pgc_up_status1;
  410. u32 m4_mix_pgc_up_status2;
  411. u32 pu_pgc_up_status0;
  412. u32 pu_pgc_up_status1;
  413. u32 pu_pgc_up_status2;
  414. u32 m4_pu_pgc_up_status0;
  415. u32 m4_pu_pgc_up_status1;
  416. u32 m4_pu_pgc_up_status2;
  417. u32 a53_lp_io_0;
  418. u32 a53_lp_io_1;
  419. u32 a53_lp_io_2;
  420. u32 cpu_pgc_dn_status1;
  421. u32 mix_pgc_dn_status0;
  422. u32 mix_pgc_dn_status1;
  423. u32 mix_pgc_dn_status2;
  424. u32 m4_mix_pgc_dn_status0;
  425. u32 m4_mix_pgc_dn_status1;
  426. u32 m4_mix_pgc_dn_status2;
  427. u32 pu_pgc_dn_status0;
  428. u32 pu_pgc_dn_status1;
  429. u32 pu_pgc_dn_status2;
  430. u32 m4_pu_pgc_dn_status0;
  431. u32 m4_pu_pgc_dn_status1;
  432. u32 m4_pu_pgc_dn_status2;
  433. u32 res[3];
  434. u32 mix_pdn_flg;
  435. u32 pu_pdn_flg;
  436. u32 m4_mix_pdn_flg;
  437. u32 m4_pu_pdn_flg;
  438. u32 imr1_core2;
  439. u32 imr2_core2;
  440. u32 imr3_core2;
  441. u32 imr4_core2;
  442. u32 imr1_core3;
  443. u32 imr2_core3;
  444. u32 imr3_core3;
  445. u32 imr4_core3;
  446. u32 pgc_ack_sel_pu;
  447. u32 pgc_ack_sel_m4_pu;
  448. u32 slt15_cfg;
  449. u32 slt16_cfg;
  450. u32 slt17_cfg;
  451. u32 slt18_cfg;
  452. u32 slt19_cfg;
  453. u32 gpc_pu_pwrhsk;
  454. u32 slt0_cfg_pu;
  455. u32 slt1_cfg_pu;
  456. u32 slt2_cfg_pu;
  457. u32 slt3_cfg_pu;
  458. u32 slt4_cfg_pu;
  459. u32 slt5_cfg_pu;
  460. u32 slt6_cfg_pu;
  461. u32 slt7_cfg_pu;
  462. u32 slt8_cfg_pu;
  463. u32 slt9_cfg_pu;
  464. u32 slt10_cfg_pu;
  465. u32 slt11_cfg_pu;
  466. u32 slt12_cfg_pu;
  467. u32 slt13_cfg_pu;
  468. u32 slt14_cfg_pu;
  469. u32 slt15_cfg_pu;
  470. u32 slt16_cfg_pu;
  471. u32 slt17_cfg_pu;
  472. u32 slt18_cfg_pu;
  473. u32 slt19_cfg_pu;
  474. };
  475. struct pgc_reg {
  476. u32 pgcr;
  477. u32 pgpupscr;
  478. u32 pgpdnscr;
  479. u32 pgsr;
  480. u32 pgauxsw;
  481. u32 pgdr;
  482. };
  483. #endif
  484. #endif