clock.h 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan at nxp.com>
  6. */
  7. #include <linux/bitops.h>
  8. #ifdef CONFIG_IMX8MQ
  9. #include <asm/arch/clock_imx8mq.h>
  10. #elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || \
  11. defined(CONFIG_IMX8MP)
  12. #include <asm/arch/clock_imx8mm.h>
  13. #else
  14. #error "Error no clock.h"
  15. #endif
  16. #define MHZ(X) ((X) * 1000000UL)
  17. /* Mainly for compatible to imx common code. */
  18. enum mxc_clock {
  19. MXC_ARM_CLK = 0,
  20. MXC_IPG_CLK,
  21. MXC_CSPI_CLK,
  22. MXC_ESDHC_CLK,
  23. MXC_ESDHC2_CLK,
  24. MXC_ESDHC3_CLK,
  25. MXC_I2C_CLK,
  26. MXC_UART_CLK,
  27. MXC_QSPI_CLK,
  28. };
  29. enum clk_slice_type {
  30. CORE_CLOCK_SLICE,
  31. BUS_CLOCK_SLICE,
  32. IP_CLOCK_SLICE,
  33. AHB_CLOCK_SLICE,
  34. IPG_CLOCK_SLICE,
  35. CORE_SEL_CLOCK_SLICE,
  36. DRAM_SEL_CLOCK_SLICE,
  37. };
  38. enum root_pre_div {
  39. CLK_ROOT_PRE_DIV1 = 0,
  40. CLK_ROOT_PRE_DIV2,
  41. CLK_ROOT_PRE_DIV3,
  42. CLK_ROOT_PRE_DIV4,
  43. CLK_ROOT_PRE_DIV5,
  44. CLK_ROOT_PRE_DIV6,
  45. CLK_ROOT_PRE_DIV7,
  46. CLK_ROOT_PRE_DIV8,
  47. };
  48. enum root_post_div {
  49. CLK_ROOT_POST_DIV1 = 0,
  50. CLK_ROOT_POST_DIV2,
  51. CLK_ROOT_POST_DIV3,
  52. CLK_ROOT_POST_DIV4,
  53. CLK_ROOT_POST_DIV5,
  54. CLK_ROOT_POST_DIV6,
  55. CLK_ROOT_POST_DIV7,
  56. CLK_ROOT_POST_DIV8,
  57. CLK_ROOT_POST_DIV9,
  58. CLK_ROOT_POST_DIV10,
  59. CLK_ROOT_POST_DIV11,
  60. CLK_ROOT_POST_DIV12,
  61. CLK_ROOT_POST_DIV13,
  62. CLK_ROOT_POST_DIV14,
  63. CLK_ROOT_POST_DIV15,
  64. CLK_ROOT_POST_DIV16,
  65. CLK_ROOT_POST_DIV17,
  66. CLK_ROOT_POST_DIV18,
  67. CLK_ROOT_POST_DIV19,
  68. CLK_ROOT_POST_DIV20,
  69. CLK_ROOT_POST_DIV21,
  70. CLK_ROOT_POST_DIV22,
  71. CLK_ROOT_POST_DIV23,
  72. CLK_ROOT_POST_DIV24,
  73. CLK_ROOT_POST_DIV25,
  74. CLK_ROOT_POST_DIV26,
  75. CLK_ROOT_POST_DIV27,
  76. CLK_ROOT_POST_DIV28,
  77. CLK_ROOT_POST_DIV29,
  78. CLK_ROOT_POST_DIV30,
  79. CLK_ROOT_POST_DIV31,
  80. CLK_ROOT_POST_DIV32,
  81. CLK_ROOT_POST_DIV33,
  82. CLK_ROOT_POST_DIV34,
  83. CLK_ROOT_POST_DIV35,
  84. CLK_ROOT_POST_DIV36,
  85. CLK_ROOT_POST_DIV37,
  86. CLK_ROOT_POST_DIV38,
  87. CLK_ROOT_POST_DIV39,
  88. CLK_ROOT_POST_DIV40,
  89. CLK_ROOT_POST_DIV41,
  90. CLK_ROOT_POST_DIV42,
  91. CLK_ROOT_POST_DIV43,
  92. CLK_ROOT_POST_DIV44,
  93. CLK_ROOT_POST_DIV45,
  94. CLK_ROOT_POST_DIV46,
  95. CLK_ROOT_POST_DIV47,
  96. CLK_ROOT_POST_DIV48,
  97. CLK_ROOT_POST_DIV49,
  98. CLK_ROOT_POST_DIV50,
  99. CLK_ROOT_POST_DIV51,
  100. CLK_ROOT_POST_DIV52,
  101. CLK_ROOT_POST_DIV53,
  102. CLK_ROOT_POST_DIV54,
  103. CLK_ROOT_POST_DIV55,
  104. CLK_ROOT_POST_DIV56,
  105. CLK_ROOT_POST_DIV57,
  106. CLK_ROOT_POST_DIV58,
  107. CLK_ROOT_POST_DIV59,
  108. CLK_ROOT_POST_DIV60,
  109. CLK_ROOT_POST_DIV61,
  110. CLK_ROOT_POST_DIV62,
  111. CLK_ROOT_POST_DIV63,
  112. CLK_ROOT_POST_DIV64,
  113. };
  114. struct clk_root_map {
  115. enum clk_root_index entry;
  116. enum clk_slice_type slice_type;
  117. u32 slice_index;
  118. u8 src_mux[8];
  119. };
  120. struct ccm_ccgr {
  121. u32 ccgr;
  122. u32 ccgr_set;
  123. u32 ccgr_clr;
  124. u32 ccgr_tog;
  125. };
  126. struct ccm_root {
  127. u32 target_root;
  128. u32 target_root_set;
  129. u32 target_root_clr;
  130. u32 target_root_tog;
  131. u32 misc;
  132. u32 misc_set;
  133. u32 misc_clr;
  134. u32 misc_tog;
  135. u32 nm_post;
  136. u32 nm_post_root_set;
  137. u32 nm_post_root_clr;
  138. u32 nm_post_root_tog;
  139. u32 nm_pre;
  140. u32 nm_pre_root_set;
  141. u32 nm_pre_root_clr;
  142. u32 nm_pre_root_tog;
  143. u32 db_post;
  144. u32 db_post_root_set;
  145. u32 db_post_root_clr;
  146. u32 db_post_root_tog;
  147. u32 db_pre;
  148. u32 db_pre_root_set;
  149. u32 db_pre_root_clr;
  150. u32 db_pre_root_tog;
  151. u32 reserved[4];
  152. u32 access_ctrl;
  153. u32 access_ctrl_root_set;
  154. u32 access_ctrl_root_clr;
  155. u32 access_ctrl_root_tog;
  156. };
  157. struct ccm_reg {
  158. u32 reserved_0[4096];
  159. struct ccm_ccgr ccgr_array[192];
  160. u32 reserved_1[3328];
  161. struct ccm_root core_root[5];
  162. u32 reserved_2[352];
  163. struct ccm_root bus_root[12];
  164. u32 reserved_3[128];
  165. struct ccm_root ahb_ipg_root[4];
  166. u32 reserved_4[384];
  167. struct ccm_root dram_sel;
  168. struct ccm_root core_sel;
  169. u32 reserved_5[448];
  170. struct ccm_root ip_root[78];
  171. };
  172. enum enet_freq {
  173. ENET_25MHZ = 0,
  174. ENET_50MHZ,
  175. ENET_125MHZ,
  176. };
  177. #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
  178. { \
  179. .clk = (_rate), \
  180. .alt_root_sel = (_m), \
  181. .alt_pre_div = (_p), \
  182. .apb_root_sel = (_s), \
  183. .apb_pre_div = (_k), \
  184. }
  185. struct dram_bypass_clk_setting {
  186. ulong clk;
  187. int alt_root_sel;
  188. enum root_pre_div alt_pre_div;
  189. int apb_root_sel;
  190. enum root_pre_div apb_pre_div;
  191. };
  192. #define CCGR_CLK_ON_MASK 0x03
  193. #define CLK_SRC_ON_MASK 0x03
  194. #define CLK_ROOT_ON BIT(28)
  195. #define CLK_ROOT_OFF (0 << 28)
  196. #define CLK_ROOT_ENABLE_MASK BIT(28)
  197. #define CLK_ROOT_ENABLE_SHIFT 28
  198. #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
  199. /* For SEL, only use 1 bit */
  200. #define CLK_ROOT_SRC_MUX_MASK 0x07000000
  201. #define CLK_ROOT_SRC_MUX_SHIFT 24
  202. #define CLK_ROOT_SRC_0 0x00000000
  203. #define CLK_ROOT_SRC_1 0x01000000
  204. #define CLK_ROOT_SRC_2 0x02000000
  205. #define CLK_ROOT_SRC_3 0x03000000
  206. #define CLK_ROOT_SRC_4 0x04000000
  207. #define CLK_ROOT_SRC_5 0x05000000
  208. #define CLK_ROOT_SRC_6 0x06000000
  209. #define CLK_ROOT_SRC_7 0x07000000
  210. #define CLK_ROOT_PRE_DIV_MASK (0x00070000)
  211. #define CLK_ROOT_PRE_DIV_SHIFT 16
  212. #define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
  213. #define CLK_ROOT_AUDO_SLOW_EN 0x1000
  214. #define CLK_ROOT_AUDO_DIV_MASK 0x700
  215. #define CLK_ROOT_AUDO_DIV_SHIFT 0x8
  216. #define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
  217. /* For CORE: mask is 0x7; For IPG: mask is 0x3 */
  218. #define CLK_ROOT_POST_DIV_MASK 0x3f
  219. #define CLK_ROOT_CORE_POST_DIV_MASK 0x7
  220. #define CLK_ROOT_IPG_POST_DIV_MASK 0x3
  221. #define CLK_ROOT_POST_DIV_SHIFT 0
  222. #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
  223. #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
  224. #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
  225. #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
  226. #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
  227. #define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
  228. #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
  229. #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
  230. void dram_pll_init(ulong pll_val);
  231. void dram_enable_bypass(ulong clk_val);
  232. void dram_disable_bypass(void);
  233. u32 imx_get_fecclk(void);
  234. u32 imx_get_uartclk(void);
  235. int clock_init(void);
  236. void init_clk_usdhc(u32 index);
  237. void init_uart_clk(u32 index);
  238. void init_wdog_clk(void);
  239. unsigned int mxc_get_clock(enum mxc_clock clk);
  240. int clock_enable(enum clk_ccgr_index index, bool enable);
  241. int clock_root_enabled(enum clk_root_index clock_id);
  242. int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
  243. enum root_post_div post_div, enum clk_root_src clock_src);
  244. int clock_set_target_val(enum clk_root_index clock_id, u32 val);
  245. int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
  246. int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
  247. int clock_get_postdiv(enum clk_root_index clock_id,
  248. enum root_post_div *post_div);
  249. int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
  250. void mxs_set_lcdclk(u32 base_addr, u32 freq);
  251. int set_clk_qspi(void);
  252. void enable_ocotp_clk(unsigned char enable);
  253. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
  254. int set_clk_enet(enum enet_freq type);
  255. int set_clk_eqos(enum enet_freq type);
  256. void hab_caam_clock_enable(unsigned char enable);