imx8mn-beacon-som.dtsi 11 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright 2020 Compass Electronics Group, LLC
  4. */
  5. / {
  6. aliases {
  7. rtc0 = &rtc;
  8. rtc1 = &snvs_rtc;
  9. spi0 = &flexspi;
  10. };
  11. usdhc1_pwrseq: usdhc1_pwrseq {
  12. compatible = "mmc-pwrseq-simple";
  13. pinctrl-names = "default";
  14. pinctrl-0 = <&pinctrl_usdhc1_gpio>;
  15. reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  16. clocks = <&osc_32k>;
  17. clock-names = "ext_clock";
  18. post-power-on-delay-ms = <80>;
  19. };
  20. memory@40000000 {
  21. device_type = "memory";
  22. reg = <0x0 0x40000000 0 0x80000000>;
  23. };
  24. };
  25. &A53_0 {
  26. cpu-supply = <&buck2_reg>;
  27. };
  28. &A53_1 {
  29. cpu-supply = <&buck2_reg>;
  30. };
  31. &A53_2 {
  32. cpu-supply = <&buck2_reg>;
  33. };
  34. &A53_3 {
  35. cpu-supply = <&buck2_reg>;
  36. };
  37. /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
  38. &a53_opp_table {
  39. opp-1200000000 {
  40. opp-microvolt = <950000>;
  41. };
  42. };
  43. &ddrc {
  44. operating-points-v2 = <&ddrc_opp_table>;
  45. ddrc_opp_table: opp-table {
  46. compatible = "operating-points-v2";
  47. opp-25M {
  48. opp-hz = /bits/ 64 <25000000>;
  49. };
  50. opp-100M {
  51. opp-hz = /bits/ 64 <100000000>;
  52. };
  53. opp-800M {
  54. opp-hz = /bits/ 64 <800000000>;
  55. };
  56. };
  57. };
  58. &fec1 {
  59. pinctrl-names = "default";
  60. pinctrl-0 = <&pinctrl_fec1>;
  61. phy-mode = "rgmii-id";
  62. phy-handle = <&ethphy0>;
  63. phy-supply = <&buck6_reg>;
  64. phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  65. fsl,magic-packet;
  66. status = "okay";
  67. mdio {
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. ethphy0: ethernet-phy@0 {
  71. compatible = "ethernet-phy-ieee802.3-c22";
  72. reg = <0>;
  73. };
  74. };
  75. };
  76. &flexspi {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_flexspi>;
  79. status = "okay";
  80. flash@0 {
  81. reg = <0>;
  82. #address-cells = <1>;
  83. #size-cells = <1>;
  84. compatible = "jedec,spi-nor";
  85. spi-max-frequency = <80000000>;
  86. spi-tx-bus-width = <4>;
  87. spi-rx-bus-width = <4>;
  88. };
  89. };
  90. &i2c1 {
  91. clock-frequency = <400000>;
  92. pinctrl-names = "default";
  93. pinctrl-0 = <&pinctrl_i2c1>;
  94. status = "okay";
  95. pmic@4b {
  96. compatible = "rohm,bd71847";
  97. reg = <0x4b>;
  98. pinctrl-names = "default";
  99. pinctrl-0 = <&pinctrl_pmic>;
  100. interrupt-parent = <&gpio1>;
  101. interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  102. rohm,reset-snvs-powered;
  103. regulators {
  104. buck1_reg: BUCK1 {
  105. regulator-name = "buck1";
  106. regulator-min-microvolt = <700000>;
  107. regulator-max-microvolt = <1300000>;
  108. regulator-boot-on;
  109. regulator-always-on;
  110. regulator-ramp-delay = <1250>;
  111. };
  112. buck2_reg: BUCK2 {
  113. regulator-name = "buck2";
  114. regulator-min-microvolt = <700000>;
  115. regulator-max-microvolt = <1300000>;
  116. regulator-boot-on;
  117. regulator-always-on;
  118. regulator-ramp-delay = <1250>;
  119. rohm,dvs-run-voltage = <1000000>;
  120. rohm,dvs-idle-voltage = <900000>;
  121. };
  122. buck3_reg: BUCK3 {
  123. // BUCK5 in datasheet
  124. regulator-name = "buck3";
  125. regulator-min-microvolt = <700000>;
  126. regulator-max-microvolt = <1350000>;
  127. regulator-boot-on;
  128. regulator-always-on;
  129. };
  130. buck4_reg: BUCK4 {
  131. // BUCK6 in datasheet
  132. regulator-name = "buck4";
  133. regulator-min-microvolt = <3000000>;
  134. regulator-max-microvolt = <3300000>;
  135. regulator-boot-on;
  136. regulator-always-on;
  137. };
  138. buck5_reg: BUCK5 {
  139. // BUCK7 in datasheet
  140. regulator-name = "buck5";
  141. regulator-min-microvolt = <1605000>;
  142. regulator-max-microvolt = <1995000>;
  143. regulator-boot-on;
  144. regulator-always-on;
  145. };
  146. buck6_reg: BUCK6 {
  147. // BUCK8 in datasheet
  148. regulator-name = "buck6";
  149. regulator-min-microvolt = <800000>;
  150. regulator-max-microvolt = <1400000>;
  151. regulator-boot-on;
  152. regulator-always-on;
  153. };
  154. ldo1_reg: LDO1 {
  155. regulator-name = "ldo1";
  156. regulator-min-microvolt = <1600000>;
  157. regulator-max-microvolt = <3300000>;
  158. regulator-boot-on;
  159. regulator-always-on;
  160. };
  161. ldo2_reg: LDO2 {
  162. regulator-name = "ldo2";
  163. regulator-min-microvolt = <800000>;
  164. regulator-max-microvolt = <900000>;
  165. regulator-boot-on;
  166. regulator-always-on;
  167. };
  168. ldo3_reg: LDO3 {
  169. regulator-name = "ldo3";
  170. regulator-min-microvolt = <1800000>;
  171. regulator-max-microvolt = <3300000>;
  172. regulator-boot-on;
  173. regulator-always-on;
  174. };
  175. ldo4_reg: LDO4 {
  176. regulator-name = "ldo4";
  177. regulator-min-microvolt = <900000>;
  178. regulator-max-microvolt = <1800000>;
  179. regulator-boot-on;
  180. regulator-always-on;
  181. };
  182. ldo6_reg: LDO6 {
  183. regulator-name = "ldo6";
  184. regulator-min-microvolt = <900000>;
  185. regulator-max-microvolt = <1800000>;
  186. regulator-boot-on;
  187. regulator-always-on;
  188. };
  189. };
  190. };
  191. };
  192. &i2c3 {
  193. clock-frequency = <400000>;
  194. pinctrl-names = "default";
  195. pinctrl-0 = <&pinctrl_i2c3>;
  196. status = "okay";
  197. eeprom@50 {
  198. compatible = "microchip,24c64", "atmel,24c64";
  199. pagesize = <32>;
  200. read-only; /* Manufacturing EEPROM programmed at factory */
  201. reg = <0x50>;
  202. };
  203. rtc: rtc@51 {
  204. compatible = "nxp,pcf85263";
  205. reg = <0x51>;
  206. };
  207. };
  208. &uart1 {
  209. pinctrl-names = "default";
  210. pinctrl-0 = <&pinctrl_uart1>;
  211. assigned-clocks = <&clk IMX8MN_CLK_UART1>;
  212. assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
  213. uart-has-rtscts;
  214. status = "okay";
  215. bluetooth {
  216. compatible = "brcm,bcm43438-bt";
  217. shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  218. host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  219. device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
  220. clocks = <&osc_32k>;
  221. max-speed = <4000000>;
  222. clock-names = "extclk";
  223. };
  224. };
  225. &usdhc1 {
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&pinctrl_usdhc1>;
  230. bus-width = <4>;
  231. non-removable;
  232. cap-power-off-card;
  233. pm-ignore-notify;
  234. keep-power-in-suspend;
  235. mmc-pwrseq = <&usdhc1_pwrseq>;
  236. status = "okay";
  237. brcmf: bcrmf@1 {
  238. reg = <1>;
  239. compatible = "brcm,bcm4329-fmac";
  240. pinctrl-names = "default";
  241. pinctrl-0 = <&pinctrl_wlan>;
  242. interrupt-parent = <&gpio2>;
  243. interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  244. interrupt-names = "host-wake";
  245. };
  246. };
  247. &usdhc3 {
  248. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  249. pinctrl-0 = <&pinctrl_usdhc3>;
  250. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  251. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  252. bus-width = <8>;
  253. non-removable;
  254. status = "okay";
  255. };
  256. &wdog1 {
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&pinctrl_wdog>;
  259. fsl,ext-reset-output;
  260. status = "okay";
  261. };
  262. &iomuxc {
  263. pinctrl_fec1: fec1grp {
  264. fsl,pins = <
  265. MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  266. MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  267. MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  268. MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  269. MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  270. MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  271. MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  272. MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  273. MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  274. MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  275. MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  276. MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  277. MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  278. MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  279. MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
  280. >;
  281. };
  282. pinctrl_i2c1: i2c1grp {
  283. fsl,pins = <
  284. MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  285. MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  286. >;
  287. };
  288. pinctrl_i2c3: i2c3grp {
  289. fsl,pins = <
  290. MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  291. MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  292. >;
  293. };
  294. pinctrl_flexspi: flexspigrp {
  295. fsl,pins = <
  296. MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
  297. MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
  298. MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
  299. MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
  300. MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
  301. MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
  302. >;
  303. };
  304. pinctrl_pmic: pmicirqgrp {
  305. fsl,pins = <
  306. MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
  307. >;
  308. };
  309. pinctrl_uart1: uart1grp {
  310. fsl,pins = <
  311. MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
  312. MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
  313. MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
  314. MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
  315. MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
  316. MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
  317. MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
  318. MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
  319. >;
  320. };
  321. pinctrl_usdhc1_gpio: usdhc1gpiogrp {
  322. fsl,pins = <
  323. MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
  324. >;
  325. };
  326. pinctrl_usdhc1: usdhc1grp {
  327. fsl,pins = <
  328. MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
  329. MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
  330. MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
  331. MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
  332. MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
  333. MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
  334. >;
  335. };
  336. pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
  337. fsl,pins = <
  338. MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
  339. MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
  340. MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
  341. MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
  342. MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
  343. MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
  344. >;
  345. };
  346. pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
  347. fsl,pins = <
  348. MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
  349. MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
  350. MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
  351. MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
  352. MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
  353. MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
  354. >;
  355. };
  356. pinctrl_usdhc3: usdhc3grp {
  357. fsl,pins = <
  358. MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
  359. MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  360. MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  361. MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  362. MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  363. MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  364. MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  365. MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  366. MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  367. MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  368. MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  369. >;
  370. };
  371. pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
  372. fsl,pins = <
  373. MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
  374. MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  375. MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  376. MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  377. MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  378. MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  379. MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  380. MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  381. MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  382. MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  383. MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  384. >;
  385. };
  386. pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
  387. fsl,pins = <
  388. MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
  389. MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  390. MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  391. MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  392. MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  393. MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  394. MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  395. MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  396. MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  397. MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  398. MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  399. >;
  400. };
  401. pinctrl_wdog: wdoggrp {
  402. fsl,pins = <
  403. MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  404. >;
  405. };
  406. pinctrl_wlan: wlangrp {
  407. fsl,pins = <
  408. MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
  409. >;
  410. };
  411. };